|Publication number||US4348640 A|
|Application number||US 06/190,682|
|Publication date||Sep 7, 1982|
|Filing date||Sep 25, 1980|
|Priority date||Sep 25, 1980|
|Publication number||06190682, 190682, US 4348640 A, US 4348640A, US-A-4348640, US4348640 A, US4348640A|
|Inventors||Steven J. Clendening|
|Original Assignee||Rockwell International Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (30), Classifications (8), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to digital clock dividers.
The present invention arose in conjunction with the development of a multiplexer wherein three digital streams were multiplexed together onto a single high speed line. At the demultiplexed end, a synchronous one-third rate clock was needed to demultiplex the high speed data into three streams at one-third the high speed rate. The high speed clock was symmetric, and the divide by three divider circuit also had to have a symmetric output. That is, the output had to have a 50% duty cycle, with the output clock signal having a high state 50% of the time, and a low state the remaining 50% of the time.
Divide by three digital clock dividers are known, but do not have a symmetric output. One alternative is to generate a signal of twice the clock rate frequency and then perform a divide by six operation. This alternative is objectionable however because it requires too much hardware and logic operation, particularly at the higher, doubled rate. Another alternative is the use of a phase locked loop operating at one-third the fundamental frequency of the clock. This is basically an analog technique, however, and would require a large amount of hardware.
The present invention provides an all digital clock divider circuit which receives clock pulses of frequency F, divides by three, and outputs symmetrical pulses of frequency 1/3F. A divide by one and one-half circuit clocks a divide by two flip-flop resulting in a symmetrical divide by three output.
The divide by one and one-half circuit receives clock pulses of frequency F and generates a plurality of staggered nonsymmetrical pulses of frequency 1/3F, each having a duty cycle of 33%. The clock pulses are gated against two of the staggered pulse streams to provide a pulse stream with frequency 2/3F. This pulse stream clocks a divide by two flip-flop which outputs symmetrical pulses of frequency 1/3F.
FIG. 1 is a circuit diagram of a divider circuit constructed in accordance with the invention.
FIG. 2 is a truth table for a JK flip-flop.
FIG. 3 is a timing diagram illustrating operation of the circuit of FIG. 1.
FIG. 1 shows a divide by three digital clock divider circuit 10 providing a symmetrical output. Circuit 10 includes a divide by one and one-half circuit 12, and divide by two means 14. Circuit 12 receives symmetrical input clock pulses of frequency F at input 16 and reduces or divides the rate thereof by one and one-half to yield a pulse stream of frequency 2/3F at output 18. Divide by two means 14 is preferably a type D flip-flop 20 clocked by the signal on line 18, with its Q output fed back on line 22 to its D input. The Q output on line 24 provides symmetrical pulses of frequency 1/3F.
Divide by one and one-half circuit 12 includes a pair of JK flip-flops 26 and 28, each of which is clocked at its C input by the clock pulses of frequency F from input 16. The Q output of flip-flop 26 is connected to the J input of flip-flop 28, and the Q output of flip-flop 28 is connected via return line 30 to the J input of flip-flop 26. The K input of each flip-flop is tied low.
A NOR gate 32 receives its inputs from the Q outputs of flip-flops 26 and 28. A first AND gate 34 has one input connected to the output of NOR gate 32, and its second input receiving inverted clock pulses from logic means 36 providing inverted and non-inverted outputs. This logic means may be an AND gate 38 with one input tied high and the other input receiving clock pulses of frequency F from input 16. The AND gate 38 has a pair of outputs, one of which is the inversion of the other. If desired, delay means such as another gate 40 may be provided, for example, another AND gate with one of its inputs tied high. AND gate 42 has one input connected to the Q output of flip-flop 28, and receives clock pulses of frequency F at its other input. Gates 34 and 42 have their outputs connected in parallel to a common connection 18 to the clock input of flip-flop 20.
FIG. 2 shows the truth table for a JK flip-flop for the reader's convenience. FIG. 3 illustrates operation of the circuit of FIG. 1, wherein the Q output of flip-flop 26 is designated signal pulse stream S1, the Q output of flip-flop 28 is designated signal pulse stream S2, the output of gate 32 is designated signal pulse stream S3, the combined output of parallel gates 34 and 42 on line 18 is designated signal pulse stream S4, and the Q output of flip-flop 20 on line 24 is designated signal pulse stream S5.
As seen in FIG. 2, the S1 pulses output from flip-flop 26 have a frequency of 1/3F and are nonsymmetrical with a duty cycle of substantially 33%. Pulses S2 and S3 output from flip-flop 28 and gate 32, respectively, also have a frequency of 1/3F and a nonsymmetrical duty cycle of 33%. Pulses S1, S2 and S3 are not aligned, but rather are staggered such that the duty portion of S2 immediately follows the duty portion of S1, and the duty portion of S3 immediately follows the duty portion of S2, etc. The pair of gates 34 and 42 gate the clock pulses of frequency F against pulse streams S2 and S3.
Gate 42 outputs a pulse during the first half of the duty portion of a cycle of S2. Gate 34 outputs a pulse during the second half of the duty portion of a cycle of S3. This results in pulses S4 of frequency 2/3F on line 18 with a duty cycle of substantially 33%. These 2/3F pulses S4 clock flip-flop 20 to provide symmetrical signal pulse stream S5 of frequency 1/3F, having a duty cycle of substantially 50%.
Circuit 10 may be used in any system requiring a divide by three circuit. The circuit may be implemented using any integrated circuit family, depending upon the frequency at which the divide operation is required to operate. In one system, a symmetrical output at 24 with a 50%+/-5% duty cycle was desired from a 90 MHz input clock 16. Circuit 10 easily satisfied these requirements. For input speeds over 100 MHz, ECL type integrated circuits are preferred.
It is recognized that various modifications are possible within the scope of the appended claims.
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|U.S. Classification||377/48, 377/47|
|International Classification||H03K21/08, H03K23/50|
|Cooperative Classification||H03K23/505, H03K21/08|
|European Classification||H03K21/08, H03K23/50B2|
|Sep 16, 1991||AS||Assignment|
Owner name: ALCATEL NETWORK SYSTEM INC.,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:ROCKWELL INTERNATIONAL CORPORAITON, A DE CORP.;REEL/FRAME:005834/0511
Effective date: 19910828
Owner name: ALCATEL NETWORK SYSTEM INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROCKWELL INTERNATIONAL CORPORAITON;REEL/FRAME:005834/0511
Effective date: 19910828