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Publication numberUS4392212 A
Publication typeGrant
Application numberUS 06/206,131
Publication dateJul 5, 1983
Filing dateNov 12, 1980
Priority dateNov 12, 1979
Also published asEP0028916A2, EP0028916A3
Publication number06206131, 206131, US 4392212 A, US 4392212A, US-A-4392212, US4392212 A, US4392212A
InventorsKiyoshi Miyasaka, Mitsuo Higuchi
Original AssigneeFujitsu Limited
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor memory device with decoder for chip selection/write in
US 4392212 A
Abstract
A semiconductor memory device includes in its chip a decoder circuit which receives external selection signals for selecting a memory chip. The decoder circuit performs the selection of the memory chip in accordance with a logic corresponding to the combination of the external selection signals. The selection logic can be changed by the user of the semiconductor device.
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Claims(12)
What is claimed is:
1. A semiconductor memory device for receiving a plurality of external selection signals in which a semiconductor memory chip of said device is selected in accordance with a predetermined combination of the external selection signals, said device comprising:
a semiconductor memory chip; and
a decoder circuit for receiving said external selection signals and provided in said semiconductor memory device, said decoder circuit selecting said semiconductor memory chip in accordance with a logic corresponding to the predetermined combination of said external selection signals, said logic capable of being changed by the user of said semiconductor memory device.
2. A semiconductor memory device for receiving a plurality of external selection signals, having a writing-in mode and a chip selection mode in which a semiconductor memory chip of said device is selected in accordance with a predetermined combination of the external selection signals, said device comprising:
a semiconductor memory chip;
a control circuit for receiving said external selection signals and producing a first output signal and its inversion in the writing-in mode and a second output signal and its inversion in the chip selection mode; and
a decoder circuit for receiving said first and second output signals and their inversions for writing into said semiconductor memory chip or selecting said semiconductor memory chip;
wherein said control circuit and said decoder circuit are provided in said semiconductor memory device, data is written into said semiconductor memory chip in response to the writing-in mode and said first output signal and its inversion to said decoder circuit, and said semiconductor memory chip is selected in response to the chip selection mode and applying said second output signal and its inversion to said decoder circuit.
3. A semiconductor memory device as defined in claim 2, wherein said control circuit comprises:
an inverter circuit including a plurality of transistors; and
an output control circuit for receiving a variable gate voltage and including a plurality of transistors, the gates of each transistor connected to receive said variable gate voltage.
4. A semiconductor memory device as defined in claim 2, wherein said decoder circuit comprises control circuits for receiving a variable gate voltage, each control circuit includes a plurality of transistors, the gates of each transistor operatively connected to receive said variable gate voltage.
5. A semiconductor memory device as defined in claim 3 or 4, wherein said variable gate voltage is high in response to the writing-in mode, and is zero in response to the chip selection mode.
6. A semiconductor memory device having a plurality of memory cell groups, each having selected and non-selected states, said device comprising:
means for selecting said memory cell groups and for receiving a plurality of external memory cell select signals having a plurality of input signal combinations, each select signal having active and inactive states, said selecting and receiving means having a plurality of outputs correspondingly, connected to said plurality of memory cell groups said outputs vary selectively in response to said plurality of input signal combinations, select predetermined corresponding memory cell groups and place in the non-selected state, the remainder of said memory cell groups; and
means for allowing the user of said semiconductor memory device to change said predetermined corresponding memory cell group selected in response to each one of said plurality of said input signal combinations.
7. A semiconductor memory device having a write-in mode and a chip selection mode, a plurality of memory cell groups each having selected and non-selected states, said device comprising:
decoder circuit for receiving a relatively high power supply voltage and a relatively low power supply voltage, having a plurality of outputs correspondingly, operatively connected to said plurality of memory cell groups, for selecting said memory cell groups, said memory cell groups being selected in accordance with said plurality of input signal combinations; and,
control circuit for receiving a relatively high power supply voltage and a relatively low power supply voltage, and for receiving external memory cell select signals having a plurality of input signal combinations, each select signal having active and inactive states comprising a plurality of input signal combinations, said control circuit having a first output signal and its inversion for application to said decoder circuit varying in response to said plurality of input combinations and said writing-in mode, and a second output signal and its inversion for application to said decoder circuit varying in response to said plurality of input signal combinations and said chip selection mode; and
wherein the writing-in of data into said semiconductor memory device is enabled by said first output signal and its inversion and the selection of said semiconductor memory device is enabled by said second output signal at its inversion.
8. A semiconductor memory device according to claim 2 or 7, wherein said control circuit comprises:
an inversion circuit for receiving one of said plurality of external memory select signals, and having a first and a second output, said inversion circuit including
a group of depletion type enhancement type inverters including a plurality of enhancement type transistors and a plurality of depletion type transistors, the drains of said plurality of enhancement type transistors are correspondingly connected to the sources of said plurality of depletion type transistors and the gate and source of each said plurality of depletion type transistors are connected together, the drain of each of said plurality of depletion type transistors is connected to a relatively low voltage supply and the sources of said plurality of enhancement type transistors are connected to ground, the gate of each of said plurality of enhancement type transistors being the input for each of said inverters and the drain source junction of each inverter being the output of said inverter, and wherein said inverters are connected in series; and
an output control circuit including
a plurality of depletion type transistors, a plurality of enhancement type transistors, wherein the drains of said plurality of depletion type transistors are connected to said inversion circuit, the gate of each depletion type transistor is operatively connected to a first variable gate voltage supply and the gate of each enhancement type transistor is operatively connected to a second variable gate voltage supply, the drains of said plurality of enhancement type transistor is operatively connected to a relatively high supply voltage and the sources of said plurality of enhancement type transistors are connected to corresponding sources of said depletion type transistors and operatively to said decoder circuit.
9. A semiconductor memory device according to claim 2 or 7, wherein said decoder circuit further comprises:
first control circuit comprising a plurality of depletion type transistors connected such that at least one pair of series connected depletion type transistors is formed, wherein the drain of a first transistor of said pair is operatively connected to a relatively low supply voltage, the gate of said first transistor is operatively connected to the source of said first transistor and to the drain of the second transistor of said pair, the gate of said second transistor is operatively connected to a first variable gate voltage supply, and the source of said second transistor is operatively connected to said decoder means; and
second control circuit comprising at least one enhancement type transistor wherein the rate of said enhancement type transistor is operatively connected to a second variable gate voltage supply, the drain of said enhancement type transistor is operatively connected to a high supply voltage, and the source of said enhancement type transistor is operatively connected to the source of said second transistor of said depletion type transistor pair.
10. A semiconductor memory device according to claim 2 or 7, wherein said decoder circuit further comprises:
a plurality of double gate transistors connected in parallel pairs, such that the drains of said double gate transistors are operatively connected together, the source of each double gate transistor is operatively connected to ground, and the gates of said parallel pairs are operatively connected to said control circuit for receiving external selection signals.
11. A semiconductor memory device according to claim 10, wherein said decoder circuit further comprises:
an output inversion circuit comprising a series connection of an enhancement type transistor and a depletion type transistor,
wherein the gate and source of said depletion type transistor are operatively connected to the drain of said enhancement type transistor, the gate of said enhancement type transistor is operatively connected to said drains of said double gate transistors, the source of said enhancement type transistor is operatively connected to ground and, the drain of said depletion type transistor is operatively connected to a relatively low supply voltage.
12. A semiconductor memory device according to claim 2 or 7, wherein said device further comprises an output buffer circuit including
first transistor with its drain correspondingly, operatively connected to said memory cell group;
second transistor with its drain correspondingly, operatively connected to said memory cell group and with its gate operatively connected to the gate of said first transistor and operatively connected to said decoder circuit;
third transistor with its gate operatively connected to said drain of said second transistor, the source of said third transistor is operatively connected to the sources of said first and second transistors and to ground; and
fourth transistor with its gate operatively connected to said drain of said first transistor, with its source operatively connected to the drain of said third transistor, and with its drain operatively connected to a relatively low supply voltage.
Description
BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device which provides chip selection means. The semiconductor memory device of the present invention is in the form of a ROM, an EPROM, a PROM, an EAROM or a RAM.

In the system which uses a plurality of memory chips, it is necessary to select the desired memory chip by means of address signal supplied to the system.

In the prior art systems illustrated in FIGS. 1A and 1B, each of the chips CH-1, CH-2, CH-3 and CH-4 provides a chip selection terminal CS or chip selection terminals CS1 (CS1) and CS2 (CS2). The chips of FIG. 1B are of the Mask ROM type. The chip selection logic is determined in the wafer processing stage. The chip selection signal SEL which occupies the higher bit portions of the address signal ADR is supplied to the external decoder circuit in FIG. 1A and the chip selection terminals CS1 (CS1) and CS2 (CS2) in FIG. 1B.

The disadvantage of the prior art system of FIG. 1A is that an external decoder circuit DEC is required to generate from signal SEL the signals to select the desired chip.

The disadvantage of the prior art system of FIG. 1B is that it is impossible to change the select condition of the signals applied to the chip selection terminals CS1 (CS1) and CS2 (CS2), once they are selected at wafer processing.

The present invention eliminates the disadvantages in the prior art semiconductor memory systems described above.

SUMMARY OF THE INVENTION

The present invention presents a semiconductor memory device in which a memory chip is selected out in accordance with the logic of external selection signals. The semiconductor memory device is characterized by a decoder circuit on the memory chip for receving the external selection signals for selecting a memory chip. The decoder circuit selects a memory chip in accordance with a logic corresponding to the combination of external selection signals. The selected combination can be changed by the user of the semiconductor memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate prior art semiconductor memory device chip selection systems,

FIG. 2 illustrates a semiconductor memory device embodying the present invention,

FIGS. 3A and 3B illustrate the control circuits used in the device of FIG. 2, and,

FIG. 4 is a table indicating a manner of cell selection in the device of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor memory device embodying the present invention is illustrated in FIG. 2. The semiconductor memory device of FIG. 2 is an EPROM type. The control circuits 7 and 8 for producing the chip selection signals S1, S1, S2 and S2 are illustrated in FIGS. 3A and 3B. These signals are applied to the gates of the double gate FAMOS FETs 312, 313, 314 and 315 in the device of FIG. 2.

Control circuit 7 of FIG. 3A comprises depletion type load FETs 101, 103 and 105 connected to a voltage source Vcc (e.g., 5 volts), and enhancement type driver FETs 102, 104 and 106, a depletion type FET 107, an enhancement type FET 108, a depletion type FET 109, an enhancement type FET 110 connected to a voltage source Vpp (e.g. 25 volt).

The structure of control circuit 8 of FIG. 3B is identical to that of the control circuit 7 of FIG. 3A.

In the writing-in mode, the potential of the signal PRG is HIGH (e.g. 25 volts) and the potential of the signal PRG is LOW (0 volt). Accordingly, the potentials of the signals S1 and S1 are HIGH or LOW in accordance with the potential of the signal SEL1. The HIGH potential of the signals S1 and S1 is equal to the HIGH potential of the signal PRG (e.g. 25 volts), minus the threshold voltage of the FET 108 or FET 110. The LOW potential of the signals S1 and S1 is zero volt. In the chip-selection mode, the potential of the signal PRG is LOW (0 volt) and the potential of the signal PRG is HIGH (e.g. 5 volts). Accordingly, the potentials of the signals S1 and S1 are HIGH (e.g. 5 volts) or low (0 volt) in accordance with the potential of the signal SEL1.

The semiconductor memory device of FIG. 2 comprises a NOR gate circuit portion 6, an inverter circuit portion 5, an output buffer portion 4, a sense circuit 3, a column gate 2 and memory Cells No. 1. The NOR gate circuit portion 6 comprises double gate FAMOS type FEts 312, 313, 314 and 315, an FET 311, an FET 323 and an FET 316.

The inverter circuit portion 5 comprises FETs 317 and 318. The output buffer portion 4 comprises FETs 319, 320, 321 and 322. The output signal Sl of the inverter circuit portion 5 is applied to an input terminal of the output buffer portion 4.

In the NOR gate circuit portion 6, the drains of the FETs 312, 313, 314 and 315 are series connected to the voltage sources Vcc through FETs 323 and 311, and to voltage source Vpp through FET 316. In the writing-in mode, the potential of the signal PRG is HIGH (e.g. 25 volts) and the potential of the signal PRG is LOW (0 volt). In the chip selection mode, the potential of the signal PRG is LOW (0 volt) and the potential of the signal PRG is HIGH (e.g. 5 volts). The writing-in of the chip selection logic is usually carried out simultaneously with the writing-in of the information to the memory. The potentials of the signals SEL1 and SEL2 are set so that when in the chip selection mode, the memory cell in question is selected when the signals SEL1 and SEL2 assume potentials. The potentials applied during the writing-in mode of the signals SEL1 and SEL2 must be filed constant while the writing-in of the information into the memory is carried out.

A HIGH potential of a signal SEL1 and the LOW potential of the signal SEL2 are used to realize the chip selection logic in which the memory chip 1 is selected by the high potential of SEL1 signal and the LOW potential of SEL2 signal. When this condition occurs in the writing-in mode, the potential of the signals PRG becomes HIGH (e.g. 25 volts) and the potential of the signal PRG becomes LOW (0 volt). Accordingly, the potentials of the signals S1 and S2 become HIGH, that is 25 volts minus the threshold voltage of the FET 110 or FET 208. Also, the potentials of the signals S1 and S2 become LOW (0 volt). Electrons are injected into the floating gates of the FETs 312 and 315, in accordance with the well-known operative characteristics of the floating gate type EPROM, due to the application of a HIGH (approximately 20 volts) voltage to the drains of the FETs whose gate potentials are HIGH. As a result, the threshold voltages of FETs 312 and 315 are caused to shift to a positive value of, for example, 8 volts. No electrons are injected into the floating gates of the FETs 313 and 314 whose gate potentials are LOW. Therefore, the threshold voltages of the FETs 313 and 314 are unchanged and are remain at the original value of, for example, 2 volts.

After a chip selection logic is written into the NOR gate circuit portion 6 with the aid of control circuits 7 and 8 of FIGS. 3A and 3B, the data stored in the Cells No. 1 is read out as the output signal Sout at the output terminal of the output buffer circuit 4 only when the predetermined levels of SEL1 and SEL2 are applied to the gates of FETs 102 and 202. When the potential of the signal SEL1 is HIGH and the potential of the signal SEL2 is LOW, the potentials of the signals S1 and S2 are HIGH (e.g. 5 volts) and the potentials of the signals S1 and S2 are LOW (0 volt), and all of the FETs 312, 313, 314 and 315 are brought to the cut-off state, because the thread voltages of the FETs 312 and 315 are higher than the HIGH applied gate potential (e.g. 5 volts). Thus, the potential of the signal Sl is LOW (0 volt), and both FET 319 and FET 320 are brought to the cut-off state. Accordingly, the output signal Sout which corresponds to the information stored in the memory cells 1 is obtained.

When the potential condition of the signals SEL1 and SEL2 is other than the above assumed condition, at least one of the potentials of the signals S1 and S2 is HIGH (e.g. 5 volts), and at least one of the FETs 313 314 is in the ON state. Thus, the potential of the signal Sl is HIGH (e.g. 5 volts), and FETs 319 and 320 are in the ON state and the FETs 321 and 322 are in the cut-off state. Accordingly, no output signal Sout is obtained.

Similarly, the chip selection logic will be written into the chips so that the Cells No. 2 are selected under the condition that both the selection signals SEL1 and SEL2 are in HIGH state, the Cells No. 3 are selected under the condition that both the selection signals SEL1 and SEL2 are in LOW state, and the Cells No. 4 are selected under the condition that the selection signal SEL1 is in LOW state and the selection signal SEL2 is in HIGH state. The manner of cell selection described above is tabulated in FIG. 4.

Thus, if the chip selection logic has been stored in the device of FIG. 2, the data in the memory cells in question can be read out by applying the signals SEL1 and SEL2 which correspond to the higher bit portions of the address signal, without providing external decoder circuits.

The erasure of the chip selection logic stored in the device of FIG. 2 is carried out by means of, for example, the irradiation of the ultra-violet ray, simultaneously with the erasure of the data stored in the memory cells. In this case, electrons stored in the floating gates in the FAMOS type FETs 312 through 315 are eliminated by the ultra-violet irradiation. Therefore, it is possible to set a new logic state of the FETs of the NOR gate circuit portion 6 when data is next written into the Cells Nos. 1 through 4. Thus, changing the active logic state of the FETs of the NOR gate circuit portion 6 is possible.

If it is desired that one of the Cells Nos. 1 through 4 is always selected, as in the case of the so-called "DON'T CARE" selection, such selection can be achieved by bringing all of the FETs 312, 313, 314 and 315 to the inoperative state by effecting the writing-in twice with a HIGH and a LOW level signal applied at the SEL1 and SEL2 terminals.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3969706 *Oct 8, 1974Jul 13, 1976Mostek CorporationDynamic random access memory misfet integrated circuit
US4200919 *Dec 5, 1978Apr 29, 1980The United States Of America As Represented By The Secretary Of The NavyApparatus for expanding the memory of a mini-computer system
DE2136771A1 *Jul 22, 1971Feb 1, 1973Siemens AgNach dem dynamischen prinzip arbeitende schaltungsanordnung aus mos-transistoren fuer die decodierung der adressen fuer einen mos-speicher
Non-Patent Citations
Reference
1 *Hession et al., IBM Tech. Disc. Bul., vol. 21, No. 4, 9/78, pp. 1563-1564, "Chip Select Technique for Multi-Chip Decoding".
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4649521 *Nov 26, 1984Mar 10, 1987Fujitsu LimitedProgrammable read-only memory (PROM) device having reduced programming voltage capability
US6018787 *Jan 2, 1998Jan 25, 2000Canon Kabushiki KaishaSystem for generating chip select signals based on coded and uncoded address signals
US7289386 *Jul 1, 2005Oct 30, 2007Netlist, Inc.Memory module decoder
US7532537Jan 19, 2006May 12, 2009Netlist, Inc.Memory module with a circuit providing load isolation and memory domain translation
US7580312Jul 31, 2006Aug 25, 2009Metaram, Inc.Power saving system and method for use with a plurality of memory circuits
US7581127Oct 20, 2006Aug 25, 2009Metaram, Inc.Interface circuit system and method for performing power saving operations during a command-related latency
US7590796Sep 20, 2006Sep 15, 2009Metaram, Inc.System and method for power management in memory systems
US7599205Mar 25, 2008Oct 6, 2009Metaram, Inc.Methods and apparatus of stacking DRAMs
US7609567Jul 31, 2006Oct 27, 2009Metaram, Inc.System and method for simulating an aspect of a memory circuit
US7619912Sep 27, 2007Nov 17, 2009Netlist, Inc.Memory module decoder
US7636274Mar 20, 2009Dec 22, 2009Netlist, Inc.Memory module with a circuit providing load isolation and memory domain translation
US7710754 *Aug 22, 2007May 4, 2010Qimonda North America Corp.Method of simple chip select for memory subsystems
US7724589Jul 31, 2006May 25, 2010Google Inc.System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US7730338Apr 29, 2008Jun 1, 2010Google Inc.Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US7761724Apr 29, 2008Jul 20, 2010Google Inc.Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US7822910 *Aug 22, 2007Oct 26, 2010Qimonda North America Corp.Method of flexible memory segment assignment using a single chip select
US7864627Oct 12, 2009Jan 4, 2011Netlist, Inc.Memory module decoder
US7881150Dec 2, 2009Feb 1, 2011Netlist, Inc.Circuit providing load isolation and memory domain translation for memory module
US7916574Nov 29, 2010Mar 29, 2011Netlist, Inc.Circuit providing load isolation and memory domain translation for memory module
US8019589Oct 30, 2007Sep 13, 2011Google Inc.Memory apparatus operable to perform a power-saving operation
US8041881Jun 12, 2007Oct 18, 2011Google Inc.Memory device with emulated characteristics
US8055833Dec 15, 2006Nov 8, 2011Google Inc.System and method for increasing capacity, performance, and flexibility of flash storage
US8060774Jun 14, 2007Nov 15, 2011Google Inc.Memory systems and memory modules
US8072837Dec 29, 2010Dec 6, 2011Netlist, Inc.Circuit providing load isolation and memory domain translation for memory module
US8077535Jul 31, 2006Dec 13, 2011Google Inc.Memory refresh apparatus and method
US8080874Sep 14, 2007Dec 20, 2011Google Inc.Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8081474Sep 2, 2008Dec 20, 2011Google Inc.Embossed heat spreader
US8081535Nov 24, 2010Dec 20, 2011Netlist, Inc.Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module
US8081536Feb 22, 2011Dec 20, 2011Netlist, Inc.Circuit for memory module
US8081537Jun 6, 2011Dec 20, 2011Netlist, Inc.Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module
US8089795Feb 5, 2007Jan 3, 2012Google Inc.Memory module with memory stack and interface with enhanced capabilities
US8090897Jun 12, 2007Jan 3, 2012Google Inc.System and method for simulating an aspect of a memory circuit
US8111566Nov 16, 2007Feb 7, 2012Google, Inc.Optimal channel design for memory devices for providing a high-speed memory interface
US8112266Oct 30, 2007Feb 7, 2012Google Inc.Apparatus for simulating an aspect of a memory circuit
US8130560Nov 13, 2007Mar 6, 2012Google Inc.Multi-rank partial width memory modules
US8154935Apr 28, 2010Apr 10, 2012Google Inc.Delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8169233Jun 9, 2010May 1, 2012Google Inc.Programming of DIMM termination resistance values
US8209479Oct 30, 2007Jun 26, 2012Google Inc.Memory circuit system and method
US8244971Oct 30, 2007Aug 14, 2012Google Inc.Memory circuit system and method
US8250295Jan 5, 2004Aug 21, 2012Smart Modular Technologies, Inc.Multi-rank memory module that emulates a memory module having a different number of ranks
US8280714Oct 26, 2006Oct 2, 2012Google Inc.Memory circuit simulation system and method with refresh capabilities
US8327104Nov 13, 2007Dec 4, 2012Google Inc.Adjusting the timing of signals associated with a memory system
US8335894Jul 23, 2009Dec 18, 2012Google Inc.Configurable memory system with interface circuit
US8340953Oct 26, 2006Dec 25, 2012Google, Inc.Memory circuit simulation with power saving capabilities
US8359187Jul 31, 2006Jan 22, 2013Google Inc.Simulating a different number of memory circuit devices
US8370566Oct 18, 2011Feb 5, 2013Google Inc.System and method for increasing capacity, performance, and flexibility of flash storage
US8386722Jun 23, 2008Feb 26, 2013Google Inc.Stacked DIMM memory interface
US8386833Oct 24, 2011Feb 26, 2013Google Inc.Memory systems and memory modules
US8397013Mar 27, 2008Mar 12, 2013Google Inc.Hybrid memory module
US8417870Jul 16, 2009Apr 9, 2013Netlist, Inc.System and method of increasing addressable memory space on a memory board
US8438328Feb 14, 2009May 7, 2013Google Inc.Emulation of abstracted DIMMs using abstracted DRAMs
US8446781Mar 2, 2012May 21, 2013Google Inc.Multi-rank partial width memory modules
US8516185Apr 15, 2010Aug 20, 2013Netlist, Inc.System and method utilizing distributed byte-wise buffers on a memory module
US8516188Nov 1, 2011Aug 20, 2013Netlist, Inc.Circuit for memory module
US8566516Oct 30, 2007Oct 22, 2013Google Inc.Refresh management of memory modules
US8566556Dec 30, 2011Oct 22, 2013Google Inc.Memory module with memory stack and interface with enhanced capabilities
US8582339Jun 28, 2012Nov 12, 2013Google Inc.System including memory stacks
US8595419Jul 13, 2011Nov 26, 2013Google Inc.Memory apparatus operable to perform a power-saving operation
US8601204Jul 13, 2011Dec 3, 2013Google Inc.Simulating a refresh operation latency
US8615679Sep 14, 2012Dec 24, 2013Google Inc.Memory modules with reliability and serviceability functions
US8619452Sep 1, 2006Dec 31, 2013Google Inc.Methods and apparatus of stacking DRAMs
US8626998Aug 21, 2013Jan 7, 2014Smart Modular Technologies, Inc.Multi-rank memory module that emulates a memory module having a different number of ranks
US8631193May 17, 2012Jan 14, 2014Google Inc.Emulation of abstracted DIMMS using abstracted DRAMS
US8631220Sep 13, 2012Jan 14, 2014Google Inc.Adjusting the timing of signals associated with a memory system
US8671244Jul 13, 2011Mar 11, 2014Google Inc.Simulating a memory standard
US8675429Aug 29, 2012Mar 18, 2014Google Inc.Optimal channel design for memory devices for providing a high-speed memory interface
US8705240Sep 14, 2012Apr 22, 2014Google Inc.Embossed heat spreader
US8730670Oct 21, 2011May 20, 2014Google Inc.Embossed heat spreader
US8745321Sep 14, 2012Jun 3, 2014Google Inc.Simulating a memory standard
US8751732Sep 14, 2012Jun 10, 2014Google Inc.System and method for increasing capacity, performance, and flexibility of flash storage
US8756364Nov 1, 2011Jun 17, 2014Netlist, Inc.Multirank DDR memory modual with load reduction
US8760936May 20, 2013Jun 24, 2014Google Inc.Multi-rank partial width memory modules
US8762675Sep 14, 2012Jun 24, 2014Google Inc.Memory system for synchronous data transmission
US8773937Dec 9, 2011Jul 8, 2014Google Inc.Memory refresh apparatus and method
US8796830Sep 1, 2006Aug 5, 2014Google Inc.Stackable low-profile lead frame package
US8797779Sep 14, 2012Aug 5, 2014Google Inc.Memory module with memory stack and interface with enhanced capabilites
US8811065Sep 14, 2012Aug 19, 2014Google Inc.Performing error detection on DRAMs
Classifications
U.S. Classification365/230.06, 365/185.17, 365/185.16
International ClassificationG11C11/41, G11C17/00, G11C16/06, H03K5/151, G11C8/12, G11C11/413
Cooperative ClassificationG11C8/12, H03K5/151
European ClassificationG11C8/12, H03K5/151
Legal Events
DateCodeEventDescription
May 15, 1984CCCertificate of correction