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Publication numberUS4408305 A
Publication typeGrant
Application numberUS 06/305,830
Publication dateOct 4, 1983
Filing dateSep 28, 1981
Priority dateSep 28, 1981
Fee statusPaid
Also published asEP0090002A1, EP0090002A4, WO1983001147A1
Publication number06305830, 305830, US 4408305 A, US 4408305A, US-A-4408305, US4408305 A, US4408305A
InventorsClinton C. K. Kuo
Original AssigneeMotorola, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Memory with permanent array division capability
US 4408305 A
Abstract
A memory can be divided to provide a reduced number of accessible memory elements. By selectively causing an individual address to always assume a predetermined logic state, the number of accessible memory elements is reduced by one half. The selection as to which half is accessible is achieved by applying to an array divider circuit the individual address signal data logic state which corresponds to the predetermined logic state then applying to the array divider circuit an array divider signal. The array divider circuit subsequently provides the individual address signal at the predetermined logic state effectively reducing the number of accessible memory elements by one half.
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Claims(5)
I claim:
1. In a memory comprising:
an array of memory elements, said array divided into first and second halves; and
decoder means for selecting a memory element from the first half of said array when a first address signal is in a first logic state and for selecting a memory element from the second half of said array when the first address signal is in a second logic state;
array divider means for providing the first address signal in a selected one of said first and second logic states in response to having received an array divider signal, wherein the selection of the first or second logic state in response to the array divider signal is permanent, whereby the decoder means permanently select a memory element from only the half of said array which corresponds to the selected logic state of the first address signal.
2. The memory of claim 1 wherein the array divider means is further characterized as providing the first address signal to the decoder means at the logic state which corresponds to the logic state of a first input address signal if the array divider signal has not been received.
3. The memory of claim 2 wherein the array divider means is further characterized by the selected logic state being determined by the logic state of the first input address signal when the array divider signal is received.
4. In a memory comprising:
an array of memory elements, said array divided into first and second halves; and
decoder means for selecting a memory element from the first half of said array when a first address signal is in a first logic state and for selecting a memory element from the second half of said array when the first address signal is in a second logic state;
buffer means for providing the first address signal to the decoder means in response to receiving an input address signal, for providing the first address signal at the first logic state in response to receiving a first program signal, and for providing the first address signal at the second logic state in response to receiving a second program signal; and
programmable array divider means for providing the first program signal to the buffer means in response to the first input address signal being at the first logic state when the array divider signal is received, and for providing the second program signal to the buffer means in response to the first input address signal being at the second logic state when the array divider signal is received.
5. A memory, comprising:
an array of memory elements, said array divided into first and second halves;
decoder means for selecting a memory element from the first half of said array when a first address signal is in a first logic state and for selecting a memory element from the second half of said array when the first address signal is in a second logic state; and
a programmable address buffer for providing the first address signal in a selected one of the first and second logic states, independently of the external address, subsequent to said address buffer being programmed, said programming of the address buffer permanently selecting between the first and second logic states for the first address signal.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

Related subject matter is disclosed in the following related application filed simultaneously herewith and assigned to the assignee hereof:

1. U.S. patent application Ser. No. 306,120 entitled "Column and Row Erasable EEPROM."

2. U.S. patent application Ser. No. 306,119 entitled "EEPROM With Bulk Zero Program Capability."

Related subject matter is also disclosed in related U.S. application Ser. No. 342,040 entitled "Sense Amplifier", filed Jan. 25, 1982, and assigned to the assignee hereof.

TECHNICAL FIELD

The invention relates to memory circuits, and, more particularly, to memory circuits which can be divided so that a reduced number of addressable memory elements are accessible.

BACKGROUND ART

Memories, having a fabricated number of memory elements, are sometimes sold as havng only half of the fabricated number of memory elements being good. The purpose for doing so is to get some value from a part that would otherwise be unmarketable. Existing techniques to ensure that only the good half is accessed require a response from the user, eg., requiring the user to apply either the positive power supply (VDD) voltage or the negative power supply (VSS) voltage to an address pin. This is a disadvantage to the user because it adds a required electrical connection, which in turn complicates printed circuit board layout. There are manufacturing disadvantages as well. One disadvantage is that the half good parts must be sorted into two different categories, one for parts requiring the application of VSS and the other for parts requiring the application of VDD. Yet another disadvantage is that the half good parts cannot be sold interchangeably with other parts whose fabricated number of memory elements is the same number as the number of good memory elements of the half good parts.

Techniques exist for memories having redundant rows and/or columns for replacing rows and/or columns which have bad memory elements. Such techniques relate to decoupling selected rows and/or columns from an array and replacing them with the redundant rows and/or columns. Such techniques relate to a different problem than dividing an array of memory elements. In fact, in situations where the number of redundant rows and/or columns is insufficient, it may be desirable to apply array division techniques to sell half good, or even quarter good parts in order to get some value from otherwise unmarketable parts.

SUMMARY OF THE INVENTION

A memory, according to the invention, has the capability of being divided so that only one half of the memory elements are accessible by being addressed. The memory has an array of memory elements divided into first and second halves. A decoder circuit selects a memory element from the first half when a first address signal is in a first logic state and selects a memory element from the second half when the first address signal is in a second logic state. An array divider circuit provides the first address signal at a selected logic state in response to receiving an array divider signal. Accordingly, the decoder circuit, when selecting a memory element, will select from only the half which corresponds to the selected logic state of the first address signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an EEPROM according to a preferred embodiment of the invention.

FIG. 2 is a schematic diagram of a buffer and signal generator.

FIG. 3 is a schematic diagram of a write enable signal buffer and generator.

FIG. 4 is a schematic diagram of a chip select signal buffer and generator.

FIG. 5 is a schematic diagram of a row and column control signals generator.

FIG. 6 is a schematic diagram of an output enable signal generator.

FIG. 7 is a schematic diagram of a high voltage logic signal generator.

FIG. 8 is a schematic diagram of a high voltage control signal generator.

FIG. 9 is a schematic diagram of a data high signal generator.

FIG. 10 is a schematic diagram of a program enable signal generator.

FIG. 11 is a schematic diagram of an erase signal generator.

FIG. 12 is a schematic diagram of a source voltage generator.

FIG. 13 is a schematic diagram of a column address buffer.

FIG. 14 is a schematic diagram of a row address buffer.

FIG. 15 is a schematic diagram of an array section select buffer and generator.

FIG. 16 is a schematic diagram of a programmable address buffer.

FIG. 17 is a schematic diagram of a row decoder.

FIG. 18 is a schematic diagram of a column decoder.

FIG. 19 is a schematic diagram of a level-shifted data signal generator.

FIG. 20 is a schematic diagram of a sense amplifier.

FIG. 21 is a schematic diagram of an array structure.

DESCRIPTION OF A PREFERRED EMBODIMENT

Shown in block diagram form in FIG. 1 is an electrically erasable programmable read only memory (EEPROM) 10 constructed in accordance with the preferred embodiment of the present invention. In the illustrated form, EEPROM 10 is comprised generally of a chip enable (CE) buffer 12, a write enable (W) buffer 14, a chip select (G) buffer 16, a row enable/column enable signal (CER /CEC) generator 18, control logic 20, an X buffer and array divider 22, an X buffer 24, a Y buffer 26, an array section select buffer 28, a high voltage control signal (VPH) generator 30, an X decoder 32, a Y decoder 32, a Y decoder 34, a cell array 36, a Y gate 38, an array section gate 40, a data input buffer 42, and a sense amplifier 44. In the illustrated form, cell array 36 is comprised of 32,768 bits arranged as 128 rows by 32 columns of 8-bit word locations for a total storage capacity of 4096 8-bit data words. In the preferred embodiment, each of the cells in the cell array 36 is initially erased to a logical one state. Thereafter, individual cells comprising particular words may be selectively programmed to a logical zero state. When desired, the cells may be again erased to the logical one state.

In the preferred embodiment, EEPROM 10 is capable of operating in any of the following modes: a standby mode, a read mode, a word program mode, a bulk zero program mode, first and second word erase modes, a column erase mode, a row erase mode, and an array erase mode. In general, the operating mode of EEPROM 10 is determined by one or more of the following input signals: a chip enable signal E, a high voltage signal VPP, a write enable signal W, a bulk zero signal CT1, a chip select signal G, row address signals Ax, column address signal Ay, and data signals Dn. In the illustrated form, column address signals are A0 -A4, row address signals are A5 -A11 and data signals Dn are D0 -D7. In response to the input signals, internal control signals are typically asserted as either active high or active low. For simplicity, however, the following functional description of the EEPROM 10 will describe the functions of the internal control signals without regard to whether the signals are actually active high or active low.

The EEPROM 10 will operate in the standby mode when E is high. In this mode, all other inputs are irrelevant. In response to E being high, chip enable buffer 12 negates internal chip enable signal CE to CER /CEC generator 18 indicating that EEPROM 10 is to be in the standby mode. CER /CEC generator 18 in turn negates a row enable signal CER which disables X buffer and array divider 22 and X buffer 24. CER /CEC generator 18 also negates a column enable signal CEC which disables Y buffer 26 and array section select buffer 28. In response to negated internal chip enable signal CE, X decoder 32 keeps all of the rows disabled regardless of address input. In contrast, in response to negated internal chip enable signal CE and to signals provided by disabled Y buffer 26 and array section select buffer 28, all columns of words are selected. Y decoder 34, in response to signals provided by disabled Y buffer 26 and to negated internal control signal CE, asserts column decoder signals to Y gate 38, causing Y gate 38 to couple all columns of words to array section gate 40. Array section gate 40, in response to signals asserted by otherwise disabled array section select buffer 28, couples all of the columns of words to sense amplifier 44 for precharging. Also in response to negated internal chip enable signal CE, all outputs of sense amplifier 44 are disabled to establish a high impedance output on data I/O lines 46.

The EEPROM 10 will operate in the word program mode when E is low, G is high, W is low, CT1 is low or floating, and VPP is in a program state of the order of 20.0-22.0 volts. In the preferred form, cell array 36 has two sections comprising respective halves of the cell array 36. Y gate 38 has 2 sections, each of which couples a respective one of the sections of cell array 36 to a corresponding section of array section gate 40. In response to receiving address signals A0 -A3 via Y buffer 26, Y decoder 34 asserts a column decoder signal to Y gate 38 to couple 2 columns of words, one from each section of cell array 36, to corresponding sections of array section gate 40. In response to address signals A4, array section select buffer 28 asserts a buffered A4 signal to array section gate 40 for coupling a particular one of the sections of Y gate 38 to data input buffer 42. In response to receiving address signals A5 -A11 via X buffer 24 and X buffer and array divider 22, X decoder 32 asserts a row decoder signal to the cell array 36 to enable a particular row of words, i.e. the corresponding word location in each of the columns of words of cell array 36. Thus, an 8-bit data word comprising data signals D0 -D7 is coupled via data input buffer 42 to each of the word locations in the selected column in cell array 36 but actually stored in only that particular word location in the selected column of words which is in the enabled row.

In the preferred form, data input buffer 42 level-shifts the voltage of the received data signals D0 -D7 to a voltage sufficient to program cells in cell array 36. Accordingly, the row decoder signal, the column decoder signal, and the buffered A4 signal are similarly level shifted to an appropriate level using a high voltage control signal VPH provided by VPH generator 30 to X decoder 32, Y decoder 34, and array section select buffer 28. VPH generator 30 provides high voltage control signal VPH in response to a high voltage logic signal VPL which is generated by control logic 29 in response to appropriate input signals.

The EEPROM 10 will operate in the read mode when E is low, G is low, W is high, and CT1 is low or floating. A data word stored in a particular word location is accessed by address inputs A0 -A11 in a manner similar to that for accessing a word location when EEPROM 10 is in the word program mode, except that in the read mode the data word stored in the accessed word location is coupled from cell array 36 to sense amplifier 44 via Y gate 38 and array section gate 40. In response to receiving the accessed data word, sense amplifier 44 provides the accessed data word on data I/O line 46 as data signals D0 -D7. In the read mode, a high voltage is not required on the row decoder, column decoder and the buffered A4 signals. Accordingly, high voltage control signal VPH is not provided by VPH generator 30.

The EEPROM 10 will operate in the first word erase mode when E is low, G is high, VPP is in the program state and CT1 is low or floating. In addition, write enable signal W must be in a state which is higher than a normal logic high, for example 8.0 -22.0 volts. In this mode, a particular word location is accessed by address inputs A0 -A11 in a manner similar to that for accessing a word location when the EEPROM 10 is in the word program mode. One difference is that in the word program mode the 8-bits comprising a data word are coupled via respective bit-lines to corresponding cells at the accessed word location, whereas in the first word erase mode an erase signal EEHV generated by control logic 20 on a separate erase line is coupled to each of the cells at the accessed word location via array section gate 40 and Y gate 38 to erase all cells at the word location to a logic one. In response to a negated program enable signal PE which is generated by control logic 20, data input buffer 42 is disabled and presents a high impedance to array section gate 40.

The EEPROM 10 will operate in the second word erase mode when E is low, G is high, W is low, VPP is in the program state, and CT1 is low or floating. In addition, the data signals D0 -D7 must all be high. In this mode, the data input buffer 42 couples the data signals D0 -D7 to the control logic 20 where the all-high condition of data signals D0 -D7 is detected. In response to the all high condition of data signals D0 -D7 and to the other input signals, control logic 20 provides the EEHV signal. Thereafter, the addressed word is erased in the same manner as in the first word erase mode.

The EEPROM 10 will operate in the column erase mode when E is low, G is higher than a normal logic high, W is high, VPP is in the program state, and CT1 is low or floating. In this mode, the column of words to be erased is selected via address signals A0 -A4 in the same way as a column of words is selected in the word erase modes. However, instead of only one row being enabled, all of the rows are enabled by X decoder 32 so that all of the word locations in the selected column of words receive the erase signal EEHV. In particular, X buffer 24 and X buffer and array divider 22 are disabled from responding to address signals A5 -A11 and forced to provide steady state signals which cause X decoder 32 to select all of the rows, in response to negated row enable signal CER provided by CER /CEC generator 18 in response to a negated row control signal CR generated by control logic 20.

The EEPROM 10 will operate in the row erase mode when E is low, G is higher than a normal logic high, W is higher than a logic high, VPP is in the program state, and CT1 is low or floating. In this mode, the single row to be erased is enabled in response to address signals A5 -A11 in the same manner as a row is enabled in the word erase modes. However, in this mode all of the columns of words are simultaneously selected as in the standby mode, so that the erase signal EEHV is coupled to all of the word locations of the enabled row. One difference is that in the standby mode all bit-lines, 8-bit lines per column of words, are coupled to sense amplifier 44 for precharging, whereas in the row erase mode all of the erase lines, one for each column of words, are coupled to erase signal EEHV. Consequently, all word locations of the enabled row are erased to the logical one state.

The EEPROM 10 will operate within the array erase mode when E is low, G is higher than a normal logic high, W is low, VPP is in the program state, and CT1 is low or floating. In this mode, all of the rows are enabled in the same manner as in the column erase mode and all of the columns are selected in the same manner as in the row erase mode. In particular, both the column control signal CC and the row control signal CR are generated by control logic 20, as is erase signal EEHV. With all of the columns of words selected and all of the rows enabled, erase signal EEHV is simultaneously coupled to all of the cells in cell array 36, thereby erasing entire cell array 36 to the logical one state.

The EEPROM 10 will operate in the bulk zero mode when E is low, G is high, W is low, VPP is in the program state, CT1 is high, and the data signals D0 -D7 are all low. In this mode, all of the rows and columns of words are enabled in the same manner as in the array erase mode. In addition, control logic 20 asserts program enable signal PE to enable data buffer 42. With all rows enabled, all columns of words selected, the data input buffer 42 enabled, and data signals D0 -D7 all low, a logic zero is programmed into every cell in cell array 36.

X buffer and array divider 22, in addition to buffering row address signals A10 and A11, can be used to reduce the number of word locations which are accessible to a user by one half or one fourth. A normal characteristic of decoders which receive binary address signals is that each individual address signal received causes narrowing of selection of a word location by one half, i.e., each logic state of each individual address signal corresponds to half of an array. Accordingly, providing an address signal, such as row address signal A11, at a permanently selected logic state will cause only half of the word locations in cell array 36 to be accessible. By providing another address signal, such as row address signal A10, at a permanently selected logic state, a further one half reduction in accessible word locations will occur so that only one fourth of the word locations of cell array 36 will be accessible. Thus, for example, if it is determined during manufacture of EEPROM 10 that one or more bad cells exist in a particular portion of cell array 36, that portion can be rendered permanently inaccessible. The EEPROM 10 may then be marketed as a 16K or 8K unit, as appropriate.

In the preferred embodiment, the simultaneous application of row address signal A11 at a selected logic state and an array divider signal of approximately fifteen volts to a probe pad 46, will force X buffer and array divider 22 to thereafter internally generate buffered row address A11 in the selected logic state, in those modes in which a single row is selected. Accordingly, only a selected one half of cell array 36 will be accessible to a user. Similarly, the simultaneous application of row address signal A10 at a selected logic state and the array divider signal to probe pad 48 will force X buffer and array divider 22 to thereafter internally generate buffered address A10 in the selected logic state in those modes in which a single row is selected. Accordingly, only a selected one fourth of cell array 36 will be accessible to the user.

Shown in FIG. 2 is chip enable buffer 12 and CER /CEC generator 18. Chip enable buffer 12 generates internal chip enable signals CE and CE, with CE being the logical complement of the chip enable signal E and CE being the same logic state as chip enable signal E. CER /CEC generator 18 generates row enable signal CER and column enable signal CEC in a conventional manner in response to chip enable signal E, and to row control signal CR and column control signal CC generated by control logic 20. In the tables which accompany the circuit diagrams to facilitate understanding the relationships between inputs and outputs, "1"s and "0"s represent normal logic highs and lows, respectively, whereas "HH" represents an input signal which has a voltage higher than that of a normal logic high "1" and "HV" represents a high voltage which is at least sufficient to program a cell.

Shown in FIG. 3 is W buffer 14 which generates internal write enable signals WL, WL, WH, WH, WHH, and WHH in response to write enable signal W and internal chip enable signal Ce. The higher than a normal logic high signal HH is differentiated from a normal logic high in a conventional manner, by adjusting channel length to width ratios of the respective input and load transistors. High voltage logic signals VPL and VPL are used to enable a conventional latch so that the internal write enable signals can be held stable even if write enable signal W changes.

Shown in FIG. 4 is G buffer 16 which generates internal chip select signals GL, GL, GM, GM, WHH, and WHH in the same manner as the W buffer provides the write enable signals.

Shown in FIG. 5 is a row control signal and column control signal (CR /CC) generator 510 which generates row control signal CR and column control signal CC in response to chip enable signals CE and CE; internal wirte enable signals WL, WH, and WHH ; internal chip select signal GH ; bulk zero signal CT1; and high voltage logic signal VPL. Row control signal RR is high during the array erase, bulk zero, and row erase modes. CR /CC generator 510 is a portion of control logic 20 shown in FIG. 1.

Shown in FIG. 6 is output enable generator 610 which generates output enable signals CS and CS in response to chip select signal G and internal chip enable signal CE. High voltage logic signal VPL is used to enable a conventional latch so that output enable signals CS and CS can be held stable with changes in chip select signal G. Output enable generator 610 is a portion of control logic 20 shown in FIG. 1.

Shown in FIG. 7 is high voltage logic signal (VPL) generator 710 which generates high voltage logic signals VPL and VPL in response to high voltage signal VPP, internal chip enable signals CE and CE, internal chip select signals GL and GH, and internal write enable signal WH. Internal high voltage supply VPPI is also provided via a current limiting resistor 712 which is connected between a high voltage signal terminal 714 and an internal high voltage supply terminal 716. Voltage protection for the circuitry of the EEPROM 10 is provided by an IGFET 718 having the gate thereof connected to ground and the drain and source thereof connected to high voltage supply terminal 716. High voltage logic signal VPL is high during the word program, bulk zero program, row erase, column erase, first and second word erase, and array erase modes. High voltage logic signal generator 710 is a portion of control logic 20 of FIG. 1.

Shown in FIG. 8 is VPH generator 30 which generates high voltage control signal VPH in response to high voltage logic signals VPL and VPL. High voltage control signal VPH is capacitively boosted several volts above internal high voltage supply VPPI when VPL is high. High voltage control signal VPH is low when high voltage logic signal VPL is low.

Shown in FIG. 9 is a data high signal generator 910 which generates a data high signal DH in response to inverted data signals D0 -D7 and internal chip enable signal CE. Data high signal DH is high when all data signals G0 -D7 are high. Data high signal generator 910 is a portion of control logic 20 of FIG. 1.

Shown in FIG. 10 is a program enable signal generator 1010 which generates program enable signal PE in response to data high signal DH, internal write enable signal WL, internal chip select signal GH, internal chip enable signal CE, and high voltage logic signal VPL. Program enable signal PE is high during the first word program and bulk zero program modes.

Shown in FIG. 11 is an erase signal generator 1110 which provides erase signals EEHV and EE in response to internal chip enable signal CE; internal chip select signals CH and GHH ; data high signal DH; write enable signals WL and WHH ; high control signal VPH ; and high voltage logic signal VPL. Erase signal EEHV is at a voltage which is only a neglible amount below the voltage of internal high voltage supply VPPI during the first and second word erase, row erase, column erase, and array erase modes. Erase signal generator 1110 is a portion of control logic 20 of FIG. 1.

Shown in FIG. 12 is a source voltage generator 1210 which generates source voltage S in response to bulk zero signal CT1, program enable signal PE, high voltage logic signal VPL, high voltage control signal VPH, and internal chip enable CE. Source voltage S is at a voltage only a negligible amount above ground during the standby, read, first and second word erase, row erase, column erase, and array erase modes. Source voltage S is at a voltage only a negligible amount below the voltage of positive power supply VDD during the word program mode. Source voltage S is at a high impedance during the bulk zero program mode.

Shown in FIG. 13 is a typical column address buffer circuit 1310 which generates buffered column address signals BAn and BAn in response to a column address signal AN and column enable signal CEC. When column enable signal CEC is low, both buffered column enable signal BAn and BAn are also low. When column enable signal CEC is high, buffered column address signal BAn is the same logic state as that of column address signal An and buffered column address BAn is the opposite logic state of that of column address signal An. High voltage logic signals VPL and VPL enable a conventional latch so that the buffered column address signals can be held stable even if column address signal An changes. Y buffer 26 of FIG. 1 comprises 4 column address buffer circuits 1310 which provide buffered column address signals BA0-3 and BA0-3 in response to column address signals A0-3.

Shown in FIG. 14 is a typical row address buffer circuit 1410 which is substantially the same circuit as column address buffer circuit 1310 of FIG. 13. X buffer 24 of FIG. 1 comprises 5 row address buffer circuits 1410 which provide buffered row address signals BA5-9 and BA5-9 in response to row address signals A5-9 and row enable signal CER in the manner described for Y buffer 26 of FIG. 1.

Shown in FIG. 15 is array section select buffer 28 of FIG. 1 which generates buffered signals BA4 and BA4 in response to column address signal A4 and column enable signal CEC. One of BA4 and BA4 is selectively provided at a voltage level which is only a negligible amound below the voltage of internal high voltage supply VPPI during the first and second erase, word program, and column erase modes. In response to column enable signal CEC being low, both buffered A4 signals BA4 and BA4 are at the voltage level which is only a negligible amount below the voltage of internal power supply VPPI during row erase, array erase, and bulk zero modes, and are at a logic high during standby mode. One of buffered A4 signals BA4 and BA4 is selectively high with the other low during the read mode. High voltage logic signals VPL and VPL enable a conventional latch so that the buffered A4 signals can be held stable with changes of column address signal A4.

Shown in FIG. 16 is a buffer and array divider circuit 1610 which generates, in the absence of being programmed, a buffered address signal output in the same manner as column address buffer 1410 of FIG. 14. Buffer and array divider circuit 1610 is depicted with row address signal A11 as an input with buffered row address signals BA11 and BA11 as outputs. Buffer and array divider circuit 1610, along with a similar programmable buffer circuit which provides buffered row address signals BA10 and BA10 in response to row address signal A10, comprise X buffer and array divider 22 of FIG. 1. Buffer and array divider circuit 1610 is comprised generally of a buffer section 1612 and a programmable divider section 1614. Programmable divider section 1614 is coupled to buffer section 1612 by lines 1616, 1618, and 1620. In the absence of being programmed, programmable divider section 1614 will hold lines 1618 and 1620 to a logic low resulting in buffer and array divider circuit 1610 operating in the same manner as column address buffer 1410 of FIG. 14. If line 1618 is programmed to be a logic high, with line 1620 remaining low, buffered row address signal BA11 will be held to a logic low and buffered row address signal BA11 will be held to a logic high except when row enable signal CER is low. If line 1620 is programmed to be a logic high, with line 1618 remaining a logic low, buffered column address signal BA11 will be held to a logic low and buffered column address BA11 will be at a logic high except when row enable signal CER is a logic low in which case both buffered column address signals BA11 and BA11 will be a logic low. Line 1618 is programmed to be a logic high by applying a logic low on line 1616 and applying the array divider signal of approximately 15 volts to probe pad 46. The array divider signal is coupled to a polysilicon fuse 1622 which is consequently caused to be an open circuit. With polysilicon fuse 1622 an open circuit, line 1618 will always be a logic high. Consequently, so long as row enable signal CER is a logic high, buffered row address signal BA11 will be a logic high and buffered row address signal BA11 will be a logic low. Line 1620 is programmed to be a logic high by applying a high on line 1616 and applying the array divider signal to probe pad 46. The array divider signal is then coupled to a polysilicon resistor 1624 which is consequently caused to be an open circuit. With polysilicon fuse 1624 an open circuit, line 1620 will always be a logic high. Consequently, so long as row enable signal CER is a logic high, buffered row address signal BA11 will be a logic low and buffered row address signal BA11 will be a logic high. Row enable signal CER is a logic high in those modes in which a single row is to be selected. The buffer and array divider circuit for row address signal A10 is programmed in the same way.

Shown in FIG. 17 is a row deocder circuit 1710, which generates a row detector signal X in response to a unique combination of buffered new address signals BA5-11 or BA5-11. X decoder 32 of FIG. 1 comprises 128 row decoder circuits 1710, one for each row. A particular row address circuit 1710 is selected when all the inputs thereto are low. When selected, the row decoder circuit 1710 provides a respective row decoder signal X at a logic high during the read mode and at a voltage which is only a negligible amount below the voltage of internal high voltage supply VPPI during the word program, bulk zero, first and second word erase, column erase, row erase and array erase modes. In the modes when row enable signal CER is low, all buffered row address signals are low which in turn selects all of the row address circuits of X decoder 32, thereby enabling all of the rows.

Shown in FIG. 18 is a column decoder circuit 1810 which generates a column decoder signal y0-15 in response to a unique combination of buffered column address signals BA0-3 or BA0-3. Y decoder 34 of FIG. 1 comprises 16 column decoder circuits 1810. Column decoder circuit 1810 operates the same as row decoder circuit 1710 except each column decoder circuit 1810 selects two columns of words whereas each row decoder circuit 1710 enables only a single row. A selected column decoder circuit 1810 causes Y gate 38 of FIG. 1 to couple two columns of words to array section gate 40. In the modes when column enable signal CEC is a logic low, all buffered column address signals are a logic low thereby selecting all column decoder circuits of Y decoder 34 of FIG. 1.

Shown in FIG. 19 is a data input buffer circuit 1910 which generates a level-shifted data signal LD0-7 in response to a corresponding data signal D0-7. Data input buffer 42 comprises 8 data input buffer circuits 1910. The level-shifted data signal LD0-7 is, in the word program and bulk zero modes, inverted and level-shifted to be approximately zero volts in response to a logic high, and at a voltage which is only a negligible amount below the voltage of internal high voltage supply VPPI in response to a logic low. A high impedance is provided in the other modes. In addition, inverted data signals D0-7 are provided in response to data signals D0-7. High voltage logic signals VPL and VPL enable a conventional latch so that level-shifted data signals LD0-7 and inverted data signals LD0-7 can be held stable with changes in data signals D0-7.

Shown in FIG. 20 is a sense amplifier circuit 2010 for generating a data signal D0-7 in response to an accessed cell input CD0-7. Sense amplifier 44 of FIG. 1 comprises 8 sense amplifier circuits 2010. Output enable signals CS and CS enable sense amplifier circuits 2010 to generate data signals D0-7 during the read mode only. A high impedance is provided during other modes to prevent sense amplifier 44 of FIG. 1 from interfering with data input buffer 42 of FIG. 1.

Shown in FIG. 21 is array organization structure 2110 comprising a portion of cell array 36, a portion of array section gate 38, and a portion of Y gate 40. Portions of word locations X0 Y0, X127 Y0, X0 Y15, and X127 Y15 are shown. These word locations are from the section of cell array 36 which is selected by buffered A4 signal BA4. The cells at the word locations can be conventional floating gate insulated gate field effect transistors having selectable threshold voltages, for example approximately 5.0 volts in an erased or logical one state and approximately -5.0 volts in a programmed or logical zero state. In the standby mode, all row decoder signals X0-127 are at a logic low, all column decoder signals are at a logic high, and buffered A4 signals BA4 and BA4 at a logic high. Consequently, no rows are enabled whereas all columns are coupled to sense amplifier 44 of FIG. 1 to be precharged. In the read mode, a word location to be accessed is selected by a particular row decoder signal among row decoder signals X0-127 being at a logic high, a particular column decoder signal among column decoder signals X0-15 being at a logic high, and one of buffered A4 signals BA4 and BA4 being at a logic high. Consequently, the eight cells of a single word location are coupled to sense amplifier 44 of FIG. 1 as accessed cell input CD0-7. In the word program mode, a word location is selected in a similar manner to the read mode except the particular decoder and buffered A4 signals are provided at a voltage which is only a negligible amount below the voltage of internal high voltage supply VPPI instead of at a logic high. Level-shifted data signals LD0-7 are coupled to the cells of the selected word location for programming the selected word location. In the first and second word erase modes, a word location is selected in the same manner as in the word program mode. Erase signal EEHV at a high voltage is coupled to the gates of the cells of the selected word location for erasing the selected word location. In the array erase mode all decoder and buffered A4 signals are provided at a voltage which is only a negligible amount below the voltage of internal supply voltage VPPI so that all word locations are selected. Erase signal EEHV at a high voltage is coupled to the gates of the cells of all word locations for erasing all of the word locations. In the bulk zero mode all word locations are selected in the same way as in the array erase mode. A program signal is applied to all word locations from data input buffer 42 as level-shifted data signals LD0-7 being at a voltage which is only a negligible amount below the voltage of internal supply voltage VPPI. Consequently the cells of all word locations are programmed to a logic low. In the row erase mode all columns are selected as in the array erase mode and a particulr row is selected as in the first and second word erase modes. Erase signal EEHV is coupled to the gates of the cells of all word locations along the selected row for erasing the entire row. In the column erase mode all rows are selected as in the array erase mode and a single column is selected as in the first and second word erase modes. Erase signal EEHV is coupled to the gates of the cells of all word locations along the selected column for erasing the entire column.

While the invention has been described in a preferred embodiment it will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.

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Referenced by
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Classifications
U.S. Classification365/230.03, 365/238.5, 365/230.08, 326/105, 365/185.05
International ClassificationG11C29/00, G11C8/00, G11C8/12, G11C29/04, G11C17/00
Cooperative ClassificationG11C29/78, G11C8/12, G11C8/00
European ClassificationG11C29/78, G11C8/12, G11C8/00
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Effective date: 19810924
Feb 25, 1987FPAYFee payment
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Feb 4, 1991FPAYFee payment
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Feb 24, 1995FPAYFee payment
Year of fee payment: 12