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Publication numberUS4415992 A
Publication typeGrant
Application numberUS 06/238,177
Publication dateNov 15, 1983
Filing dateFeb 25, 1981
Priority dateFeb 25, 1981
Fee statusLapsed
Also published asDE3279274D1, EP0072845A1, EP0072845A4, EP0072845B1, WO1982002976A1
Publication number06238177, 238177, US 4415992 A, US 4415992A, US-A-4415992, US4415992 A, US4415992A
InventorsRichard H. Adlhoch
Original AssigneeMotorola, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Memory system having memory cells capable of storing more than two states
US 4415992 A
Abstract
A memory system having a plurality of memory cells each capable of storing more than two states also has a reference voltage generator which is used to determine the state stored in a selected memory cell. The plurality of memory cells are arranged in groups of columns, and in a preferred embodiment, the reference voltage generator is arranged in columns which are located between two of the groups of columns. The memory system uses voltage sensing as opposed to current sensing and therefore the only current used is to charge line capacitances. The voltage reference generator is only enabled during the period of time that a cell is being read from.
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Claims(11)
I claim:
1. A read only memory having a plurality of rows and columns, comprising: a plurality of memory cells arranged into the rows and columns, the memory cells being capable of storing more than two states; row decoder for receiving row addresses and providing a plurality of outputs, each of the outputs being coupled to a row so that when a predetermined row is addressed the predetermined row is activated; column select means coupled to each of the columns; column decoder for receiving column addresses and providing outputs to the column select means so that when a predetermined column is selected the predetermined column is coupled to an output of the column select means; a plurality of reference sources arranged in columns and rows so that a row of reference sources is enabled each time one of the plurality of rows of memory cells is enabled, the columns of reference sources being positioned in between columns of the memory cells; comparator means having a first input coupled to the output of the column select means and a second input coupled to the reference sources, the comparator means providing an output indicative of the state stored in a selected memory; and means for translating the state into a binary output.
2. The read only memory of claim 1, wherein the plurality of reference sources is one less than the number of states which each memmory cell is capable of storing.
3. The read only memory of claim 2 wherein the comparator means includes a separate comparator for each one of the plurality of reference sources.
4. The read only memory of claim 1 wherein each memory cell includes a field effect transistor connected in a source follower configuration.
5. The read only memory of claim 1 wherein the column select means includes a field effect transistor for each column.
6. The memory array of claim 1 wherein the columns having the plurality of reference sources are adjacent each other and have an equal number of memory cell columns on either side.
7. A memory array comprising a plurality of memory cells arranged in columns and rows, each memory cell being capable of storing more than two states; a plurality of references located among the memory cells and arranged in rows and columns like the memory cells; row decoder means for receiving row addresses and providing a row select signal for selecting an addressed row, the row select signal also enabling at least one reference; column select means for selecting a predetermined column; means coupled to the column select means for receiving an output from the column select means and for comparing the output against the at least one reference, the at least one reference being coupled to the means coupled to the column select means; and a translator for translating an output from the means coupled to the column select means to a digital output.
8. The memory array of claim 7 wherein the plurality of references are arranged so that all the references in a given column are the same.
9. The memory array of claim 7 wherein the columns having the plurality of references are located so as to have an equal number of memory cell columns on either side.
10. A memory array having a plurality of rows and columns of memory cells wherein the columns are divided up into groups having an equal number of columns, the memory cells each being capable of storing more than two states; a plurality of columns of reference cells located between adjacent groups of columns of memory cells, the reference cells being substantially identical in physical size to the memory cells; comparator means for receiving memory cell data comparing such data to one of the reference cells; and a translator for translating an output from the comparator means to binary data.
11. The memory array of claim 10 wherein the memory cells each being capable of storing more than two states can actually store at least four states; and the plurality of columns of reference cells being at least three columns, each column further comprising a plurality of reference cells wherein each reference cell has a field effect transistor wherein each of the columns of reference cells has transistors of different threshold voltages than the other of the columns of reference cells.
Description
CROSS REFERENCE TO RELATED APPLICATIONS

Patent application Ser. Nos. 238,183 and 238,178 are related co-pending applications by the same inventor, assigned to the same assignee, and filed on same date as the present invention.

BACKGROUND OF THE INVENTION

This invention relates, in general, to memory systems, and more particularly, to a memory system having a plurality of memory cells each capable of storing more than two states.

Solid state memories are well-known, and particularly solid state memories using metal oxide semiconductor field effect transistors. There is a continuous effort to make memory systems smaller, faster, and use less power. One way to make a memory smaller is to be able to store more information in each memory cell location. However, one of the problems with such a memory is the ability to distinguish which state is stored in a selected memory cell. Some reference source will be required, but in order to make the memory a competitive product it must remain relatively small in overall size and low in power consumption.

The present invention provides such a memory system. Each memory cell is capable of storing more than two states. The memory cells are arranged in a manner that permits them to be made relatively small in size, which results in fast operation and low power consumption. The invention is described as having memory cells capable of storing four states which provides two binary bits. It will be understood that a memory cell could be built employing the principles of the present invention having memory cells capable of storing more than four different states. The present invention also has a reference voltage generator which consumes a very minimum amount of power and is only energized when data is being read from the memory. The reference voltage generator is built in a manner to conserve silicon chip area and to maximize speed of operation of the memory.

SUMMARY OF THE INVENTION

In carrying out the above and other objects and advantages of the present invention, there is provided a memory system having a plurality of memory cells capable of storing more than two states. In order to read data out of the system and determine the stored state, a reference voltage generator is provided which generates an output only when the memory is being read from. The memory system also includes a unique sense amplifier and translator which translates the output of the sense amplifier into binary format. The voltage reference generator is arrranged in columns which are spaced among the memory cell columns in a manner which minimizes reading time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 represents a memory system in block diagram form in accordance with an embodiment of the present invention;

FIG. 2 schematically shows a portion of the memory system of FIG. 1; and

FIG. 3 illustrates in logic and block diagram form a portion of the memory system of FIG. 1.

The exemplification set out herein illustrates the preferred embodiment of the invention in one form thereof, and such exemplification is not to be construed as limiting in any manner.

DETAILED DESCRIPTION OF THE DRAWINGS

A portion of a memory array along with the peripheral circuitry required to provide a memory system is illustrated in FIG. 1. The memory system shown in FIG. 1 is capable of being integrated onto a single semiconductor chip. The memory system has a row decoder 11 which receives row address inputs and provides an output which drives a selected row 41. The row address inputs are decoded by row decoder 11 so that only the selected row 41 is enabled. Although only five row select lines 41 are illustrated, it will be understood that in an actual memory there are usually many more row select lines. Row decoder 11 will typically include drivers to drive the decoder output since the decode will have many transistors connected to its output. A column decoder 12 receives column address inputs and provides outputs for enabling the selected column select devices in column select 13 and 14. Two groups of columns are illustrated. The first group of columns is represented by columns 19, 20, 21 and 22. The dashed lines between columns 21 and 22 indicate that in an actual system many more columns than just the four illustrated would be controlled by column select 13. The second group of columns is illustrated by columns 23, 24 and 25. The dashed lines between columns 24 and 25 indicate that in an actual system many more columns would be controlled by column select 14. In a preferred embodiment, column select 13 will control the same number of columns that column select 14 controls. Located between the two groups of columns are reference columns 16, 17 and 18.

The memory system illustrated in FIG. 1 will have a plurality of memory cells 15, wherein each memory cell is capable of storing more than two states. The memory cells are more fully described in related patent application Ser. No. 238,183 which is hereby incorporated herein by reference. Voltage reference columns 16, 17 and 18 each provide a different voltage level. Since it will not be known ahead of time which state is stored in one of memory cells 15, each time a memory cell is selected the three references must be used to determine which state is stored. Each reference cell 10 will contain a single transistor which will be substantially the same size as the single transistor contained within each memory cell 15. The voltage reference generator is described more fully in related patent application Ser. No. 238,178 which is hereby incorporated herein by reference.

Reference columns 16, 17 and 18 are each directly connected to sensing circuits 42 and 43. Sensing circuit 42 has three comparators 36, 37 and 38. Sensing circuit 43 also has three comparators which are identical to each of the comparators in sensing circuit 42. Column select 13 provides an output on line 39 which is connected to each of the comparators 36, 37 and 38. Column select 14 provides an output on line 40 which is connected to each of the comparators within sensing circuit 43. Each comparator in sensing circuit 42 and 43 provides an output which is connected to a transistor or decoder 44. The operation of the sensing circuits and translator 44 will be described in greater detail hereinafter.

Translator 44 is illustrated as providing a four binary bit output. The memory system illustrated in FIG. 1, by way of example, provides a four bit output. However, it will be understood that most memories provide an eight bit output since most words contain eight bits. Those persons skilled in the art will recognize that it will be necessary to provide two more groups of columns controlled by two more column selects and each group having a sensing circuit for an eight bit output.

In a preferred embodiment, the reference columns are arranged so that approximately the same time delay will be experienced from the furthermost memory column in one group as the furthermost memory column in the next group. For example, the delay from reference column 17 to column 19 will be the same as the delay from reference column 17 to column 25 assuming that column 19 is the furthermost column away on the left hand side and column 25 is the furthermost column away on the right hand side of reference column 17. In a memory system wherein time delays are not critical then only one group of reference columns is necessary and the single group of reference columns can service as many sensing circuits as required. A memory system providing a two binary bit output would only require one sensing circuit. In such a memory system the data contained in each memory cell location could be read out individually.

All reference cells 10 in column 16 provide the same voltage, while all the reference cells in column 17 will provide the same voltage which will be different from the voltage provided by the reference cells of column 16. All the reference cells of column 18 provide the same voltage which is also different from the voltage provided by the reference cells of column 16 or 17. When a row is selected, each of columns 16, 17, and 18 will provide a reference voltage so that each time a cell or cells are read from all three of the reference voltages required will be generated. Since it was assumed that only four states are stored in any one cell, only three references are required to determine which state is stored. One of the states is assumed to represent logic signal 00 or 11 and therefore does not require a reference. The state not requiring a reference can either be represented by the highest voltage or the lowest voltage available from a memory cell.

FIG. 2 illustrates, in schematic form, portions of columns 19 and 22 of FIG. 1. Transistor 50 represents a memory storage location as do transistors 51, 52 and 53. Each of the transistors is connected in a source follower configuration having their drains connected to voltage terminal 54 and their sources connected to a column line. Transistors 50 and 52 have their sources connected to column 19 whereas transistors 51 and 53 have their sources connected to column 22. Row select line 41 is connected to the gate electrodes of transistors 50 and 51, and row select line 41' is connected to the gate electrodes of transistors 52 and 53. In the system illustrated in FIG. 1 each row line is connected to the gate electrodes of one transistor in each column that is intersected by the row select line including the voltage reference generators. Each column line has an associated parasitic capacitance. The parasitic capacitance for column 19 is illustrated by capacitor 58, and the parasitic capacitance for column 22 is illustrated by capacitor 59. Each column as well as output line 39 is connected to a voltage reference during a precharge phase. Transistor 62 connects column 19 to the voltage reference, illustrated as ground, when a precharge signal connected to its gate electrode enables transistor 62. Column 22 is coupled to ground by transistor 63 and transistor 64 couples line 39 to ground. Transistors 63 and 64 are also enabled by the precharge signal. Transistors 56 and 57 serve as column select devices. Transistor 56 couples column 19 to line 39, and transistor 57 couples column 22 to line 39. The gate electrode of transistor 56 is connected to line 60, and the gate electrode of transistor 57 is connected to line 61. Lines 60 and 61 represent output lines for column decoder 12 (shown in FIG. 1). Column select 13 and column select 14 each contain a plurality of transistors such as transistors 56 and 57. Each transistor connects one column to line 39 or line 40.

Each reference column 16, 17, and 18 will look like column 19 and 22 except that the reference columns will not have column select devices such as transistors 56 and 57. Another difference, which is not a visual difference, is that all the transistors in a given reference column 16, 17 or 18 will each have the same threshold voltage. The transistors in a memory column, such as columns 19 and 22, will most likely not all have the same threshold voltage. The threshold voltage will be adjusted to represent the state stored at a given location.

FIG. 3 shows sensing circuit 42 along with a portion of translator 44. Sensing circuit 42 has comparators 36, 37 and 38 which receive an input from line 39. Comparator 36 also receives a first reference input on column line 16, comparator 37 receives a second reference input on column line 17 and comparator 38 receives a third reference input on column line 18. The output of comparator 37 goes to an inverter 71. Inverter 71 provides an output which goes to an input of NAND gate 73 and to the input of inverter 72. The output of inverter 72 represents a binary digit shown as Bit 1. The output of comparator 36 goes to a second input of NAND gate 73. The output of NAND gate 73 goes to an input of NAND gate 74. The output of comparator 38 goes to an input of inverter 76. The output of inverter 76 goes to a second input of NAND gate 74. The output of NAND gate 74 is a binary digit shown as Bit 2. Inverters 71, 72, and 76 along with NAND gates 73 and 74 are part of translator 44 (FIG. 1).

The truth table for the circuitry illustrated in FIG. 3 is as follows:

______________________________________Memory Cell      ComparatorOutput     Output            Bit   Bit(Unknown)  C1        C2    C3      1   2______________________________________1 (highest)      0         0     0       0   02          1         0     0       0   13          1         1     0       1   04 (lowest) 1         1     1       1   1______________________________________

The left hand column of the truth table indicates the four states that can be stored in the memory cells. Since the transistor in each memory cell is connected in a source follower configuration the output from the memory cells will be a voltage. Number 1, in the left hand column, is assumed to be the highest voltage with number 4 the lowest voltage. Comparator output C1 is the output for comparator 36, comparator output C2 is the output for comparator 37, and comparator output C3 is the output for comparator 38. Through an arbitrary choice, when the highest output voltage from a memory cell is present, all the comparator outputs are zeros which represent output bits 1 and 2 as zeros. When the second highest voltage level is present in the selected memory cell then the output from comparator 36 is a logic level "1" while the output from comparators 37 and 38 are logic levels "0" which produce output Bit 1 as a logic level "0" and output Bit 2 as a logic level "1". When the third highest voltage level is present in a selected memory cell then the output of comparators 36 and 37 are logic level "1's" and the output of comparator 38 is a logic level "0" making output Bit 1 a logic level "1" and output Bit 2 a logic level "0". The lowest voltage level in a memory cell causes all the outputs from the comparators to be logic level "1's" making output Bit 1 a logic level "1" and output Bit 2 a logic level "1". From this it can be seen that the first reference voltage level provided by column line 16 can be equal to the second highest voltage level or could be some value between the first and second highest voltage levels. The second reference voltage level provided by column line 17 could be equal to the third highest voltage level or some voltage level between voltage levels 2 and 3. The third reference voltage level provided by column line 18 could be equal to the lowest voltage level or some value between the third and fourth voltage levels.

By now it should be appreciated that there has been provided a unique memory system having a plurality of memory cells which are capable of storing more than two states. The memory system includes a plurality of references which are used to determine a state stored in a selected memory cell. The memory system is arranged in such a manner to result in a small memory which consumes a minimum amount of power and operates with minimum time delay. Each of the reference voltages is generated by a transistor having a threshold voltage close to or the same as a threshold voltage of a transistor used in the memory array and connected in the same manner. Thus each of the reference voltages will correspond very closely to one of the four possible voltages out of the memory cell. The required voltage levels are not generated until a row is selected. The reference voltage devices are arranged in columns which are in a layout similar to the memory columns. Consequently, any circuit parameter which can affect performance and which might vary in processing will vary the reference devices exactly the same as the memory devices. Therefore, the reference voltages will track the memory signals and the memory array will work over a wide range of processing parameters. The memory system has been illustrated as a read only memory and utilizes voltage sensing rather than current sensing. Thus, the only current needed is that required to charge the line capacitance. In addition, the memory devices can all be made minimum size, and hence the memory system can be made to draw very little power.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4094008 *Jun 18, 1976Jun 6, 1978Ncr CorporationAlterable capacitor memory array
US4202044 *Jun 13, 1978May 6, 1980International Business Machines CorporationQuaternary FET read only memory
US4342102 *Jun 18, 1980Jul 27, 1982Signetics CorporationSemiconductor memory array
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4636979 *Nov 2, 1984Jan 13, 1987Motorola, Inc.Orientation of reference cells in a memory
US4653023 *Sep 17, 1984Mar 24, 1987Fujitsu LimitedPlural-bit-per-cell read-only memory
US5163021 *Jul 22, 1991Nov 10, 1992Sundisk CorporationMulti-state EEprom read and write circuits and techniques
US5283761 *Jul 22, 1992Feb 1, 1994Mosaid Technologies IncorporatedMethod of multi-level storage in DRAM
US5440505 *Jan 21, 1994Aug 8, 1995Intel CorporationMethod and circuitry for storing discrete amounts of charge in a single memory element
US5450363 *Jun 2, 1994Sep 12, 1995Intel CorporationGray coding for a multilevel cell memory system
US5485422 *Jun 2, 1994Jan 16, 1996Intel CorporationMemory device
US5497354 *Jun 2, 1994Mar 5, 1996Intel CorporationBit map addressing schemes for flash memory
US5515317 *Jun 2, 1994May 7, 1996Intel CorporationAddressing modes for a dynamic single bit per cell to multiple bit per cell memory
US5539690 *Jun 2, 1994Jul 23, 1996Intel CorporationWrite verify schemes for flash memory with multilevel cells
US5566125 *Mar 31, 1995Oct 15, 1996Intel CorporationMethod and circuitry for storing discrete amounts of charge in a single memory element
US5574879 *Oct 10, 1995Nov 12, 1996Intel CorporationAddressing modes for a dynamic single bit per cell to multiple bit per cell memory
US5594691 *Feb 15, 1995Jan 14, 1997Intel CorporationAddress transition detection sensing interface for flash memory having multi-bit cells
US5612912 *Jan 11, 1996Mar 18, 1997Mosaid Technologies IncorporatedMethod of multilevel DRAM sense and restore
US5677869 *Dec 14, 1995Oct 14, 1997Intel CorporationProgramming flash memory using strict ordering of states
US5701266 *Dec 6, 1996Dec 23, 1997Intel CorporationProgramming flash memory using distributed learning methods
US5729489 *Dec 14, 1995Mar 17, 1998Intel CorporationProgramming flash memory using predictive learning methods
US5737265 *Dec 14, 1995Apr 7, 1998Intel CorporationProgramming flash memory using data stream analysis
US5742543 *Jun 13, 1997Apr 21, 1998Intel CorporationFlash memory device having a page mode of operation
US5748546 *Apr 10, 1997May 5, 1998Intel CorporationSensing scheme for flash memory with multilevel cells
US5764571 *Feb 27, 1995Jun 9, 1998Btg Usa Inc.Electrically alterable non-volatile memory with N-bits per cell
US5781472 *May 2, 1997Jul 14, 1998Intel CorporationWrite path circuit for writing data
US5796667 *Apr 19, 1996Aug 18, 1998Intel CorporationBit map addressing schemes for flash memory
US5815434 *Sep 29, 1995Sep 29, 1998Intel CorporationMultiple writes per a single erase for a nonvolatile memory
US5815443 *Apr 19, 1996Sep 29, 1998Intel CorporationMemory cell
US5828616 *Feb 19, 1997Oct 27, 1998Intel CorporationSensing scheme for flash memory with multilevel cells
US5892710 *Aug 13, 1997Apr 6, 1999Intel CorporationMethod and circuitry for storing discrete amounts of charge in a single memory element
US5905673 *Jun 2, 1997May 18, 1999Agate Semiconductor, Inc.Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
US5936884 *Jul 22, 1996Aug 10, 1999Intel CorporationMultiple writes per a single erase for a nonvolatile memory
US5991517 *Dec 20, 1996Nov 23, 1999Sandisk CorporationFlash EEprom system with cell by cell programming verification
US6002614 *Nov 21, 1997Dec 14, 1999Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US6052308 *Aug 3, 1999Apr 18, 2000Texas Instruments IncorporatedBalanced sensing arrangement for flash EEPROM
US6091618 *Aug 13, 1997Jul 18, 2000Intel CorporationMethod and circuitry for storing discrete amounts of charge in a single memory element
US6097637 *Sep 10, 1996Aug 1, 2000Intel CorporationDynamic single bit per cell to multiple bit per cell memory
US6104640 *Nov 18, 1998Aug 15, 2000Btg International Inc.Electrically alterable non-violatile memory with N-bits per cell
US6115285 *Feb 7, 1997Sep 5, 2000Siemens AktiengesellschaftDevice and method for multi-level charge/storage and reading out
US6243321Jan 28, 2000Jun 5, 2001Btg Int IncElectrically alterable non-volatile memory with n-bits per cell
US6246613Oct 4, 1999Jun 12, 2001Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US6282145Jan 14, 1999Aug 28, 2001Silicon Storage Technology, Inc.Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
US6285598Mar 13, 2000Sep 4, 2001Silicon Storage Technology, Inc.Precision programming of nonvolatile memory cells
US6304485Nov 9, 1998Oct 16, 2001San Disk CorporationFlash EEprom system
US6324121Feb 28, 2001Nov 27, 2001Btg International Inc.Electrically alterable non-volatile memory with n-bits per cell
US6327189Feb 28, 2001Dec 4, 2001Btg International Inc.Electrically alterable non-volatile memory with n-bits per cell
US6339545Feb 28, 2001Jan 15, 2002Btg International Inc.Electrically alterable non-volatile memory with n-bits per cell
US6343034Jan 28, 2000Jan 29, 2002Btg International Inc.Electrically alterable non-volatile memory with n-bits per cell
US6344998Feb 28, 2001Feb 5, 2002Btg International Inc.Electrically alterable non-volatile memory with N-Bits per cell
US6353554Dec 12, 2000Mar 5, 2002Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US6356486Jun 5, 2000Mar 12, 2002Btg International Inc.Electrically alterable non-volatile memory with n-bits per cell
US6396742Jul 28, 2000May 28, 2002Silicon Storage Technology, Inc.Testing of multilevel semiconductor memory
US6404675Feb 28, 2001Jun 11, 2002Btg International Inc.Electrically alterable non-volatile memory with n-bits per cell
US6414876Jul 12, 1999Jul 2, 2002Sandisk CorporationFlash EEprom system
US6434050Jun 29, 2001Aug 13, 2002Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US6462986Feb 24, 1999Oct 8, 2002Silicon Storage Technology, Inc.Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
US6462988May 17, 1999Oct 8, 2002Sandisk CorporationHighly compact EPROM and flash EEPROM devices
US6483742 *Apr 19, 1996Nov 19, 2002Intel CorporationBit map addressing schemes for flash memory
US6487116Jul 20, 2001Nov 26, 2002Silicon Storage Technology, Inc.Precision programming of nonvolatile memory cells
US6504762Mar 29, 1999Jan 7, 2003Sandisk CorporationHighly compact EPROM and flash EEPROM devices
US6584012Jun 4, 2002Jun 24, 2003Btg International Inc.Electrically alterable non-volatile memory with N-bits per cell
US6587372Jan 11, 2001Jul 1, 2003Micron Technology, Inc.Memory device with multi-level storage cells and apparatuses, systems and methods including same
US6654280Jan 28, 2003Nov 25, 2003Micron Technology, Inc.Memory device with multi-level storage cells
US6714455Jul 5, 2002Mar 30, 2004Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US6724656May 5, 2003Apr 20, 2004Btg International Inc.Electrically alterable non-volatile memory with n-bits per cell
US6816408 *Apr 15, 2003Nov 9, 2004Micron Technology, Inc.Memory device with multi-level storage cells
US6847550Oct 25, 2002Jan 25, 2005Nexflash Technologies, Inc.Nonvolatile semiconductor memory having three-level memory cells and program and read mapping circuits therefor
US6870763Mar 25, 2004Mar 22, 2005Btg International Inc.Electrically alterable non-volatile memory with n-bits per cell
US6901007Aug 7, 2002May 31, 2005Micron Technology, Inc.Memory device with multi-level storage cells and apparatuses, systems and methods including same
US7006384Dec 23, 2003Feb 28, 2006Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US7068542Sep 20, 2004Jun 27, 2006Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US7075825Mar 25, 2004Jul 11, 2006Btg International Inc.Electrically alterable non-volatile memory with n-bits per cell
US7266017May 30, 2001Sep 4, 2007Sandisk CorporationMethod for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system
US7283397Nov 7, 2002Oct 16, 2007Sandisk CorporationFlash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks
US7286414Apr 20, 2006Oct 23, 2007Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US7447069Apr 22, 1998Nov 4, 2008Sandisk CorporationFlash EEprom system
US7471581Mar 22, 2007Dec 30, 2008Silicon Storage Technology, Inc.Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory
US7848159Nov 20, 2008Dec 7, 2010Silicon Storage Technology, Inc.Non-volatile memory systems and methods including page read and/or configuration features
US7889545 *Aug 7, 2008Feb 15, 2011Samsung Electronics Co., Ltd.Apparatus and method of nonvolatile memory device having three-level nonvolatile memory cells
US7911851Oct 22, 2007Mar 22, 2011Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US8432750Dec 6, 2010Apr 30, 2013Silicon Storage Technology, Inc.Non-volatile memory systems and methods including page read and/or configuration features
US8570814Mar 4, 2011Oct 29, 2013Mlc Intellectual Property, LlcMemory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US8614924Apr 19, 2013Dec 24, 2013Silicon Storage Technology, Inc.Non-volatile memory systems and methods
US20140122967 *Oct 31, 2012May 1, 2014Infineon Technologies AgCircuitry and Method for Multi-Bit Correction
USRE37072Jan 31, 1996Feb 27, 2001Mosaid Technologies, Inc.Method of multi-level storage in DRAM and apparatus thereof
USRE40075Sep 1, 2000Feb 19, 2008Mosaid Technologies, IncorporatedMethod of multi-level storage in DRAM and apparatus thereof
USRE40567Feb 21, 2002Nov 11, 2008Intel CorporationFlash memory device of capable of sensing a threshold voltage of memory cells on a page mode of operation
WO1995034073A1 *May 17, 1995Dec 14, 1995Intel CorpBit map addressing schemes for flash memory
Classifications
U.S. Classification365/94, 365/210.1, 365/207, 365/210.12
International ClassificationG11C11/56, G11C17/00
Cooperative ClassificationG11C2211/5634, G11C11/56, G11C11/5692, G11C16/30
European ClassificationG11C11/56R, G11C11/56
Legal Events
DateCodeEventDescription
Jan 28, 1992FPExpired due to failure to pay maintenance fee
Effective date: 19911117
Nov 17, 1991LAPSLapse for failure to pay maintenance fees
Jun 18, 1991REMIMaintenance fee reminder mailed
Feb 25, 1987FPAYFee payment
Year of fee payment: 4
Feb 25, 1981ASAssignment
Owner name: MOTOROLA, INC., SCHAUMBURG, IL A CORP. OF DE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:ADLHOCH RICHARD H.;REEL/FRAME:003870/0968
Effective date: 19810220