|Publication number||US4430712 A|
|Application number||US 06/325,351|
|Publication date||Feb 7, 1984|
|Filing date||Nov 27, 1981|
|Priority date||Nov 27, 1981|
|Also published as||CA1198813A, CA1198813A1, EP0080877A2, EP0080877A3|
|Publication number||06325351, 325351, US 4430712 A, US 4430712A, US-A-4430712, US4430712 A, US4430712A|
|Inventors||Richard L. Coulson, Ronald L. Blickenstaff, P. David Dodd, Robert J. Moreno, Dean P. Kinard|
|Original Assignee||Storage Technology Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (68), Classifications (12), Legal Events (9)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to data storage management and control. More particularly, the invention relates to a memory system wherein a solid-state cache memory used in conjunction with long-term magnetic disk storage devices of varying types can be subdivided into blocks or "domains" of sizes chosen so as to insure efficient cache memory utilization despite varying demands placed on the system.
The present invention relates to a solid-state cache memory subsystem designed to be used primarily as an adjunct to long-term magnetic disk storage media. The cache memory is connected outboard of a conventional data transmission channel not specially designed for use with such a cache memory sub-system, such that the cache memory system is plug-compatible with and software transparent to a host computer. In particular, the invention is designed to operate in accordance with the cache memory subsystem which is the subject matter of copending patent application Ser. No. 325,346 filed Nov. 27, 1981 incorporated herein by reference. That application describes a cache memory subsystem which is operatively connected to storage director(s) which in turn are connected between a host computer at one point and the control modules at another. In turn the control modules connect to the actual disk drive. As is known in the art, the directors serve to interface the host with the control modules which in turn interface the directors to the disk drives. The control modules are selected in accordance with the particular type of disk drive used while the directors may be used with various types of control modules and hence with various types of disk drives. According to the invention of that application, the cache is adapted to be used with varying sorts of disk drives by connection to the director(s).
The function of the solid-state cache memory subsystem in the invention of the copending application referred to above is to store certain data which has been determined to be likely to be called for by the host in advance of an actual host request for that certain data. This determination is done in accordance with the invention disclosed in another copending application, Ser. No. 325,350 filed Nov. 27, 1981, also incorporated herein by reference. In a preferred embodiment of that invention, once it has been determined that a particular block of data is likely to be called for by the host, the entire disk track containing that block of data is brought into the cache memory for temporary storage in anticipation of its being called for by the host computer. Inasmuch as the cache memory subsystem must be adapted to cooperate with varying types of disk drives which in turn have varying amounts of data stored on a given track, means must be provided whereby the cache memory is as useful as is possible despite the fact that disk tracks of varying sizes will be stored therein track by track. For example, if it were assumed that the total cache memory was to contain 200 kilobytes (hereinafter 200 kb) of data, and the track length of a particular disk drive was 20 kb, 10 such tracks would fit into the cache. Stated slightly differently, the cache could be divided into ten 20-kb "frames". When, for example, all ten frames were full and it was desired to cache another track, a cache manager could then simply deallocate a frame, for example a frame containing the data which had been least recently used and then allocate that frame to the new track. However, if data stored on another type of disk drive having a track size of, say, 25 kb, were desired to be staged, it would be necessary to deallocate two adjacent 20 kb frames in order to accommodate a 25 kb track thus wasting 15 kb of space. Even assuming two adjacent frames could be deallocated without loss of useful data, the waste of space alone would clearly be undesirable. If on the other hand the entire solid-state memory were divided into one subportion or "domain" adapted to store only tracks of one size, and another subportion proportioned to storage of tracks of another size, the individual domains of the memory might be efficiently allocated. However, utility of this solution presupposes that the relative activity of the two sizes of tracks is constant over time, which cannot be expected to be the case. Thus, it is desirable that all area of the solid state memory be accessible to any track size supported by the cache in order that it can be most efficiently used. Finally, one could divide all track sizes into much smaller uniformly-sized "pages", e.g., 2 kb, which would fit fairly uniformly within the frames. However, this would require complex hardware to implement and would additionally reduce the efficiency of the cache as necessarily an individual disk track would tend to be stored on varying portions of the cache, which would entail substantial additional support, e.g. recall of the numerous storage locations of the portions of a given track.
It is accordingly an object of the present invention to provide a means whereby the storage area available in a solid-state cache memory can be most efficiently used.
It is a further object of the invention to provide a method whereby a solid-state cache memory subsystem can be operated efficiently to store data records of varying sizes.
It is a further object of the invention to provide a means for "adaptively" or "dynamically" reconfiguring a cache memory previously divided into domains of plural classes in accordance with actual use, so as to fully utilize the memory space available.
The above needs of the art and objects of the invention are satisfied by the present invention according to which a solid-state memory is subdivided into domains. The size of the domains is chosen to be a substantially integral multiple of each of the track sizes desired to be stored therein, such that, for example, three 50-kb tracks from one class of device will fit within the same 150-kb domain as two 75-kb tracks from another class. Each individual domain is thereafter assigned to storage of tracks from a given type of device, and then divided into track-sized frames, to which individual tracks are written. Statistics are maintained on domain usage. If the indications are that the data staged from a particular device type predominates over another, a given domain is reallocated from the second device type to the first device type so as to insure efficient usage of the total memory space available. In this way, fragmentation due to intermingling of varying track sizes in the same area of memory is avoided.
The invention will be better understood if reference is made to the accompanying drawings, in which:
FIG. 1 represents a schematic block diagram view of the system of the invention;
FIG. 2 shows how individual domains can be subdivided according to the track sizes desired to be stored therein;
FIG. 3 shows a domain switching decision table used in determining which domains to switch at a particular time; and
FIG. 4 shows a diagram indicating how the domain switching determination decision is utilized in actually performing the switching operation and how the control tables are updated as the scheme proceeds.
As discussed above, the adaptive domain partitioning methods of the invention are designed to be used in a solid-state cache memory subsystem operated to contain data being stored on disk memory in anticipation of its being called for by a host computer.
FIG. 1 shows a schematic diagram of such a system. The host computer 10 is connected by means of a conventional channel interface 12 to a storage director 16. The storage director in turn interfaces to plural control modules 18 which themselves control disk drives 14 which as shown may be of differing types. In particular, the amount of data stored on a given track of one of the disks 14 can vary. When a decision is made by a cache manager 24, e.g. in accordance with copending application Ser. No. 325,350 filed Nov. 27, 1981, that it would be desirable to store the entire contents of a track in a solid-state cache memory array 22, a number of locations in the cache corresponding in size to the length of the track on the disk 14--i.e., a "frame" of locations in the cache--must be assigned to the data. When it is desired by the cache manager that a particular track be staged into a frame in the cache array 22, a frame is assigned to that track and the operation proceeds. The present invention is concerned with efficient division of the cache array into subportions or "domains". The size of the domains is chosen so that approximately integral numbers of disk tracks of varying lengths fit into "frames" in each domain. Thus, after allocation of the domain to a particular track length, it is divided into "frames" of sizes corresponding to the track lengths.
It can be expected that at some point all the domains allocated to tracks of a particular length would be heavily in use, while those allocated to disk tracks of other type(s) were not. According to an important aspect of the present invention, the domains are chosen to all be of the same size so that they can be efficiently reallocated to contain data stored on a different type of disk memory device. The domains are "dynamically" repartitioned into frames of a different size according to usage. For this reason, the domain size is chosen such that the domains contain integral numbers of frames of various sizes. FIG. 2 shows an example of how this can be done. There the domain size is approximately 256 kilobytes (kb). In a preferred embodiment, the cache contains some 12 of such domains for a total capacity of approximately three megabytes. Three possible domain subdivision schemes are shown in FIG. 2.
FIG. 2A shows a scheme which might be adopted for a domain to be used with the Model 8650 disk drive sold by Storage Technology Corporation, the assignee of the present invention, in which each track contains some 19,069 bytes plus some indentifying "header" information. Thirteen such tracks with their headers will fit within the 256 kb domain. Storage Technology Corporation's Model 8375 disk drive has a track size of approximately 37,000 bytes. As shown in FIG. 2b, six such 37,000 kb tracks with headers will fit within the 256 kb domain. Finally, Storage Technology Corporation's Model 8380 disk drive has a 47,476 byte track size. FIG. 2c shows that five such frames together with headers fit well into the 256 kb domain size.
According to the present invention, dynamic repartitioning of cache space allocation is provided in accordance with usage. This allows high storage efficiency without severe fragmentation. Fragmentation is wastage of space due to lack of correspondence between the size of available frames and the sizes of the tracks that are to be stored in the available frames. Severe fragmentation is avoided because a domain may be reallocated from one device type to another by reframing whenever desirable. Reallocation occurs in only one domain at a time, thus providing stability and simplicity by eliminating the need to invalidate the entire cache design. A "domain use count" is kept to keep track of which class of domains is experiencing heavy usage. This makes it possible to determine whether the current allocation of the domains is the most efficient with respect to usage of the system at any particular time. This is discussed below in connection with FIGS. 3 and 4.
A preliminary problem which must be addressed is frame assignment, that is, picking the best frame to assign to a given track to be staged to the cache array. The "best frame" is one which is not currently assigned to any track. However, if no frames are free then a frame must be "detached" from the track to which it is currently assigned and reassigned to the new track which is to be staged. The best frame to detach is one which is no longer being read by the host. Frames which are still being read by the host should not be detached because overhead spent in staging the track would not be recovered if it is detached before the data is read. In a presently preferred embodiment of the invention, frame assignment is performed using a "least recently used" (LRU) scheme. The LRU scheme is implemented by means of a list of frames. The list has a top, at which is located the frames which have been most recently used, and a bottom, which corresponds to the frames which have not been used recently and those which are free. Thus when a frame is used, that is, is staged to or read from, its name is placed atop the list. When a frame is detached it is moved to the bottom of the list. This occurs when the host directs a write operation to the area on disk from which the contents of that frame were staged, thus rendering the data in that frame invalid, or when all records have been read from that track. Thus, the bottom of the list contains a free frame or the least recently used frame, and the frame on the bottom of the list will typically be the best to assign to a track to be staged. Of course, when the frame is assigned, it is moved to the top of the list, indicating that it is the most recently used.
Even given the LRU scheme, however, it may well be that if two or more classes of domains of different sizes are present in the cache memory, a first type will be much more heavily used than a second type so that the LRU list for the first domain type will have, for example, fewer free frames on it than the list of the second domain type. System performance, in general, can be improved by reallocating domains from the second type of storage to the first. This domain reallocation method allows for efficient use of cache space. Since the need for frames suited to a particular device will vary with time, it is particularly desirable to dynamically allocate and deallocate domains to device type based on demand. An important aspect of the present invention relates to an adaptive or dynamic domain allocation scheme; in a preferred embodiment, the invention supports two types of disk storage devices having differing track storage capacities and can reallocate domains from, e.g. device type A to device type B, although it would be possible to provide three or more class of domains in a given cache. In this way the cache space is allocated in proportion to the input/output activity.
According to the presently preferred embodiment of the invention, three questions are considered by the domain allocation decision-making process:
How often to switch domains?
When to switch a domain?
Which domain to switch?
With respect to the first question, domain switching is considered in the presently preferred embodiment on the order of once every 1000 stage operations, i.e., every 1000 times a data track is read into the cache memory. In a relatively large embodiment of the invention this is expected to occur approximately every 30 to 60 seconds.
The second problem is determining when to switch a domain. This decision should be based on an imbalance between the cache input/output activity ratios for device type A with respect to device type B. A suitable method of measuring activity is to count the stages to domains assigned to each device type. This stage count ratio should be equal to the ideal "frames available" ratio. In turn, the frames available ratio can be used to compute an ideal "domains allocated" ratio since the number of frames per domain is known. If the actual domains allocated ratio is different from the ideal domains allocated ratio it is time to switch domains. In this way the relative size of the various frames is removed from the consideration, as opposed to merely measuring domain type activity.
The third and most difficult problem is to determine which domain to switch. Domains with many recently used frames are clearly not good candidates for switching. The best domains to switch are instead those that have many old and free frames. Two alternatives may be considered. First, since the LRU list described above shows the relative age of the frames of each domain, the list can be used to determine which domain to switch. A scan of a predetermined number of frames on the list described above can be made, incrementing a counter for each domain when a frame belonging to that domain is found on the list. Accordingly, the domain having the lowest count at the end of the scan is that which is currently undergoing the least activity. The scan should be limited to the top portion of the list, because this is where activity occurs. It might seem that the lower end of the list could be most profitably looked at because this is where the old and invalid frames will congregate. However, if but a single active frame is in the same domain with a large number of old frames it would invalidated as well by the domain reallocation operation which would be undesirable. The second alternative is to count the stages to each domain rather than examine the least recently used frame list. This would again provide an indication of relative activity.
Thus, it will be clear that the domain switching scheme according to the invention has two portions: the decision making portion, which decides whether or not it is desirable to switch domains from one class to another, and the actual switching process, in which it is determined which domain is to be switched. In a particularly preferred embodiment, the decision making process is table driven in order to save execution time; that is to say, when the device is turned on, a look-up table indicating the ideal allocations of the domains for varying relative activity levels is generated and stored so that subsequent reallocation decisions can then simply be look-up processes not requiring an elaborate computation. Such a domain switch decision table usable in a preferred embodiment of the invention where the domain switching occurs between two device types is shown in FIG. 3.
The table is built by making all the possible domain switching decisions at post-IMPL time (that is, upon initial loading of the device) thus saving computation time when the decision is actually made. The decision thus becomes a simple table look up based on, e.g. the number of domains allocated to device type A and "A domain use"--a number representing actual staging operations from devices of the type A--at a particular time. In the embodiment of FIG. 3, the table shows numbers between zero and 15 (i.e., F, in hexadecimal) along the horizontal axis indicative of the relative number of stages to A device type domains. Each column thus represents the A-use figure. The table is built one horizontal "row" at a time with each row representing the number of domains allocated to device A at a given time. For each row, that is, for each number of domains allocated to A-type devices, there is thus an ideal target A-use. The table thus provides a correlation between the number of domains assigned to device A and the relative number of A stages in a given time. If the correspondence is not found then it is evident that domain switching should be performed. Target A use is calculated based on the assumption that the ideal cache partitioning is achieved when ##EQU1## One can usefully define a term called "Target A Stages", this being the number of stages which would occur to domains assigned to device type A if the staging activity was in balance with cache allocation. This will lead to a target A frame use which can be compared with the actual A frame use to determine how close the actual stage activity compares with what would be ideal. Thus, in the table of FIG. 3 each of the horizontal rows represents a given number of domains allocated to a device. The target A use is then identical for that row. One of three indications is then filled in for each position of that row according to the actual use. A small a, indicating that a B to A domain reallocation is pending, i.e. desirable, is filled in if actual A use is greater than target A use, thus indicating that switching of a frame from B to A is an acceptable action if a request for an A frame assignment cannot be satisfied based on current allocation. Similarly, a small b indicating a pending switch from A to B is filled in if A use is less than target A use. Otherwise an n, indicating a "no switching required" condition is filled in.
As will be observed from Table III, several, typically 3, of the columns for each row have n's which indicate that no switch is pending. This is desirable in order to prevent unnecessary domain switching due to statistical variation in the number of stages per domain type over a short period of time which can be expected to occur, while not indicating that domain reallocation is called for. The plurality of n's in the columns thus provide a quasi-damping effect on the domain switching according to the invention.
As noted above, domain switching is initiated based on demand for a frame and on the value of a "domain switch pending" flag generated in the statistics keeping process. Thereafter, if data is to be cached and no frame for the proper device type is free, and a domain switch operation is pending which would provide a frame of the proper device type, the domain switching operation is initiated.
The first task performed in the domain switching operation is to decide which domain would be the best to switch. The least recently used list of the "from" device type is scanned to determine which domain has the fewest frames on the top half of the least recently used list. If this domain in turn has no frames marked "In use" or "Stage in Progress", it is presumed to be the best one to switch. Otherwise, the domain with the next fewest frames in the top of the least recently used list is chosen. Once a domain is chosen for switching, the domain is converted to the new device type. All valid frames belonging to the domain are deallocated. All frames in the domain are removed from the "from" device type least recently used list. The number of new frames that will fit into the new domain are linked onto the bottom of the new device type least recently used list. Finally, new pointers to the cache array are assigned for each frame according to the frame size of the new device type. Thus, when the domain conversion routine is finished, the new frames are at the bottom of the new device type least recently used frame list, and are marked free.
FIG. 4 shows a schematic view of the decision-making process according to the invention. As discussed above, at initial program load, "IMPL time", the table is written with all the possible decisions as at 32, the table then appearing as in FIG. 3. This information is then available to domain switch determination module 34. This decision making process is also supplied with domain switch statistics as at 36 which indicate whether domain usage is presently corresponding to domain allocation. Therefore, upon a stage request being validated as at 38 by the cache manager 24, (FIG. 1) as discussed in copending application Ser. No. 325,350 filed Nov. 27, 1981, the domain switch statistics may be examined to determine which, domain if any, should be switched. Typically, the operation is performed every, e.g., 1000 stages. If an imbalance is detected by accessing the table of FIG. 3 as at 32, a flag is set indicating that a switch is pending as at 40. Thereafter, upon a request that a frame be allocated to a data record at 42, if no free frame is available, and if an appropriate switch is pending, the least recently used domain is switched as described above as indicated at 44. The domain thus converted at 46 has now been allocated to the new device type, e.g. type A, and the table is updated to reflect this fact at 48, while the directory of frames available is likewise updated as at 50.
Attached hereto as Appendix A and incorporated herein by reference is a document entitled "Module: Domain Switching" which is a detailed description of methods used to perform the apparatus of the invention. This document is largely written in a form of convenient shorthand language referred to as pseudocode, the grammar of which is explained in a document also attached hereto and incorporated by reference, marked Appendix A-1, entitled "Chinook Pseudo Code Conventions". Those skilled in the art supplied with the domain switching document of Exhibit A together with the interpretative pseudocode convention document would have no difficulty implementing the methods of the invention.
Those skilled in the art will recognize that there has been described a domain partitioning system for dividing up a solid-state memory which fulfills the needs of the art and objects of the invention mentioned above. Specifically, use of domains having a size into which commonly accessed quantities of data, e.g., tracks, fit conveniently provides efficient storage of data without fragmentation as old records are overwritten by new data. More particularly, the provision of an adaptive domain switching scheme allows efficient utilization of memory to be achieved even when relative domain utilization changes from time to time. Furthermore, it will be appreciated that the method of the invention has applicability beyond the two device embodiment specifically described, and that therefore the description of the invention given above should not be considered as a limitation on its scope but only as exemplary thereof; the scope of the invention is more properly limited by the following claims. ##SPC1## ##SPC2##
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4499539 *||Dec 20, 1982||Feb 12, 1985||International Business Machines Corporation||Method and apparatus for limiting allocated data-storage space in a data-storage unit|
|US4724518 *||Jun 16, 1987||Feb 9, 1988||Hewlett-Packard Company||Odd/even storage in cache memory|
|US4800483 *||May 28, 1987||Jan 24, 1989||Hitachi, Ltd.||Method and system for concurrent data transfer disk cache system|
|US4870565 *||Mar 13, 1989||Sep 26, 1989||Hitachi, Ltd.||Parallel transfer type director means|
|US4875155 *||Jun 28, 1985||Oct 17, 1989||International Business Machines Corporation||Peripheral subsystem having read/write cache with record access|
|US4905141 *||Oct 25, 1988||Feb 27, 1990||International Business Machines Corporation||Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification|
|US4947319 *||Sep 15, 1988||Aug 7, 1990||International Business Machines Corporation||Arbitral dynamic cache using processor storage|
|US5218689 *||Jun 10, 1992||Jun 8, 1993||Cray Research, Inc.||Single disk emulation interface for an array of asynchronously operating disk drives|
|US5276832 *||Jun 19, 1990||Jan 4, 1994||Dell U.S.A., L.P.||Computer system having a selectable cache subsystem|
|US5283791 *||Mar 18, 1993||Feb 1, 1994||Cray Research Systems, Inc.||Error recovery method and apparatus for high performance disk drives|
|US5367653 *||Dec 26, 1991||Nov 22, 1994||International Business Machines Corporation||Reconfigurable multi-way associative cache memory|
|US5394531 *||Nov 18, 1991||Feb 28, 1995||International Business Machines Corporation||Dynamic storage allocation system for a prioritized cache|
|US5473764 *||Apr 8, 1994||Dec 5, 1995||North American Philips Corporation||Multilevel instruction cache|
|US5572699 *||Mar 15, 1993||Nov 5, 1996||Hitachi, Ltd.||Variable length data in a parallel disk array|
|US5678022 *||Sep 21, 1993||Oct 14, 1997||Nec Corporation||Storage control system with auxiliary storage and optimized process data length and gap to reduce track and cylinder switching|
|US5689514 *||Sep 30, 1996||Nov 18, 1997||International Business Machines Corporation||Method and apparatus for testing the address system of a memory system|
|US5717893 *||May 20, 1991||Feb 10, 1998||International Business Machines Corporation||Method for managing a cache hierarchy having a least recently used (LRU) global cache and a plurality of LRU destaging local caches containing counterpart datatype partitions|
|US5802003 *||Dec 20, 1995||Sep 1, 1998||International Business Machines Corporation||System for implementing write, initialization, and reset in a memory array using a single cell write port|
|US5826006 *||Sep 30, 1996||Oct 20, 1998||International Business Machines Corporation||Method and apparatus for testing the data output system of a memory system|
|US5875464 *||Mar 18, 1996||Feb 23, 1999||International Business Machines Corporation||Computer system with private and shared partitions in cache|
|US5914906 *||Dec 20, 1995||Jun 22, 1999||International Business Machines Corporation||Field programmable memory array|
|US5949719 *||Nov 12, 1998||Sep 7, 1999||International Business Machines Corporation||Field programmable memory array|
|US6016535 *||Oct 11, 1995||Jan 18, 2000||Citrix Systems, Inc.||Method for dynamically and efficiently caching objects by subdividing cache memory blocks into equally-sized sub-blocks|
|US6023421 *||Nov 12, 1998||Feb 8, 2000||International Business Machines Corporation||Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array|
|US6034945 *||May 15, 1996||Mar 7, 2000||Cisco Technology, Inc.||Method and apparatus for per traffic flow buffer management|
|US6038192 *||Nov 10, 1998||Mar 14, 2000||International Business Machines Corporation||Memory cells for field programmable memory array|
|US6044031 *||Nov 12, 1998||Mar 28, 2000||International Business Machines Corporation||Programmable bit line drive modes for memory arrays|
|US6075745 *||Nov 12, 1998||Jun 13, 2000||International Business Machines Corporation||Field programmable memory array|
|US6091645 *||Nov 12, 1998||Jul 18, 2000||International Business Machines Corporation||Programmable read ports and write ports for I/O buses in a field programmable memory array|
|US6118707 *||Nov 10, 1998||Sep 12, 2000||International Business Machines Corporation||Method of operating a field programmable memory array with a field programmable gate array|
|US6118899 *||Oct 12, 1999||Sep 12, 2000||Citrix Systems, Inc.||Method for lossless bandwidth compression of a series of glyphs|
|US6130854 *||Nov 12, 1998||Oct 10, 2000||International Business Machines Corporation||Programmable address decoder for field programmable memory array|
|US6141737 *||Nov 4, 1999||Oct 31, 2000||Citrix Systems, Inc.||Method for dynamically and efficiently caching objects received from an application server by a client computer by subdividing cache memory blocks into equally-sized sub-blocks|
|US6172683||Oct 29, 1999||Jan 9, 2001||Citrix Systems, Inc.||Method for the lossless compression of lines in a distributed computer system|
|US6233191||Feb 22, 2000||May 15, 2001||International Business Machines Corporation||Field programmable memory array|
|US6272592 *||Mar 2, 1993||Aug 7, 2001||Inria Institut National De Recherche En Informatique Et En Automatique||Cache memory device|
|US6370622||Nov 19, 1999||Apr 9, 2002||Massachusetts Institute Of Technology||Method and apparatus for curious and column caching|
|US6430191||Jun 30, 1997||Aug 6, 2002||Cisco Technology, Inc.||Multi-stage queuing discipline|
|US6487202||Jun 30, 1997||Nov 26, 2002||Cisco Technology, Inc.||Method and apparatus for maximizing memory throughput|
|US6526060||Dec 5, 1997||Feb 25, 2003||Cisco Technology, Inc.||Dynamic rate-based, weighted fair scheduler with explicit rate feedback option|
|US6535484||Jan 24, 2000||Mar 18, 2003||Cisco Technology, Inc.||Method and apparatus for per traffic flow buffer management|
|US6775292||Jan 24, 2000||Aug 10, 2004||Cisco Technology, Inc.||Method for servicing of multiple queues carrying voice over virtual circuits based on history|
|US7028025||May 25, 2001||Apr 11, 2006||Citrix Sytems, Inc.||Method and system for efficiently reducing graphical display data for transmission over a low bandwidth transport protocol mechanism|
|US7127525||May 25, 2001||Oct 24, 2006||Citrix Systems, Inc.||Reducing the amount of graphical line data transmitted via a low bandwidth transport protocol mechanism|
|US7142558||Apr 17, 2000||Nov 28, 2006||Cisco Technology, Inc.||Dynamic queuing control for variable throughput communication channels|
|US7275135||Aug 31, 2001||Sep 25, 2007||Intel Corporation||Hardware updated metadata for non-volatile mass storage cache|
|US7490166||May 25, 2001||Feb 10, 2009||Citrix Systems, Inc.||Remote control of a client's off-screen surface|
|US7502784||Mar 3, 2006||Mar 10, 2009||Citrix Systems, Inc.||Method and system for efficiently reducing graphical display data for transmission over a low bandwidth transport protocol mechanism|
|US7877547 *||May 6, 2005||Jan 25, 2011||International Business Machines Corporation||Method, system and circuit for efficiently managing a cache storage device|
|US8099389||Feb 6, 2009||Jan 17, 2012||Citrix Systems, Inc.||Method and system for efficiently reducing graphical display data for transmission over a low bandwidth transport protocol mechanism|
|US8171169||May 1, 2012||Citrix Systems, Inc.||Method and apparatus for updating a graphical display in a distributed processing environment|
|US8290907||Oct 16, 2012||Citrix Systems, Inc.|
|US8423673||Mar 14, 2005||Apr 16, 2013||Citrix Systems, Inc.||Method and apparatus for updating a graphical display in a distributed processing environment using compression|
|US8677022||Mar 18, 2013||Mar 18, 2014||Citrix Systems, Inc.||Method and apparatus for updating a graphical display in a distributed processing environment using compression|
|US9223710||Mar 16, 2013||Dec 29, 2015||Intel Corporation||Read-write partitioning of cache memory|
|US20020029285 *||May 25, 2001||Mar 7, 2002||Henry Collins||Adapting graphical data, processing activity to changing network conditions|
|US20020035596 *||May 25, 2001||Mar 21, 2002||Ruiguo Yang||Remote control of a client's off-screen surface|
|US20030046432 *||May 25, 2001||Mar 6, 2003||Paul Coleman||Reducing the amount of graphical line data transmitted via a low bandwidth transport protocol mechanism|
|US20030046493 *||Aug 31, 2001||Mar 6, 2003||Coulson Richard L.||Hardware updated metadata for non-volatile mass storage cache|
|US20030074524 *||Oct 16, 2001||Apr 17, 2003||Intel Corporation||Mass storage caching processes for power reduction|
|US20050138296 *||Dec 18, 2003||Jun 23, 2005||Coulson Richard L.||Method and system to alter a cache policy|
|US20060143383 *||May 6, 2005||Jun 29, 2006||Xiv Ltd.||Method, system and circuit for efficiently managing a cache storage device|
|US20060203007 *||Mar 14, 2005||Sep 14, 2006||Citrix Systems, Inc.||A method and apparatus for updating a graphical display in a distributed processing environment using compression|
|US20060206820 *||Mar 14, 2005||Sep 14, 2006||Citrix Systems, Inc.||A method and apparatus for updating a graphical display in a distributed processing environment|
|US20090144292 *||Feb 6, 2009||Jun 4, 2009||Henry Collins|
|US20100205246 *||Aug 12, 2010||Henry Collins|
|US20110161557 *||Jun 30, 2011||Seagate Technology Llc||Distributed media cache for data storage systems|
|WO2003034230A1||Oct 4, 2002||Apr 24, 2003||Intel Corporation||Mass storage caching processes for power reduction|
|U.S. Classification||1/1, 711/171, 711/173, 711/E12.019, 707/999.205|
|International Classification||G06F3/06, G06F12/08|
|Cooperative Classification||Y10S707/99956, G06F2212/312, G06F12/0866, G06F2212/601|
|Nov 8, 1982||AS||Assignment|
Owner name: STORAGE TECHNOLOGY CORPORATION, P.O. BOX 98, LOUIS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:COULSON, RICHARD L.;BLICKENSTAFF, RONALD L.;DODD, P. DAVID;AND OTHERS;REEL/FRAME:004061/0452
Effective date: 19811124
|Sep 13, 1987||REMI||Maintenance fee reminder mailed|
|Feb 7, 1988||REIN||Reinstatement after maintenance fee payment confirmed|
|Mar 24, 1988||SULP||Surcharge for late payment|
|Mar 24, 1988||FPAY||Fee payment|
Year of fee payment: 4
|Apr 26, 1988||FP||Expired due to failure to pay maintenance fee|
Effective date: 19880207
|Jun 14, 1988||DP||Notification of acceptance of delayed payment of maintenance fee|
|Jul 31, 1991||FPAY||Fee payment|
Year of fee payment: 8
|Jul 24, 1995||FPAY||Fee payment|
Year of fee payment: 12