|Publication number||US4456488 A|
|Application number||US 06/364,157|
|Publication date||Jun 26, 1984|
|Filing date||Mar 31, 1982|
|Priority date||Apr 14, 1981|
|Also published as||DE3165937D1, EP0062725A1, EP0062725B1|
|Publication number||06364157, 364157, US 4456488 A, US 4456488A, US-A-4456488, US4456488 A, US4456488A|
|Original Assignee||Itt Industries, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Non-Patent Citations (2), Referenced by (8), Classifications (13), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention deals with the fabrication of integrated planar transistors of very small size as are used in bipolar integrated circuits of high packing density. It starts from the triple-diffusion process (3D technology) disclosed in DE-OS No. 30 09 434 and in the journal "Electronics" of Aug. 7, 1975, pages 101 to 106. In that method, the impurities of the collector region, the base region, and the emitter region are deposited by ion implantation and diffused in three sequential steps, so that three diffusion processes succeed one another.
In addition to permitting the manufacture of bipolar integrated circuits of high packing density, this method, henceforth called "3D process", has the advantage of eliminating the need for the high-temperature processes for depositing an epitaxial layer on a substrate, which may be provided with doped regions for forming buried layers if necessary, and the diffusion of isolation regions. In the 3D process, these high-temperature processes, which are generally necessary to electrically isolate the individual transistors from each other, are replaced by one high-temperature process, namely the collector-diffusion process. Planar transistors are formed whose regions are diffused into one another.
The object of the invention is to fabricate planar transistors whose three regions are formed in only two high-temperature processes, so that very small diffusion depths are possible.
In the method according to the invention, which can thus be referred to as "2D process", besides the collector-diffusion high-temperature process, only one high-temperature process is necessary which takes place after the impurities of both the base region and the emitter region have been introduced into the semiconductor surface.
Preferably, use in made exclusively of photoresist masks to shield selected portions of the semiconductor surface during ion implantation because the production of such masks requires no high temperatures as would be necessary to produce oxide masks for the same purpose.
In a preferred embodiment of the method according to the invention, the dopant of the base region and that of the emitter region are implanted through the same oxide layer, which is produced in controlled fashion during the diffusion of the collector region. This has the advantage of compensating for the effects of variations in the thickness of the oxide layer formed during the collector diffusion on the variations in the thickness of the base region under the emitter region, because these oxide-thickness variations affect the implantation processes for introducing the dopants of both the emitter region and the base region in the same way.
If a protective oxide (SiO2) is used, the high-temperature process for activating the dopants of the base region and the emitter region below the protective-oxide layer has the advantage that the SiO2, which is solidified by this process, becomes etchable. This solidification goes to the point that, even if a wet-etching process is used to form contact windows, practically the same time as that required with a passivating layer thermally produced from the semiconductor material is needed for the etching process.
An embodiment of the method according to the invention will now be described with reference to the accompanying drawing, in which
FIGS. 1 to 4 show part of a monolithic integrated circuit in the cross-sectional views approximately perpendicular to a semiconductor wafer, and which serves to explain the sequential steps of the method according to the invention.
The semiconductor wafer 2 commonly contains a plurality of integrated circuits with a plurality of integrated planar transistors. After processing, the wafer is separated into individual integrated-circuit chips.
The method according to the invention starts from an arrangement as shown in the sectional view of FIG. 1. FIG. 1 shows a p-type semiconductor wafer 2 into which the n-type collector region 4 was diffused in an oxidizing atmosphere using an oxide mask layer 14, with the oxide layer 13 being formed at the surface. The conventional planar diffusion process can be used for this purpose. Since, however, the necessary small amounts of impurities are virtually only controllable by ion implantation, it is preferred to implant the dopant into the semiconductor surface using the oxide mask layer 14 or a photoresist mask, and to activate the dopant in an oxidizing atmosphere during a subsequent diffusion process. The dopant for the collector region 4 may be phosphorous.
It is very advantageous to produce within the openings 15 in the oxide mask layer 14 an oxide layer 13 of such a thickness that the dopant of the base region 3 can be implanted through the same oxide layer 13 as the emitter region 1. This has the advantage of reducing the effects of the variations in the thickness of the oxide layer 13 on the variations in the thickness of the base region 3 below the emitter region 1. If the thickness of the oxide layer 13 ranges between 30 and 60 nm, both boron as the dopant of the base region 3 and arsenic as the dopant of the emitter region 1 can be implanted through the same oxide layer 13.
After the collector region 4 and the oxide layer 13 have been produced, a frame-shaped opening 18 surrounding the collector region 4 can be formed in the oxide mask layer 14. Through this opening 18, the dopants of a guard-ring region 19 (see FIG. 4) are implanted during the implantation of the dopants of the base region 3.
Following the deposition of the mask layer 16, preferably a photoresist layer, with the frame-shaped implantation opening 17 and the base-implantation opening 20, boron ions are implanted (FIG. 2). Then, the mask layer 16 is removed.
Next, the implantation mask 9 is deposited. It has a frame-shaped opening 11, which surrounds the emitter-region-implantation opening 10 and allows the implantation of the dopant of a frame-shaped collector contact region 12 (see FIG. 4). This deposition is followed by the implantation of arsenic ions.
At a thickness of the oxide layer 13 in the above-mentioned range between 30 and 60 nm, accelerating voltages of about 200 KV are necessary for the arsenic atoms. If phosphorous ions are implanted instead of arsenic ions, an accelerating voltage of 100 KV is sufficient, because the phosphorous ion is smaller than the arsenic ion. However, the preferred dopant for the emitter region is arsenic, because it is better accommodated in the Si lattice, so that better electrical properties of the components are obtained.
After careful removal of the implantation mask 9, the surface of the semiconductor wafer 2 is covered with a protective insulating layer 5, preferably of SiO2, and the implanted ions are then activated in a tempering process, during which the base region 3, the emitter region 4, the collector contact region 12, and the guard-ring region 19 are formed; in addition, the protective insulating layer 5 is densified.
As can be seen in FIG. 4, contact windows are now formed in the protective insulating layer 5, and the contacts 6, 7, and 8 are deposited. An advantage lies in the fact that the edges of the emitter pn junction 21 are protected during the whole high-temperature process and remain protected thereafter, so that emitters for reproducible high emitter efficiencies at comparatively low current densities are obtained.
The cutoff frequency (fD) of an integrated planar transistor fabricated by the method according to the invention and occupying an area of 36 μm2 is about 2 GHz, i.e., considerably higher than that of transistors fabricated by the method disclosed in DE-OS No. 30 09 434.
In the process described, only photoresist masks were used to provide a masked area during ion implantation into the base region 3 and the emitter region 1.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3756861 *||Mar 13, 1972||Sep 4, 1973||Bell Telephone Labor Inc||Bipolar transistors and method of manufacture|
|US3928081 *||Oct 26, 1973||Dec 23, 1975||Signetics Corp||Method for fabricating semiconductor devices using composite mask and ion implantation|
|US4018627 *||Sep 22, 1975||Apr 19, 1977||Signetics Corporation||Method for fabricating semiconductor devices utilizing oxide protective layer|
|US4106954 *||Feb 10, 1977||Aug 15, 1978||U.S. Philips Corporation||Method of manufacturing transistors by means of ion implantation|
|US4133704 *||Jan 17, 1977||Jan 9, 1979||General Motors Corporation||Method of forming diodes by amorphous implantations and concurrent annealing, monocrystalline reconversion and oxide passivation in <100> N-type silicon|
|1||*||Briska et al., IBM TDB, 23 (1980), 644.|
|2||Briska et al., IBM-TDB, 23 (1980), 644.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4566176 *||May 23, 1984||Jan 28, 1986||U.S. Philips Corporation||Method of manufacturing transistors|
|US4567644 *||Nov 21, 1984||Feb 4, 1986||Signetics Corporation||Method of making triple diffused ISL structure|
|US4648909 *||Nov 28, 1984||Mar 10, 1987||Fairchild Semiconductor Corporation||Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits|
|US4739389 *||Sep 26, 1986||Apr 19, 1988||U.S. Philips Corporation||High-frequency circuit arrangement and semiconductor device for use in such an arrangement|
|US4762804 *||Jan 23, 1987||Aug 9, 1988||U.S. Philips Corporation||Method of manufacturing a bipolar transistor having emitter series resistors|
|US5187117 *||Feb 11, 1992||Feb 16, 1993||Ixys Corporation||Single diffusion process for fabricating semiconductor devices|
|US5789288 *||May 12, 1997||Aug 4, 1998||Sgs-Thomson Microelectronics S.R.L.||Process for the fabrication of semiconductor devices having various buried regions|
|US5895251 *||Feb 19, 1997||Apr 20, 1999||Lg Semicon Co., Ltd||Method for forming a triple-well in a semiconductor device|
|U.S. Classification||438/356, 257/565, 438/527, 438/370, 257/E21.337, 438/371|
|International Classification||H01L29/73, H01L21/265, H01L21/331, H01L27/06, H01L21/8222|
|Mar 31, 1982||AS||Assignment|
Owner name: ITT INDUSTRIES, INC., 320 PARK AVE., NEW YORK, NY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GAHLE, HANS-JUERGEN;REEL/FRAME:003983/0846
Effective date: 19820317
|Aug 11, 1987||FPAY||Fee payment|
Year of fee payment: 4
|Aug 26, 1991||FPAY||Fee payment|
Year of fee payment: 8
|Jan 30, 1996||REMI||Maintenance fee reminder mailed|
|Jun 23, 1996||LAPS||Lapse for failure to pay maintenance fees|
|Sep 3, 1996||FP||Expired due to failure to pay maintenance fee|
Effective date: 19960626