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Publication numberUS4476481 A
Publication typeGrant
Application numberUS 06/384,649
Publication dateOct 9, 1984
Filing dateJun 3, 1982
Priority dateAug 31, 1981
Fee statusPaid
Also published asDE3231676A1
Publication number06384649, 384649, US 4476481 A, US 4476481A, US-A-4476481, US4476481 A, US4476481A
InventorsSusumu Iesaka, Shigenori Yakushiji
Original AssigneeTokyo Shibaura Denki Kabushiki Kaisha
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Low-loss P-i-n diode
US 4476481 A
Abstract
A low-loss P-i-n diode includes an i-type layer consisting of first and second i-type regions formed on the cathode layer of the diode and the i-type has a thickness Wi of less than 25 μm. The impurity concentration of the first i-type region is higher than that of the second i-type region. To obtain a good forward-voltage Vf, Wi 2 /τ is selected to be in the range of 20-200cmcm 2/sec and the carrier lifetime τ of the i-type layer is controlled by a carrier lifetime killer with a small resistivity compensation effect which is diffused into the i-type layer. The P-i-n diode has a high reverse breakdown voltage, small forward-voltage drop and a short recovery time.
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Claims(5)
What we claim is:
1. A P-i-n diode comprising:
a semiconductor substrate of a first conductivity type which functions as the anode of the P-i-n diode;
a first i-type layer of said first conductivity type formed on said semiconductor substrate and having a first thickness W1 ;
a second i-type layer of said first conductivity type formed on the first i-type layer and having a second thickness of W2 ;
said second i-type layer having an impurity concentration lower than that of said first i-type layer;
carrier lifetime killer characterized by a small carrier compensation effect being diffused into said first and second i-type layers whereby said first and second i-type layers have a carrier lifetime of τ; and
a region of second conductivity type diffused into said second i-type layer and having a thickness of W3 which functions as the cathode of the P-i-n diode.
2. The P-i-n diode of claim 1 wherein W1 2 /τ is in the range of 20-200 cm2 /sec where Wi equals W1 +W2 -W3.
3. The P-i-n diode as claimed in claim 1 wherein the carrier lifetime killer is platinum.
4. The P-i-n diode as claimed in claim 1 wherein the thickness W1 of the first i-type layer is less than 5 μm.
5. The P-i-n diode as claimed in claim 1 wherein the thickness W2 of the second i-type layer is approximately 25 μm.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a P-i-n diode, and more particularly to the fabrication and structure of the intrinsic region (i-region) of the P-i-n diode.

2. Description of the Prior Art

The conventional P-i-n diode includes an n+ type cathode layer, an i-type layer, a p-type anode region, an anode electrode connected to the anode region, and a cathode electrode connected to the cathode region. The i-type layer is normally formed by growing an epitaxial layer of low impurity concentration on the cathode region. The p-type anode region is formed by diffusing p type impurity into the i-type layer. Accordingly, the P-i-n diode has a profile of impurity concentration as shown in FIG. 1.

Some of the problems experienced with this type of prior art P-i-n diode include a high forward-voltage drop, on the order of 1 volt, the reverse-recovery time is quite long, for instance 200-300 nanoseconds, and the power loss of the device is high necessitating a radiator.

SUMMARY OF THE INVENTION

An object of this invention is to provide a low-loss P-i-n diode which has a low forward-voltage drop.

Another object of this invention is to provide a low-loss P-i-n diode which has a short reverse-recovery time.

Still another object of this invention is to provide a low-loss P-i-n diode which has a high reverse pulse surge capability.

In accordance with this invention, a P-i-n diode comprises a semiconductor substrate of one conductivity type, a first i-type layer of the one conductivity type formed on the semiconductor substrate, a second i-type layer of the one conductivity type formed on the first i-type layer, the impurity concentration of the second i-type layer being lower than that of the first i-type layer and carrier lifetime killer with a small carrier compensation effect being diffused into the first and second i-type layers, and finally a diffused layer of other conductivity type. The structure of the P-i-n diode is such that Wi2 divided by τ falls in the range of 20 to 200/cm2 /sec. Wi represents the combined thickness of the first and second i-type layers less the thickness of the diffused layer and τ represents the carrier lifetime of the first and second i-type layers.

BRIEF DESCRIPTION OF THE DRAWINGS

This invention will be explained with reference to the accompanying drawings, in which:

FIG. 1 is a profile showing impurity concentration characteristics plotted against the depth of the P-i-n diode.

FIG. 2 shows forward-voltage drop Vf as a function of Wi2 /τ.

FIG. 3 shows forward-voltage drop Vf as a function of current density If for varying carrier lifetimes τ.

FIG. 4 shows minority-carrier current density J as a function of Wi2 /τ.

FIG. 5 shows a profile of the impurity concentration characteristics as a function of depth of the low-loss P-i-n diode in accordance with this invention.

FIG. 6 is a sectional view showing the structure of a low-loss P-i-n diode of this invention.

FIGS. 7A-7G show the process steps for manufacturing a low-loss P-i-n diode as shown in FIG. 6.

FIG. 8 is a profile showing the reverse current IR characteristics with reverse-voltage VR for gold (Au) and platinum (Pt).

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIGS. 1 and 2, an analysis of the operation of a P-i-n diode will be made.

Unless the current density is extremely high, current in both emitter regions of a P-i-n diode is primarily a diffusion current and not a drift current. As a result, the minority carrier currents Jpe and Jne are given by the following expressions: ##EQU1## where P0 and n0 are the minority-carrier densities at the respective emitter edges; q is the unit charge 1.610-19 C; Dpe and Dne are respectively the electron diffusion coefficient in the p emitter and the hole diffusion coefficient in the n emitter; and τpe and τne are respectively the electron lifetime in the n emitter and the hole lifetime in the p emitter.

Total recombination current in the intrinsic region i is equal to the total change in electron or hole current density Jpi, Jni in the i region. ##EQU2## where the origin 0 of the x axis is located at the p-i interface junction and where X=Wi is at the i-n interface junction. The ratio ni0 /n is considered to be negligibly small, and the neutrality condition n(x)=p(x) is assumed. For a short carrier lifetime less than 1 microsecond and relatively low current density levels below several hundred amperes, auger recombination can be neglected. Thus, the following equation holds: ##EQU3## where n(0) and N(Wi) denote carrier densities at the p-i interface junctions respectively, and Vi denotes the potential difference across the intrinsic region i. p0 and n0 are related to n(0) and n(Wi) as shown by the following expressions: ##EQU4## where Nn and Np denote impurity concentrations at the respective emitters and hp and hn denote the ratios of the p-n products between the respective emitter and the intrinsic region i. Heavy doping effects are taken into account by the h factors.

The simplifying approximation that n(x) is substantially constant throughout the intrinsic region i allows us to obtain a simple expression for Vi. This approximation holds if the carrier lifetime is long (ambipolar diffusion length L≳Wi /2) and both the geometrical symmetry of the p and n emitters and the asymmetry of carrier lifetime in the p and n emitters are insignificant. Under the above approximation, the total current Jpe +Jni +Jne is equivalent to the drift current in the intrinsic region i. Thus, the following expression holds:

Jpe +Jni +Jne ≅q(μnp)nEi ( 7)

wherein Ei is the electric field in the i region. Therefore, the voltage drop Vi is given by ##EQU5## Under the above assumption of relatively low current density level and short carrier lifetime, the first two terms in equation (8) can be neglected. For a P-i-n diode having a narrow intrinsic region Wi, this assumption is valid regardless of the length of the carrier lifetime. This is due to the fact that the contribution to the value of Vi of the first two terms is extremely small.

Finally, the total current density J is given by the following equation: ##EQU6## The first term in equation 9 is a diffusion current term while the second is a recombination current term. As can be seen in FIG. 2, the recombination current term for a constant voltage VF is generally inversely proportional to τ and reaches a maximum value at ##EQU7## Below the value τ0, the recombination current decreases exponentially accompanying the decrease in n.

However, the diffusion current for a constant voltage VF almost always decreases with a decrease in τ because τne and τpe are determined by the high impurity in the respective emitters in equation 1 for relatively high τ values.

Equation 9 can be rewritten as a function of Wi 2 /τ and 1/Wi as follows: ##EQU8##

Generally, the latter recombination term is dominant when the carrier density n and the current density are small. For the following analysis, we assume that the value for Wi 2 /τ is kept constant. For a diode with a sufficiently narrow intrinsic region Wi, the recombination current will be dominant even for high current density levels. This is because the current changes proportionally to 1/Wi.

Therefore, the total current at a constant voltage reaches its maximum at Wi 20 =8μi kT/q. This is also the point that the recombination current reaches its maximum. In other words, the forward-voltage for a constant current will have its minimum at Wi 20 =8μi kT/q. As discussed before, the recombination current in the P-i-n diode which has a narrow thickness Wi of the intrinsic layer is 10 times as much as the drift current. For example, in FIG. 2 the current density characteristics as a function of Wi 2 /τ is shown where VF =0.85 V, Wi =10 m or Wi =17 m, μ1 =400/cm2 /V.sec, n0 =1.21010 /cm3, T=300K, τnepe =510-8 sec, hn =hp =10, Dne =Dpe =2 cm2 /sec, and Nn =Np = 51019 /cm3. The solid line curve "a" shows the diffusion current. The solid line curves "b1 " and "b2 " show the recombination current when Wi =10 m and Wi =17 m, respectively. The dotted line curves "c1 " and "c2 " show total current for the two cases respectively.

As shown in FIG. 3, it is clear that by increasing the semiconductor pellet size the forward-voltage drop of a P-i-n diode can be decreased. In FIG. 3 the characteristic of the current density (If) and the forward-voltage drop (Vf) is shown.

However, since the current density If is proportional to the reciprocal to the semiconductor pellet area, it also becomes necessary to greatly increase the pellet size in order to decrease the forward-voltage drop.

Therefore, in accordance with the present invention, measures can be taken to decrease the forward-voltage drop Vf without unnecessarily increasing the semiconductor pellet size. In particular, a relatively small forward-voltage drop is obtained by selecting a suitable value for the term Wi 2 /τ as is obvious from FIG. 4.

Referring now to FIG. 4, there is shown the case where the value of Wi (thickness of the i-type epitaxial layer less the thickness of the p-type anode region as shown in FIG. 6) is equal to 25 μm. In this case, the value of the forward-voltage drop Vf can be changed without varying the semiconductor pellet size. This is so only in those cases when the value of Wi is not large. When Wi is large the forward-voltage drop Vf is substantially constant for varying values of Wi 2 /τ as shown by the dotted line in FIG. 4. When Wi is very large, the forward-voltage drop is not controlled by the value of the carrier lifetime τ because the drift current increases significantly in comparison with the recombination current. Therefore, the total current, i.e., the combination of drift and recombination currents, is not affected significantly by the value of τ. In the case of τ an extremely short lifetime as shown in FIG. 3, the current density If is also not significantly influenced by the value of the forward-voltage drop Vf.

FIG. 4 shows that in the range for W1 2 /τ of 20-200 cm2 /sec the value of the forward-voltage drop Vf can be significantly decreased and indeed optimized. The phenomenon in which minority carrier current density J changes with Wi 2 /τ is also shown by FIG. 2. FIG. 3 shows that the required recombination current is obtained when Wi is less than 25 μm and Wi 2 /τ lies in the range from 20 to 200 cm2 /sec. A typical current density J is 150 A/cm2 which is shown in FIG. 2 where Wi 2 /τ is selected in the range of 20-200 cm2 /sec.

Another consideration in the design of a P-i-n diode is the reverse pulse surge capability of the diode. For instance, in a switching regulator using a P-i-n diode, a spike voltage from a primary coil is often applied to the diode connected to the secondary of the switching regulator. In this type of situation the P-i-n diode must be capable of withstanding a reverse pulse surge. At the same time, it is necessary to diffuse a carrier lifetime killer to obtain a value for Wi 2 /τ which lies between 20-200 cm2 /sec. Such a higher concentration causes an increase in resistivity due to the carrier compensation effect. If the change in resistivity is too large, the depletion layer will extend beyond the thickness of the i layer; that is, a punch-through effect will occur. Therefore, such a diode will have a small reverse pulse surge capability.

This problem is alleviated by the present invention as will be shown in the subsequent discussion. In FIG. 6, a preferred embodiment of the present invention is shown. A low-loss P-i-n diode 10 includes an n+-type anode layer 1, respective i-type epitaxial layers 2 and 3, a p-type cathode region 5, an anode electrode 7 connected to the anode layer 1 and a cathode electrode 6 connected to the cathode region 5. The i-type epitaxial layer consists of a first i-type region 2 and a second i-type region 3, the second i-type region 3 having a lower impurity concentration than that of the first i-type region 2. A carrier lifetime killer, for example platinum (Pt), is diffused into the i-type epitaxial layers 2 and 3 to control the carrier lifetime.

In the embodiment of FIG. 6, platinum (Pt) is a desirable element to use as a carrier lifetime killer since it does not increase the resistivity to the degree that gold (Au) would. Wi and τ are chosen to satisfy the following equation:

Wi 2 /τ=20˜200[cm2 /sec]

The P-i-n diode of FIG. 4 has an impurity concentration profile as shown in FIG. 5. In FIG. 5, the solid line shows a profile of the i-type layer using platinum (Pt) as the lifetime killer and the dotted line curve represents the impurity concentration profile of the i-type layer when gold is diffused as a lifetime killer. Also the impurity concentration of the first i-type region 2 is higher than that of the second i-type region 3. Therefore, the depletion layer ends at the first i-type region 2.

Therefore, the P-i-n diode of FIG. 4 with an impurity concentration profile as shown in FIG. 5 will have a good reverse pulse surge capability. Permanent destruction to the P-i-n diode due to punch-through will not occur. With the present invention as depicted in the embodiment of FIG. 4 a low forward-voltage drop is obtained, the reverse-recovery time is shortened and the reverse pulse surge capability is extremely high. Typical values using the present invention are a forward-voltage drop of 0.86 volts, a reverse-recovery time of 50-60 nanosec and a reverse pulse surge capability of 800 volts.

Referring now to FIGS. 7A-7G, the steps of manufacturing a P-i-n type diode in accordance with the present invention will be described. On an n+-type semiconductor substrate 1 as shown in FIG. 7A, an epitaxial region 2 having a resistivity of approximately 5 ohms and a thickness W1 of approximately 5 μm is formed. A second epitaxial region 3 is formed on the first i-type region 2, the second epitaxial region having a lower impurity concentration than that of the first i-type region 2. The thickness W2 of the second epitaxial region is approximately 20 μm.

A thermal oxide layer 4' is then formed on the second i-type region 3 as a masking layer which is then selectively etched away so as to provide apertures 4A, 4A' . . . as shown in FIGS. 7C and 7D. A p-type impurity such as boron is diffused into the second i-type region 3 through the apertures 4A, 4A' . . . to form a plurality of p+ regions 5 having a thickness W2 of approximately 5 μm as shown in FIG. 7E. The thickness Wi =W1 +W2 -W3. Platinum (Pt) as a lifetime killer is diffused into the first and second i-type regions to control the carrier lifetime. For instance, it can be set at 10-7 -10-8 sec above 900 C. Anode and cathode electrodes 7 and 6 respectively, are formed on the p+ region and the n+ region 1 as shown in FIGS. 7F and 7G. The wafer is then separated into pellets 10, 10', etc.

In the present invention, the permanent destruction which is possible due to excessive surge voltage is prevented by providing the second i-type layer having a lower impurity concentration than the first i-type layer. This construction prevents the punch-through phenomenon.

In accordance with the present invention a high reverse breakdown voltage, for instance above 200 volts and a small forward-voltage drop of for instance 0.85 volts, can be obtained with a very short recovery time of 50-60 nsec.

FIG. 8 shows the profile of the IR -VR characteristics for P-i-n diode using respectively, gold and platinum as the diffused lifetime killer. The different effects on the resistivity of the diode can be seen.

Although this invention has been disclosed with reference to a particular preferred embodiment, the principles involved are capable of other applications which will be apparent to those skilled in the art. The invention is therefore not to be limited to the above disclosure but only as indicated by the scope of the claims to follow.

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Referenced by
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US4594602 *Apr 11, 1984Jun 10, 1986Hitachi, Ltd.High speed diode
US4665428 *Aug 12, 1986May 12, 1987The British Petroleum Company P.L.C.Semiconductor device
US4885622 *Jun 6, 1988Dec 5, 1989Oki Electric Industry Co., Ltd.Pin photodiode and method of fabrication of the same
US5294843 *Oct 26, 1992Mar 15, 1994Semikron Elektronik GmbhFreewheeling diode circuit
US5742092 *Apr 15, 1996Apr 21, 1998Zotov; Vladislav DmitrievichSemiconductor structures, methods for controlling their conductivity and sensing elements based on these semiconductor structure
US5977611 *Apr 6, 1998Nov 2, 1999Siemens AktiengesellschaftPower diode and hybrid diode, voltage limiter and freewheeling diode having the power diode
US6388306 *Jul 18, 2000May 14, 2002Mitsubishi Denki Kabushiki KaishaSemiconductor device with rapid reverse recovery characteristic
US6403989Oct 19, 2000Jun 11, 2002Koninklijke Philips Electronics N.V.Semiconductor device, method of manufacturing same, and circuit provided with such a device
US7737534Jun 10, 2008Jun 15, 2010Northrop Grumman Systems CorporationSemiconductor devices that include germanium nanofilm layer disposed within openings of silicon dioxide layer
US20090302426 *Jun 10, 2008Dec 10, 2009Northrop Grumman Systems CorporationMethod for the Selective Deposition of Germanium Nanofilm on a Silicon Substrate and Semiconductor Devices Made Therefrom
WO2001029899A2 *Oct 4, 2000Apr 26, 2001Koninklijke Philips Electronics N.V.Semiconductor pn-junction diode, method of making the same and electronic circuit comprising the same
WO2001029899A3 *Oct 4, 2000Feb 21, 2002Koninkl Philips Electronics NvSemiconductor pn-junction diode, method of making the same and electronic circuit comprising the same
Classifications
U.S. Classification257/610, 257/E29.086, 257/656, 257/E29.336
International ClassificationH01L29/868, H01L29/167, H01L29/861, H01L21/322
Cooperative ClassificationH01L29/167, H01L29/868
European ClassificationH01L29/167, H01L29/868
Legal Events
DateCodeEventDescription
Jun 3, 1982ASAssignment
Owner name: TOKYO SHIBAURA DENKI KABUSHIKI KAISHA, 72, HORIKAW
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:IESAKA, SUSUMU;YAKUSHIJI, SHIGENORI;REEL/FRAME:004017/0847
Effective date: 19820526
Jun 3, 1986CCCertificate of correction
Mar 29, 1988FPAYFee payment
Year of fee payment: 4
Oct 28, 1991FPAYFee payment
Year of fee payment: 8
Mar 25, 1996FPAYFee payment
Year of fee payment: 12