|Publication number||US4477737 A|
|Application number||US 06/398,033|
|Publication date||Oct 16, 1984|
|Filing date||Jul 14, 1982|
|Priority date||Jul 14, 1982|
|Publication number||06398033, 398033, US 4477737 A, US 4477737A, US-A-4477737, US4477737 A, US4477737A|
|Inventors||Richard W. Ulmer, Roger A. Whatley|
|Original Assignee||Motorola, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (55), Classifications (9), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Related subject matter can be found in U.S. Pat. No. 4,342,926, entitled "BIAS CURRENT REFERENCE CIRCUIT", filed Nov. 18, 1980 by Roger A. Whatley and assigned to the assignee hereof.
This invention relates generally to voltage generators, and, more particularly, to integrated voltage generator circuits which provide a voltage which is reduced from a supply voltage.
Typically, CMOS integrated circuitry has two voltage potentials associated therewith which are known in the art as a supply voltage VDD and a reference voltage VSS. The supply voltage VDD is commonly a more positive voltage than the reference voltage VSS. For circuit operation where the difference in voltage potential between VDD and VSS is approximately eight volts or greater, some processes, such as a silicon gate process, having small device geometries, such as five microns and less, utilize digital logic circuits which may latch-up and maintain false or erroneous data. To overcome this problem, a reduced supply voltage, which is internal to an integrated circuit chip and negative with respect to VDD, is provided to operate digital logic circuits at a sufficiently low voltage to prevent latch-up. Internal reduced supply voltages previously have been provided by coupling a first terminal of a Zener diode to the supply voltage VDD and coupling a second terminal of the Zener diode to both a current source and an input of a buffer amplifier. An output of the buffer amplifier provides the reduced internal voltage. A typical Zener diode has a fixed temperature coefficient of approximately +5 millivolt per degree Centigrade.
Others have used series-connected bipolar type diodes which each have a fixed voltage drop of approximately 0.7 volt to provide an internal reduced supply voltage. Size disadvantages are obvious when a substantially reduced voltage is desired because a plurality of diodes must be used. Further, bipolar diodes display a stable negative temperature coefficient of approximately -2 millivolts per degree Centigrade. Others have also coupled a Zener diode in series with a bipolar diode in an attempt to provide a reduced supply voltage displaying a 0 millivolt per degree Centigrade temperature coefficient. These types of internal voltage generators are intended to produce an internal supply voltage that is substantially independent of process and temperature. However, a fixed supply voltage does not compensate devices powered by the power supply (i.e. inverters, NAND gates, etc.) for propagation delay time as a function of process and temperature.
It is an object of the present invention to provide an improved voltage generator.
Another object of the present invention is to provide an improved voltage generator which tracks temperature and process variations associated with circuitry which the voltage generator is powering.
A further object of the present invention is to provide an improved voltage generator which provides a voltage having a substantially non-zero temperature coefficient of proper sign and magnitude to compensate for propagation delays created by process and temperature variation associated with devices which the voltage generator is powering.
Yet another object of the present invention is to provide an improved integrated CMOS internal voltage generator which tracks process and temperature variations associated with a CMOS circuit with an operating voltage primarily greater than five volts.
In carrying out the above and other objects of the present invention, there is provided, in one form, a voltage generator having reference voltage means comprising two diode-connected devices of opposite conductivity type coupled in series. A first diode-connected device is coupled to a supply voltage and a second diode-connected device is coupled to both a current source and an input of a buffer means. The current source is coupled to a reference voltage. By using the gate-to-source voltage, VGS, of the two diode-connected devices when operated at a specific current by the current source, the buffer means provide an output supply voltage which is reduced a predetermined amount below the supply voltage and which may be used as an internal supply for digital logic. The use of devices having electrical characteristics which are matched to corresponding electrical characteristics of the digital logic allows the voltage generator to provide a voltage which changes with temperature and process variation in such a manner as to substantially cancel the variation of propagation delays over process and temperature.
The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
FIG. 1 illustrates in schematic form a voltage generator constructed in accordance with a preferred embodiment of the present invention; and
FIG. 2 illustrates in schematic form an alternative embodiment of the present invention.
Shown in FIG. 1 is an internal voltage generator 10 which is comprised generally of a reference voltage section 12, a current source section 14 and an output buffer section 16. While specific N-channel and P-channel MOS devices are shown, it should be clear that voltage generator 10 could be implemented by completely reversing the processing techniques (e.g. P-channel to N-channel). Further, it should be clear that voltage generator 10 could be implemented in other processes such as N-channel.
Reference voltage section 12 comprises a P-channel transistor 18 having a source or current electrode coupled to a supply voltage VDD and a gate electrode coupled to a drain or current electrode. An N-channel transistor 20 has a drain or current electrode connected to a gate electrode and coupled to both the gate and drain electrodes of P-channel transistor 18. Current source section 14 comprises a current source 22 which has a first terminal coupled to a source electrode of N-channel transistor 20 and a second terminal coupled to a reference ground potential, VSS. Output buffer section 16 comprises an operational amplifier 24 having a noninverting input coupled to both the source electrode of transistor 20 and the first terminal of current source 22 at a node 26. An inverting input terminal of operational amplifier 24 is coupled to an output terminal which provides an output supply voltage, VSI, which is reduced in magnitude from VDD.
In operation, voltage reference 12 provides a voltage potential equal to the sum of the gate-to-source voltages of transistors 18 and 20 between node 26 and supply voltage VDD. Since node 26 is a high impedance node, operational amplifier 24 buffers the output voltage and provides a low impedance output. The output supply voltage VSI exists at the output of operational amplifier 24, for operating digital logic (not shown) at a reduced supply voltage equal to the difference in potential between VDD and VSI. In this application, VDD and VSI are known as supply rails. Digital logic commonly includes inverter circuits which have a propagation delay, td, associated therewith. The propagation delay may be represented mathematically as a function of process, temperature, supply voltage, device geometry and loading characteristics. The output voltage of the circuit shown in FIG. 1, VDD -VSI, is a function of process, temperature, device geometry, and bias current. In particular, both the propagation delay of digital logic and the digital supply voltage VDD -VSI are functions of process and temperature. Because the digital logic and voltage generator are fabricated on the same integrated circuit chip in close thermal proximity, the change in one tends to track changes in the other. For example, under given process conditions, if the operating temperature is elevated the propagation delay of MOS inverters is increased. However, the supply voltage VDD -VSI is also increased and thus tends to compensate for changes in propagation delay. At a given temperature, if the processing is worse than nominal, the supply voltage VDD -VSI increases to compensate the slower propagation delay that would have resulted from using a fixed supply voltage. Therefore, voltage reference 12 tracks temperature and process variations in a manner so as to substantially cancel the propagation delay dependence on temperature and process of any coupled logic gates operating at a VDD -VSI potential. It should be clear that voltage reference 12 may also be implemented as a diode-connected device of the same process type as the digital circuitry or as a plurality of diode-connected devices.
Although reference voltage section 12 of FIG. 1 varies the difference in potential between VDD and VSI with variations in temperature and process, current source 22 has not been described as varying with temperature and process. Shown in FIG. 2 is another embodiment of the invention wherein voltage generator 10 comprises a reference voltage section 12, a current source section 14 and an output buffer section 16. In this embodiment, current source section 14 provides a bias current for reference voltage section 12 wherein the bias current is also process and temperature varying in the same manner as the devices which may be powered by voltage generator 10.
Reference voltage section 12 again comprises P-channel transistor 18 having a source electrode coupled to a supply voltage VDD and a gate electrode coupled to a drain electrode. As in the previous embodiment, N-channel transistor 20 has a drain electrode connected to a gate electrode which are both coupled to both the gate and drain electrodes of P-channel transistor 18.
Current source section 14 comprises a P-channel transistor 28 having a source electrode connected at a node 26 to both a source electrode of transistor 20 and a noninverting input of operational amplifier 24. Transistor 28 has both a gate electrode and a drain node 26 to both a source electrode of transistor 20 and a noninverting input of operational amplifier 24. Transistor 28 has both a gate electrode and a drain electrode connected together. An N-channel transistor 30 has a drain electrode connected to both the drain and gate electrodes of transistor 28 and a source electrode coupled to the reference ground potential VSS. A resistor 32 has a first terminal coupled to supply voltage VDD and a second terminal coupled to a source electrode of a P-channel transistor 34. Transistor 34 has a gate electrode connected to both the gate and drain electrodes of transistor 28. An N-channel transistor 36 has a drain electrode connected to its gate electrode and both drain and gate electrodes are connected to both a drain electrode of transistor 34 and the gate electrode of transistor 30. A source electrode of transistor 36 is coupled to the reference ground potential VSS.
Output buffer section 16 again comprises operational amplifier 24 having a noninverting input coupled to both reference voltage section 12 and current source section 14 at node 26, and an inverting input coupled to an output, for providing output voltage VSI.
In operation, a varying voltage equal to the sum of the gate-to-source voltages of transistors 18 and 20 is reflected across resistor 32. The gate-to-source voltage of transistors 18 and 20 creates a current, I, through resistor 32 which is determined in part by the value of resistor 32. The current I flows through transistors 34 and 36 and is mirrored by transistors 30 and 36 to also flow through transistor 28. When the gate widths and lengths of transistors 28 and 34 and transistors 30 and 36 are substantially identical, the same current flows through transistors 28 and 34. Therefore, the current flowing through transistors 18 and 20 is controlled by the process variation of the VGS of transistors 18 and 20. The result of this is to cause an even greater variation of (VDD -VSI) as a function of process and temperature than in the circuit of FIG. 1, resulting in improved compensation of digital propagation delay. In FIG. 2, the noninverting input of operational amplifier 24 may be coupled to the source electrode of transistor 34 rather than to node 26. The same voltage exists at both points provided transistors 28 and 34 and transistors 30 and 36 are respectively identical.
By now it should be appreciated that a voltage generator which provides a reduced internal supply voltage for integrated digital logic circuits has been provided. Further, the internal supply voltage varies with respect to process and temperature changes in a manner analogous to the same variation in the digital logic circuits.
While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.
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|U.S. Classification||327/541, 327/576, 327/543, 323/316, 327/513, 327/562|
|Jul 14, 1982||AS||Assignment|
Owner name: MOTOROLA,INC SCHAUMBURG IL A CORP OF DE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:ULMER, RICHARD W.;WHATLEY, ROGER A.;REEL/FRAME:004027/0266
Effective date: 19820713
|Mar 7, 1988||FPAY||Fee payment|
Year of fee payment: 4
|Feb 27, 1992||FPAY||Fee payment|
Year of fee payment: 8
|Feb 20, 1996||FPAY||Fee payment|
Year of fee payment: 12