|Publication number||US4491241 A|
|Application number||US 06/338,641|
|Publication date||Jan 1, 1985|
|Filing date||Jan 11, 1982|
|Priority date||Jul 21, 1980|
|Publication number||06338641, 338641, US 4491241 A, US 4491241A, US-A-4491241, US4491241 A, US4491241A|
|Inventors||John T. Knepler, Wesley J. Bachman|
|Original Assignee||Dickey-John Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (20), Referenced by (17), Classifications (9), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation-in-part of prior application Ser. No. 170,719, filed July 21, 1980, and now abandoned.
The present invention is directed generally to the monitoring arts and more particularly to a monitor for complex machinery such as agricultural machinery. While the invention is useful for monitoring the operation of any of a broad variety of machines, the disclosure will be facilitated by specific reference to a field seed planter or grain drill.
A framer engaged in the mechanized planting of seeds or grain generally utilizes a seed planting machine pulled behind a tractor or the like. Modern seed planting machines generally include a plurality of individual planting units which receive seed or grain from one or more hoppers and distribute the seed to individual rows for planting, so that a plurality of rows may be planted in a single pass over the field. In the planting of such crops as corn or soybeans, the planting machine may include as few as four to as many as twenty-four individual planting units, while machinery for planting grain crops such as wheat may include as many as forty or more individual planting units.
Many arrangements have been heretofore proposed for monitoring the operation of a plurality of such individual planting units in the planting machine and providing a suitable display or other observable indication thereof to a console conveniently mounted to be observed in the tractor cab. The systems heretofore provided, however, have generally required a separate signal lead or wire from a sensor unit associated with each planting unit back to the cab-mounted console.
While such an arrangement has proven quite useful for the planting of corn or soybean seeds in planting machines containing up to 24 planting units, the additional wiring requirements for typical grain drill machines containing 40 or more planting units has presented some difficulty. For example, the proper cabling and interconnection of 40 or more such separate signal leads would prove quite cumbersome and difficult in field assembly of such a monitoring system for all but the highly skilled technician. However, provision of a pre-assembled package of cables and connectors for accommodating such a large number of leads may be economically unfeasable due to the expense it would add to the purchase price of such a preassembled monitoring system. Moreover, since various makes and models of planting machinery and tractors would require different lengths of cables and different configurations of leads, cables and connectors, it would be difficult if not impossible to provide a suitable preassembled cable and connector package for any conceivable arrangement or combination of equipment upon which the monitoring system is to be installed.
Additionally, such a complex cabling and connector arrangement might lead not only to error in the proper assembly of the monitoring equipment in the first instance but also to an increased frequency of equipment failure or malfunction in the field. Moreover, a farmer faced with such equipment failure might well find it difficult or impossible to locate and remedy the source of the equipment malfunction, without the aid of a skilled technician. Since the purpose of such large-scale, multiple row planting equipment is to maximize the acreage which may be planted during the optimum time in the planting season, such an increased frequency of equipment malfunction and the relatively time-consuming repair procedure is clearly undesirable.
Accordingly, it is a general object of this invention to provide a new and improved monitor for a complex machine such as a field planting machine which substantially avoids the problems encountered with prior art devices.
A more specific object is to provide a monitor of the type described which includes relatively simple wiring requirements, so as to be readily assemblable or repairable even by a relatively unskilled worker.
Another object is to provide a monitor of the type described which is relatively simple and economical in its design and manufacture and yet highly reliable in operation.
Briefly, and in accordance with the foregoing objects, the present invention provides a monitor for a machine having a plurality of operating parts and a plurality of sensors respectively associated with the operating parts. The monitor comprises a plurality of sensor circuit means coupled in series circuit, one of said sensor circuit means being coupled intermediate each of said sensors and a common signal line. The sensor circuit means and the associated sensors are sequentially selectable for causing a first condition on said common signal line in response to the production of a predetermined signal by a selected sensor and a second condition on said common signal line in response to the non-production of said predetermined signal by a selected sensor.
Other objects, features and advantages of the invention will become more readily apparent upon reading the following detailed description of the illustrated embodiment, together with reference to the accompanying drawings wherein:
FIG. 1 is an electrical circuit diagram, primarily in block form, of a novel monitoring system according to the present invention;
FIG. 2 is a circuit diagram, partially in block form, showing additional detail of a sensor circuit portion of the monitoring system of FIG. 1;
FIGS. 3A and 3B, taken together form a detailed circuit diagram of a monitoring circuit portion of the monitoring system of FIG. 1;
FIG. 4 is a detailed circuit diagram of the circuit of FIG. 2;
FIG. 5 is a simplified schematic circuit diagram of a termination portion of the monitoring system of FIG. 1;
FIG. 6 illustrates an alternate embodiment of the circuit of FIGS. 3A and 3B;
FIG. 7 is a schematic circuit diagram of a modified sensor circuit for accommodating a hopper level sensor;
FIG. 8 is a schematic circuit diagram of a modified termination circuit;
FIG. 9 is a schematic circuit diagram of a further hopper level sensor circuit portion useful with the circuit of FIG. 7;
FIG. 10 is a schematic circuit diagram of another modified form of a sensor circuit for use with the circuit of FIGS. 1A and 1B;
FIGS. 11A and 11B, together form a schematic circuit diagram illustrating another embodiment of a monitoring circuit; and
FIG. 12 is a schematic circuit diagram of an area monitor circuit useful with the circuit of FIGS. 11A and 11B.
Referring now to the drawings, and initially to FIG. 1, a novel monitoring system in accordance with the invention is illustrated. A plurality of seed sensors, such as sensors indicated by reference numerals 10 and 12, are associated with the respective planting units of a field planter having a plurality of such planting units. While the illustrated embodiment is intended for use with a grain drill having 40 or more planting units, the invention is not so limited, but may be readily utilized with other machines in which a plurality of parts are to be monitored.
Briefly, the seed sensors 10, 12 are responsive to the dispensing of seeds by the associated planting units for producing electrical signals. A sensor circuit or transfer cell 14, 16 is coupled intermediate each of the sensors 10, 12 and a common signal line 18. For convenience of illustration, only the first sensor 10 and its associated sensor circuit 14 and a last sensor 12 and its associated sensor circuit 16 have been illustrated in FIG. 1, it being understood that 40 or more such sensors and sensor circuits are utilized, one for each planting unit on the planting machine to be monitored. Additionally, each of the sensor circuits 14, 16 is provided with a positive voltage supply and a circuit ground connection. A ground is also provided for each sensor 10, 12.
In accordance with a feature of the invention, these sensor circuits 14, 16 are coupled in series circuit, the first sensor circuit 14 being fed by an enable line 20. The common signal line 18 and enable line 20 are coupled at their opposite ends with a monitoring and control circuit portion designated generally by the reference numeral 22. This monitoring and control circuit 22 also drives a suitable alarm indicator 24 and a suitable visual display 26. This latter display 26 is energized by way of a suitable display driver circuit 28.
At the end of this series-connected string of sensor circuits 14, 16 is provided a termination circuit 17. As will be more fully described later, this termination circuit 17 provides a suitable signal indicating that the condition of all seed planting units has been monitored and that the monitoring system may repeat a monitoring sequence, starting from the first sensor circuit 14 and its associated sensor 10 and planting unit.
In operation, the sensor circuits 14, 16 and associated sensors are individually and sequentially selectable for causing a first signal condition on the common signal line 18 in response to the production of a seed signal by the associated one of the seed sensors 10, 12 and a second condition on the common signal line 18 in response to the non-production of a seed signal by the associated one of the seed sensors 10, 12. The monitoring circuit 22 provides suitable signals on the data line 18 and the enable line 20 for sequentially selecting the series-coupled sensor circuits 14, 16, and is further responsive to the first and second signal conditions on the common signal line 18 for producing suitable control signals to the display driver 28 and alarm 24.
In operation, if the planting unit associated with the sensor 10, for example, is not dispensing seeds, when the associated sensor circuit 14 is selected by the monitoring circuit 22, the second signal condition will be detected on the line 18. In response to this signal condition on the line 18, the monitoring circuit will energize the display driver 28 to cause a display on the display unit 26 of a suitable failure signal and a number or other symbol identifying the planting unit associated with the sensor 10. Simultaneously, the monitoring circuit 22 will produce a suitable control signal for energizing the alarm 24 which may take the form of an audible alarm. Should all of the planting units associated with the sensors 10, 12, etc., be dispensing seeds properly, the monitoring circuit 22 will detect only the corresponding first indication signal on the common signal line 18 and hence will not energize the display 26 and alarm 24, which serve primarily as failure indicators to the operator. Hence, in the absence of energization of the display 26 and alarm 24, the operator is assured that all of the planting units of the planting machine are dispensing seeds properly and may continue the planting operation.
Referring now to FIG. 2, a typical sensor circuit, such as the sensor circuit 14, is illustrated in equivalent logic form. In accordance with the feature of the invention, each sensor circuit includes an enable input portion 30 and an enable output portion 32. In the illustrated embodiment, the enable input portion 30 and enable output portion 32 each comprises a flip-flop circuit FF1, FF2 having a set input S, a reset input R, and Q and Q outputs. The Q outputs Q1, Q2 of the flip-flops 30 and 32 feed two inputs of a three-input gate circuit 34. The remaining input of this three-input gate circuit 34 is fed from the sensor element 10 by way of circuit 36, here schematically shown, which functions as a one-shot. This one-shot circuit 36 comprises an NPN transistor 40 and an inverter buffer circuit 38 in series between one terminal of sensor 10 and the base electrode of the transistor 40. The collector electrode of the transistor 40 feeds the third input of the gate circuit 34. A suitable capacitor 42 is joined between the collector electrode of the transistor 40 and ground, and a suitable biasing resistor 44 joins the collector electrode of the transistor 40 with a suitable positive voltage supply. The emitter electrode of the transistor 40 and the remaining terminal of the sensor element 10 are tied to ground. Further details of the circuit 36 are illustrated in FIG. 4.
In the illustrated embodiment, the sensor 10, which comprises one of the sensors 10, 12, etc., of FIG. 1, comprises a piezoelectric element. Such a piezoelectric element is particularly suitable for use with grain drill planting units of a grain planting machine. However, other types of sensor elements may be utilized without departing from the principles of the invention. Briefly, as each seed or grain impinges upon the piezoelectric sensor 10, the sensor emits a responsive electrical signal pulse to the inverter buffer circuit 38 which forms the input of the one shot circuit 36. Accordingly, the one-shot circuit 36 is triggered by each signal pulse received from the sensor element 10. The value of the capacitor 42 determines the period of the one-shot circuit 36, which therefore functions as a one-bit memory for storing a seed pulse for this period. Hence, if a seed is dispensed triggering the one-shot 36, a logic zero is input to the gate circuit 34 for the duration of the one-shot "memory" period. Otherwise, this input to the gate 34 will be held substantially at a logic 1 level.
The output of the gate circuit 34 feeds the common signal line 18 by way of a series-connected diode 46 and resistor 48. The diode 46 has its anode electrode joined with the resistor 48 and its cathode electrode joined with the output of the gate circuit 34.
Consequently, if a logic 0 (i.e., a "memorized" seed pulse) is fed to the gate 34 from the "memory", the gate 34, which is an inverting gate, will produce a logic 1 signal to the common signal line 18. However, if there is no "memorized" seed pulse, a logic 1 is fed to the gate 34 and the gate circuit 34 will pull the common signal line 18 toward a logic 0 level. Advantageously, however, the level will vary from the nominal logic 0 of the circuit sufficiently, due to provision of the resistor 48, so as to produce a recognizable failure signal level on the line 18. The monitoring circuit 22 recognizes this failure signal as indicating failure of the associated seed planting unit to dispense seeds at or above the predetermined rate.
Referring again to the flip-flop circuits 30 and 32, it will be seen that the reset input R1 of the flip-flop 30 receives an enabling signal from the monitoring circuit 22 on the enable line 20, while the Q1 output of the flip-flop 30 feeds the reset input R2 of the flip-flop 32. The Q2 output of the flip-flop 32 feeds the set input S1 of the flip-flop 30 by way of an intervening series-connected inverter buffer 50 and a time delay element 52. The set input S2 of the flip-flop 32 is connected to receive the signal on the common signal line 18. The Q2 output of the flip-flop 32 also feeds an enable signal output line 20a which feeds the enable input circuit of the next succeeding sensor circuit, which input comprises the reset input of a flip-flop corresponding to the flip-flop 30.
In operation, the enable input flip-flop 30 is responsive to the enabling signals received on the enable line 20 from the monitoring circuit 22 for producing an enabling output signal on its Q output to the gate circuit 34. Hence, the gate circuit 34 effectively allows the resulting signal from the sensor 10 to be passed on to the common signal line 18 by way of the diode 46 and resistor 48.
Referring again to the enable input circuit 30 and enable output circuit 32, the set input of the flip-flop 30 is initially at a logic 1 state and consequently the Q1 output is also at logic 1, effectively disabling response to the "memory" at the gate 34. Upon reception of a first positive enable pulse at the reset input R1 of the flip-flop 30, the Q1 output reverts to a logic 0 or low state, while the Q2 output of the flip-flop 32 remains at a logic 0 state due to the low transition of the clock pulse on line 18 at the set input S2 thereof and the logic 0 state at the reset input R2 thereof received from the Q1 output of the flip-flop 30.
Accordingly, the gate circuit 34 is enabled for effectively interrogating the sensor 10 by ascertaining the condition of the one-shot "memory" 36 associated therewith. If the memory 36 is held at a logic 0 state by continued detection of delivery of seeds at the sensor 10, the output of the gate circuit 34 will remain in a high or logic 1 condition, and hence have no effect on the production of normal periodic clock signal levels on the common signal line 18. Hence, the next transition high of the clock signal on the line 18 will set the flip-flop 32, causing a logic 1 condition on its Q2 output, effectively disabling the gate circuit 34 and passing an enable signal out on the line 20a to the next succeeding sensor circuit.
In this regard, the set input S2 of the flip-flop 32 is driven low by the low transition of the clock signal substantially simultaneously with the high transition of the enable signal at the reset input R1 of the flip-flop 30, hence enabling the low transition of the Q2 output of the flip-flop 32 in response to the logic 0 signal received at the reset input R2 thereof from the Q1 output of the flip-flop 30. Immediately thereafter, the Q2 output of the flip-flop 32 is driven to its logic 1 or high state, temporarily pulsing the set input S1 of the flip-flop 30 to a logic 0 state to permit the resetting thereof by the enable pulse received on the line 20. If the gate 34 allows the next succeeding positive clock transition on the line 18, however, the set input S2 of the flip-flop 32 will again be driven to a logic 1 state, driving the Q2 output thereof to the logic 0 state at the same time as the transition of the Q2 to the logic 1 state, hence preventing succeeding enable signals received on the line 20 from enabling the sensor circuit 14 by again resetting the flip-flop 30.
Referring briefly to FIG. 4, a detailed circuit diagram of a typical sensor circuit 14 illustrates preferred forms of the components illustrated in equivalent logic form in FIG. 2. The enabling input circuit or flip-flop 30 is formed from a pair of NAND gates 30a and 30b, while the enabling output circuit or flip-flop 32 is similarly formed from a pair of NOR gates 32a and 32b. The inverter 50 comprises a two-input NAND gate having its two inputs tied together to the Q2 output of the flip-flop 32. The time delay element 52 comprises a capacitor joined in series between the output of the gate 50 and the set input of the flip-flop 30. The gate circuit 34 comprises a two-input NOR gate 34a which receives the Q1 and Q2 outputs of the flip-flops 30 and 32 and whose output feeds one input of a two-input NAND gate 34b. The remaining input of the NAND gate 34b is fed from the capacitor 42, of the circuit 36 associated with the sensor 10. The inverter buffer 38 is formed from a two-input NOR gate 38a having one input tied to the sensor 10 and a second input tied to ground. A suitable feedback resistor 54 joins the output of the gate 38a with its input from the sensor 10. A capacitor 56 is interposed between the output of the gate 38a and the base electrode of the transistor 40 and a resistor 58 runs to ground from the junction of these two components. The capacitor 42 and the resistor 44 as well as the diode 46 and resistor 48 are the same as illustrated in FIG. 2.
Reference is next invited to FIG. 5 wherein a preferred form of the termination circuit 17 is illustrated. The last enabling input line 20n feeds the base electrode of a transistor 60 by way of a series-connected resistor 62. A suitable resistor 64 joins the base electrode of the transistor 60 with ground while a capacitor 66 is interposed between the base electrode and the collector electrode thereof. The common signal line 18 feeds the collector electrode of the transistor 60 by way of a suitable series-connected resistor 68, while the emitter electrode of the transistor 60 is grounded. Accordingly, upon reception of the enabling output signal on the line 20n from the last of the series-connected sensor circuits, the transistor 60 will be switched on, effectively grounding the common signal line 18. This ground condition will be substantially at circuit ground which is at a recognizable level somewhat lower than the nominal logic 0 level. This ground signal will result in suitable signal levels on both the line 18 and the enable line 20 from the monitoring and control circuit 22 for effectively resetting all of the sensor circuits 14, 16, etc., in a ripple-effect fashion, so as to permit a subsequent "scan" through the series-connected sensor circuits for determining the condition of the respective associated sensors.
Reference is next invited to FIGS. 3A and 3B wherein a first exemplary embodiment of the monitoring and control circuit 22 is illustrated in schematic form. Referring initially to FIG. 3A, at the lower left hand portion, a master clock oscillator is formed utilizing an operational amplifier (op amp) 70. A feedback resistor 72 joins the inverting input of the op amp 70 with the output thereof and a suitable capacitor 74 is joined between the inverting input and ground. The non-inverting input of the op amp 70 is provided with a similar feedback resistor 76 to the output thereof, either side of the resistor 76 being coupled with a positive voltage supply by way of suitable intervening resistors 78 and 80. A further resistor 82 ties the non-inverting input of the op amp 70 to ground, thereby completing the oscillator. The oscillations at the output of the op amp 70 are fed to display frequency input terminals of three display driver elements 84, 86, and 88 which form the display driver 26 of FIG. 1.
In the illustrated embodiment, the display driver element 84 is of the type generally designated 4054 while the elements 86 and 88 are the type generally designated 4055. These display drivers 84, 86 and 88 energize a liquid crystal display (LCD) 90, which in the illustrated embodiment comprises three seven-segment display characters. The back plate, decimal point characters and unused character segments are driven to suitable potentials by the strobe output 89 of the display 88.
In the illustrated embodiment, the liquid crystal display (LCD) 90 and display drivers 86 and 88 are interconnected so as to display two numerals identifying any failed planting unit. The display driver 84 controls display character segments to display alpha-numeric F indicating a failure of the planting unit whose identifying number is simultaneously displayed. The display drivers 86 and 88 are driven by a pair of quad OR gates 92, 94, each OR gate therein receiving one input from a common line 96 and the other input from the outputs of a dual up-counter 98, which is wired as a two-digit BCD counter. The inputs of the display driver 84 are driven from suitable logic including an inverter 100 driven from the output of an OR gate 102, one of whose inputs is tied to the signal line 96 and the other of whose inputs is fed from a Q1 output of a dual flip-flop circuit 104. The highest stage output of the counter 98 drives the first clock input C1 of the dual flip-flop 104 by way of an inverter buffer 105. A second Q2 output of the dual flip-flop 104 drives a further input of display driver 84 while the remaining input thereof is driven from the output of a two-input OR gate 103, both of whose inputs are tied to the third stage of the most significant digit of the counter 98 and by way of a diode 108 to the Q1 output of the dual flip-flop 104.
A suitable audible alarm 24 has one terminal tied to a positive voltage supply and the other terminal tied to the collector electrode of a transistor 112 whose emitter electrode is grounded. Accordingly, the alarm will be energized when the transistor is switched to an ON state at its base electrode. This base electrode is tied to the output of a two-input OR gate 114 by way of a suitable intervening resistor 116. One input of this OR gate 114 is fed from the output of the OR gate 103 while the remaining input thereof is fed from the Q2 output of the dual flip-flop 104.
Referring now also to FIG. 3B, a seven-stage binary counter 120 takes its count input C from the oscillator signal provided at the output of the op amp 70. This same oscillator signal also feeds the base electrode of an NPN transistor 122 by way of a resistor 124, the transistor 122 comprising an electronic switch element. The base electrode of the transistor 122 is also provided with a suitable resistor 126 to ground while the emitter electrode thereof is grounded. The collector electrode of the transistor 122 receives a positive potential by way of a pair of series-connected resistors 128 and 130, the junction of which is coupled to the common signal line 18. Accordingly, the periodic clock signal on the common signal line 18 is effectively an inverted version of the oscillator output signal, derived from the action of the electronic switch comprising the transistor 122. The last stage output Q7 of the counter 120 drives a further electronic switch comprising a PNP transistor 174, by way of an inverter buffer 176 and a resistor 178 in series to the base electrode thereof. Suitable biasing and pulse shaping is provided at the base electrode of the transistor 174 from the junction of a resistor 180 and capacitor 182 tied in series between a positive potential ground. The emitter electrode of the transistor 174 is tied to a positive potential while the collector electrode thereof is fed to the common signal line 18.
The oscillator signal from the output of op amp 70 also feeds a first reset input R1 of a dual flip-flop circuit 132 by way of a differentiating or pulse forming circuit comprising a capacitor 134 in series to the R1 input and a resistor 136 from the R1 input to ground. The set inputs S1, S2 of the dual flip-flop 132 are tied to ground while the inputs D1 and D2 thereof are tied to a positive voltage supply. The first clock input C1 and second reset input R2 of the dual flip-flop 132 are both tied to the common signal line 18, while the second clock input C2 thereof is tied to the Q2 or second stage output of the counter 120. The Q1 output of the dual flip-flop 132 drives the reset input R of the counter 120 while the Q2 output thereof drives the signal line 96 of FIG. 3A. This signal line 96 also feeds the second reset input R2 of the dual flip-flop 104 by way of a series-connected inverter buffer 138.
A termination detector circuit for detecting the termination signal provided by the termination circuit 17 as discussed above, comprises an operational amplifier (op amp) 140 whose inverting input is joined with the common signal line 18 by a pulse forming network comprising a series-connected resistor 142 and a capacitor 141 to ground. The non-inverting input of this op amp 140 is biased by a voltage divider comprising a pair of resistors 144 and 146 in series between a suitable positive potential and ground. The op amp 140 is further provided with a suitable feedback resistor 148 between its output and its non-inverting input and the output is biased by a further resistor 150 tied to a positive potential. The output of the op amp 140 also energizes the reset inputs R1, R2 of the counter 98 and the reset input R1 of the dual flip-flop 104 of FIG. 3A via a line 152. The enable signal line 20 is also derived from the output of the op amp 140 by way of a series-connected resistor 154 and inverter buffer 156. The junction of the resistor 154 and the inverter buffer 156 is also provided with a capacitor 158 to ground to provide suitable pulse shaping.
The biasing of the op amp 140 is such that the enable signal will remain at a high or logic 1 state at all times, that is, so that the clock signals on the line 18 will not drive the op amp to its low or logic 0 output state. However, upon encountering the termination detector, which it will be remembered presents a relatively lower, ground signal level, the op amp 140 will be momentarily switched to its opposite state to drive the enable line to a low or logic 0 level state.
A suitable circuit for providing the correct logic signals upon "power up" or initial energization of the circuits of FIGS. 3A and 3B is also provided in FIG. 3B. This circuit utilizes an NPN transistor 160 whose collector electrode is tied to the inverting input of op amp 140 and whose emitter is grounded. A suitable switching signal on "power up" is supplied to the base of the transistor 160 from the output of a two-input OR gate 162 by way of a suitable series-connected resistor 164. The two inputs of the OR gate 162 are tied together and received a suitable "power up" pulse from a positive voltage supply by way of a series-connected capacitor 166 and resistor 168. A feedback resistor 170 is tied between the output of the OR gate 162 and its inputs, and a suitable biasing resistor 172 is also provided at the junction of the capacitor 166 and resistor 168.
In operation, the periodic clock signal provided on the line 18 repeatedly clocks the R2 input of the dual flip-flop 132, resulting in a logic 1 signal at its Q2 output on the line 96. This logic 1 signal on the line 96 holds all of the quad OR gates 92 and 94 high, thereby disabling the display drivers 86, 88 and blanking the numeric characters of the LCD 90 utilized to identify a failed planting unit. This logic 1 level on the line 96 also effectively disables the display driver 84 by way of the above-described intervening logic elements, thereby blanking the failure character of the LCD 90. As the series-connected sensor circuits are enabled and interrogated one-by-one if no failure is detected, the clock signal on the line 18 will continue its periodic excursion between logic 1 and logic 0 uninterrupted, thus holding the display in its blanked condition, while at the same time advancing the count held in the counter circuit 98 by way of the enable input E1 thereof. Hence, the state of the counter 98 will always comprise a BCD digit, corresponding to the numerical identity of the sensor circuit and associated planting unit currently being interrogated.
Moreover, upon the normal, uninterrupted clock transitions on the common signal line 18, the counter 120 is repeatedly reset due to the application of the clock signal on the line 18 to the count input C1 of dual flip-flop 132, whose Q1 output then resets the counter 120 at its R input. However, upon encountering a failed sensor condition, it will be remembered that the clock signal on the common signal line is not allowed to return to its nominal logic level but is instead pulled to a low signal level. Accordingly, the counter 120 will not be reset when this condition is encountered but will begin to count the clock pulses presented at the count input C thereof, directly from the op amp 70. The second clock pulse thus received will be fed from the Q2 output of the counter 120 to the C2 input of the dual flip-flop 132, causing a logic 0 on the Q2 output thereof and thus on the line 96, enabling the quad OR gates 92 and 94 and other logic and removing the blanking condition from the LCD 90. Accordingly, the identifying number of the failed planting unit held in the counter 98 will be displayed in the digits of the LCD 90, together with the failure display character "F". The same signal transition on the line 96 will reset the R2 pin of dual flip-flop 104, thus triggering the audible alarm 110 by means of a logic signal at the Q2 output thereof.
In one-half to one second, depending upon the frequency of operation chosen for the oscillator comprising the op amp 70 and related components, the counter 120 will reach its last stage, emitting a logic 1 signal from its Q7 output. This logic 1 signal will switch the transistor 174 on, thus once again pulling the line 18 to its logic 1 or high state. As described above with reference to FIGS. 2 and 4, when the line 18 is again returned to its logic 1 or high state, it will be remembered that the sensor circuit effectively disables or discontinues the interrogation of the associated sensor and passes the enabling signal on to the next succeeding series-connected sensor circuit. Accordingly, the clock signal on the common signal line 18 will resume its periodic transitions, to interrogate remaining sensors in the same fashion.
Accordingly, the sequential scan of the series-connected sensor circuits will continue, interrupted only for the one-half to one second failure display and alarm upon encountering sensor circuits whose associated planting units are not dispensing seeds at or above the predetermined rate. Upon encountering the termination circuit 17, the resulting signal state transition of the op amp 140 will reset the counter 98 by way of the line 152, to resume counting from 0 as the scan of the series-connected sensor circuits is repeated starting with the first sensor circuit. The signal on the line 152 also resets the dual flip-flop 104. Should a malfunction occur in the termination circuit 17 or the termination sensing arrangement comprising the op amp 140 in related components, the counter 98 will continue to count upwardly, thus triggering the failure signal and the audible alarm by way of the intervening logic elements including the inverter buffer 105, OR gate 103 and dual flip-flop 104, whose interconnections are described above. Accordingly, as a failure signal "F" will be displayed without a planting unit identifying number, the operator will be alerted to check for the proper connection of the termination unit at the end of the string of series-connected sensor circuits.
Referring now to FIG. 6, an alternate embodiment of the monitoring and control circuit 22 is illustrated. In this embodiment, the majority of the logic functions described above with reference to FIGS. 3A and 3B are carried out by a microprocessor component 200 which may be any of a plurality of known microprocessor elements commercially available. The programming of such a microprocessor will be apparent to one skilled in the art upon the following description of the function thereof.
The microprocessor 200 is provided with five input/output ports, identified as port 1, port 2, etc., in FIG. 6. Port 1 receives the output signal from the termination detector, operational amplifier 140, which is the same as that illustrated and described above with reference to FIG. 3B. An internal oscillator circuit provides a clock signal output at port 3 which drives the clock input of an N-bit shift register 202 and an electronic switch 204 for driving the common signal line 18 from a suitable positive potential B+. This switch circuit 204 may comprise the transistor 122 and related circuit elements described above with reference to FIG. 3B or any other suitable equivalent electronic switching circuit.
Port 2 of the microprocessor 200 receives an input signal from a second, similar operational amplifier 206, which is provided with suitable biasing components similar to those described above with respect to the op amp 140 of FIG. 3B. The reference potential or biasing level provided to the op amp 206 is such, however, as to activate port 2 of the microprocessor 200 upon encountering a failed planting unit. It will be remembered that the signal level presented on the common data line 18 by the sensor circuits in response to a failure of a planting unit to dispense seeds is somewhat different from the normal or nominal logic 1 and 0 levels provided by the clock signal thereon. Accordingly, the op amp 206 is referenced to this "failure" signal level. Port 4 of the microprocessor 200 comprises a serial data output port to a serial data input of the N-bit shift register 202. The N parallel outputs of the N-bit shift register 202 feed the display driver 28 for the display 26, which may take the form illustrated and described with reference to FIG. 3A. Alternatively, the display may contain any desired number of display elements comprising some number N of segments or ports to be driven by the N-bits of the N-bit shift register 202 to provide a suitable display as desired. An additional output is provided at port 5 of the microprocessor 200 for driving the audible alarm element 24 by way of a suitable transistor 112 and resistor 116, in similar fashion to that illustrated and described above with reference to FIG. 3A.
In operation, the microprocessor 200 effects a relatively rapid sequential scanning of the sensor circuits 14, 16, etc., preferably at a rate of on the order of 10 kHz. If a failed planting unit is detected, the corresponding signal provided by the op amp 206 to port 2 of the microprocessor 200 will be internally stored therein, together with suitable data, generated internally, identifying the failed planting unit. Data corresponding to the failed planting units encountered may then be read out of the microprocessor 200 for display whenever desired by actuation of a "write" terminal thereof. A suitable display ON-OFF switch 210 is provided for this purpose. Consequently, the monitoring and control circuit as embodied in FIG. 6 permits substantially constant monitoring of all of the planting units by way of their associated series-connected sensor circuits 14, 16, etc., due to the relatively high scanning rate thereof. The display of suitable characters indicating failed planting units encountered during the scan may be accomplished independently of the scan, in "real time", whenever desired by the operator.
As a specific example to which no limitation is intended, in the embodiment illustrated in FIGS. 3A and 3B the following commercially available integrated circuit components may be utilized:
______________________________________Reference No. Commercial No.______________________________________84 404586,88 405592,94 407198 4518104,132 4013120 4024______________________________________
Referring now to FIGS. 7 through 10, additional circuitry may be readily provided for accommodating other sensors associated with the grain drill or seed planting machine. For example, one or more hopper level sensors may be provided for sensing the level of grain in the hopper or hoppers of the planting machine. The circuits of FIGS. 7 through 10 are preferably used in conjunction with a microprocessor-based monitoring circuit, as shown in detail in FIGS. 11A and 11B. The operation of the invention with this microprocessor-based circuit presents certain additional features and advantages which will be discussed presently.
In FIG. 7 a further sensor circuit or transfer cell 210 similar to that illustrated and described above with reference to FIG. 4 is illustrated. This transfer cell 210 receives signals from a hopper level sensor by way of a suitable sensor interface circuit illustrated in FIG. 9. Briefly, the transfer cell 210 of FIG. 7 comprises an enabling input circuit or flip-flop 230 comprising a pair of NAND gates 230a and 230b. A similar, enabling output circuit or flip-flop 232 comprises a pair of NOR gates 232a, 232b.
Hopper level sensor signals provided by one or more circuits such as the circuit of FIG. 9 are input at a terminal 268 to both inputs of a two-input NOR gate 234, this input being further provided with a suitable positive voltage pullup. The output of the NOR gate 234 feeds the junction of a capacitor 236 with one input of a two-input NAND gate 238. The other input of this NAND gate 238 is fed from the output of a two-input NOR gate 240 which receives its input from respective outputs of the two flip-flops 230 and 232. The output of the NAND gate 238 feeds the common data line 18 by way of a suitable resistor 242 and diode 244. In similar fashion to the circuit of FIG. 4, an inverter comprising a two-input NAND gate 246 receives both of its inputs from a remaining output of the flip-flop 232 and feeds a second input of the flip-flop 230 by way of a time delay capacitor 248 and voltage pullup resistor 250.
The enable input line 20 is fed to the remaining input of the flip-flop 230, while an enable output line 20b is fed from the output of the flip-flop 232. Preferably, this transfer cell 210 is interposed in the enable line 20 from the monitoring circuit 22 (see FIG. 1) ahead of the first seed sensor 10 and its associated transfer cell 14. Hence, with reference to FIG. 11, a microprocessor may be arranged to interrogate one or more hopper level sensors prior to interrogating the individual seed sensor transfer cells. A clock line 235 is energized from the microprocessor of FIG. 11 for clocking the remaining input of the flip-flop 232. Similarly, when this microprocessor is utilized, as will be described later, this clock line 235 is utilized to clock the "S" inputs of all of the enable output flip-flops 32 (see FIG. 4) of the sensor transfer cells 14, 16 etc., the data line 18 being used only to receive the data from the memories of each sensor circuit. This modified transfer cell or sensor circuit is illustrated in FIG. 10. The circuit of FIG. 10 is substantially identical in structure and operation to the circuit of FIG. 4, aside from the provision of the clock line 235 separate from the data line 18. Hence, further description of the circuit of FIG. 11 is unnecessary.
Referring briefly to FIG. 9, a hopper level sensor may comprise a light sensitive resistor 250 which is set at a predetermined level in a hopper to produce a detectable change in its output signal when the seed or grain falls below that level. This sensor 250 forms a voltage divider with a resistor 252 and reference voltage +V1, the divided voltage feeding the inverting input of an operational amplifier 254. This operational amplifier receives a reference voltage at its non-inverting input from the junction of a pair of resistors 256, 258 coupled in series between a suitable positive potential ground. A feedback resistor 260 is also provided from the output of the op amp 254 to its non-inverting input. The output of the op amp 254 also feeds a suitable switching transistor 262 which in the illustrated embodiment comprises a grounded-emitter NPN transistor. A suitable current limiting resistor 264 is placed in series between the base electrode of the transistor 262 and the output of the op amp 254. A further suitable current limiting resistor 266 extends from the collector or output terminal of the switching transistor 264 and a terminal 268 which forms the input to the gate 234 of FIG. 7. The reference voltage +V1 is provided by a circuit comprising a capacitor 270, a resistor 272 and a diode 274 as illustrated in FIG. 9, which may be energized from a 12 volt battery, for example, the battery of a tractor which pulls the planting machine.
Referring now briefly to FIG. 8 an alternative form of the termination circuit of FIG. 5 is illustrated. Briefly, this termination circuit includes an input enable flip-flop 276, an output enable flip-flop 278 and an interconnecting inverter in the form of a NAND gate 280. An enable input line 20n and feeds one input of the enable input flip-flop 276 and the clock line 235 feeds the input of the flip-flop 278.
The data line 18 is fed from a grounded emitter NPN switching transistor 282 by way of a suitable series-connected resistor 284. The transistor 282 receives an input at its base electrode through a series resistor 286 from the outputs of a pair of similar two-input NOR gates 288, 290. One input of each of these NOR gates 288, 290 is fed from the same output of the flip-flop 276 which feed one input of the flip-flop 278. The remaining input of both of these NOR gates 288, 290 is fed in common from the remaining output of the flip-flop 278. Hence, a recognizable terminal signal will be given to the data line 18 upon enabling and clocking of the terminal circuit of FIG. 8. This signal indicates to the microprocessor (FIG. 11) that the last seed sensor in the string has been interrogated and read.
Referring now to FIG. 11A and FIG. 11B, a preferred embodiment of a microprocessor-based monitoring and control circuit is illustrated in circuit schematic form. This circuit is preferably used with the sensor circuits of FIGS. 7 through 10, as mentioned above.
A microprocessor 400 preferably comprises a single-chip microcomputer of the type generally designated MK3870/22. This microprocessor 400 includes a plurality of input/output ports, designated by hyphenated numbers indicating first the port number and second the bit number (e.g., 1-0 indicates port 1, bit 0). A suitable crystal element 402 is coupled to oscillator control input ports X1 and X2 of the microprocessor 400 for providing a master frequency signal in conventional fashion.
The bits 1-6 and 1-7 of port 1 receive signals from respective comparators 404, 406 which function similarly to the comparators 140 and 206 described above with reference to FIG. 6, in generating recognizable signal levels to the microprocessor 400 in response to the data conditions on the data line 18. In this regard, the data line 18 is coupled to the non-inverting inputs of both comparators 404, 406 by way of an RC network comprising a resistor 408 and a capacitor 418. A voltage pullup is also provided by a suitable resistor 410. Suitable reference voltages are provided at the inverting inputs of the respective comparators 404, 406 by way of a voltage divider network comprising resistors 412, 414 and 416.
The clock signal on line 235 is provided from the 1-1 terminal of the microprocessor 400 by way of an operational amplifier 420, a switching transistor 422, and a pair of opposite polarity bipolar transistors 421, 423. Similarly, the enable line 20 (E/R line) is fed from bit 1-0 of the microprocessor 400 by way of an operational amplifier 424 and a switching transistor 426. The audible alarm 24 is fed from bit 0-6 of the microprocessor 400 by way of a first switching transistor 428 and a second switching transistor 430. The sounding of the audible alarm 24 is further controlled by a suitable timing or oscillator circuit comprising an operational amplifier 432 and associated components.
A display panel 434 includes three seven-segment characters and a group of message characters designated generally 436. The display panel 434 preferably comprises a liquid crystal display (LCD) and is driven from a suitable display driver integrated circuit 438, which in the illustrated embodiment comprises a liquid crystal display driver of the type generally designated HLCD0438. This display driver circuit 438 receives a clock signal from the bit 0-4 of the microprocessor 400, a load signal from the bit 0-3 and a serial data input line from the bit 0-5.
Bits 0-0, 0-1, and 0-2 of the microprocessor 400 are coupled to a suitable function selection switch (not shown) for selecting the planter function to be displayed by the messages 436 of the display panel 434. The seven-segment characters display the value of the selected function. In this regard, the RPM rotational speed of a fan which provides the pressurized air in a typical "air seeder" type of grain drill may be directly displayed. Other machine functions may be monitored by providing suitable sensors and interfacing these sensors with the microprocessor 400, which may readily be programmed to respond thereto. When none of these additional functions is selected for display, the number of any planting row or seed tube at which a failure to deliver seeds is detected will be displayed in the seven-segment characters of the display panel 434. If the data on line 18 indicates that one or more of the seed supply hoppers is low, in response to the signals from the associated hopper level sensor 250 (see FIG. 9) and transfer cell 210 (see FIG. 7), an appropriate alarm signal including sounding of audible alarm 24 and a message 436 of display panel 434 will be given. The microprocessor recognizes signals on the data line 18 in accordance with a predetermined sequence of scanning thereof.
Ports 4-0, 4-1, 4-2 and 4-3 of the microprocessor receive a four-bit code from a "rate selection" control switch 437 for selecting a number representing an expected or desired number of seeds to be dispensed from each planting unit over a predetermined time. If the actual number of seeds dispensed falls below this selected number an alarm is given and a failure indication is displayed in the display panel 434. It is a feature of the invention that the microprocessor 400 is adapted to receive and store a plurality of the signals generated on the data line 18 from each of the seed sensor transfer cells of FIG. 10. In this regard, a suitable register or equivalent means (not shown) is provided internally in the microprocessor 400 for storing the signals sensed at each transfer cell over some period of time, and hence over a given number of scans of all of the cells.
In the illustrated embodiment, the microprocessor clocks at a 3.007 kHz rate so as to scan 3060 transfer cells in 1.0176 seconds, and preferably 102 transfer cells in sequence repeated 30 times in 1.0176 seconds. The first of these 102 transfer cells scanned is the hopper level cell of FIG. 7, followed by up to 99 seed sensor cells in sequence (FIG. 10) and the termination cell of FIG. 8. The last clock of the 102 count sequence is used to reset all of the transfer cells by way of the E/R line 20. This sequence is repeated six times to form one monitoring cycle. Hence, 99 storage locations are provided for the data signals received from up to 99 seed sensor transfer cells, each therefore corresponding to one of up to 99 rows of seeds simultaneously planted by the planting machine. Moreover, since these signals are produced for 180 scan sequences, each storage location accommodates at least 180 readings for its associated seed sensor.
With reference to FIG. 10, the 1-bit memory in each of the transfer cells provide a responsive pulse width of on the order of 34 milliseconds each time a seed is detected present by the associated piezoelectric sensing element. However, it is known that different percentages of the seeds actually delivered through a seed tube will strike the piezoelectric element causing this response of the memory. For example, in planting soy beans it is to be expected that from substantially 80 to 90 percent of seeds will strike the piezoelectric element. However, in smaller grains such as wheat, it is known that only from substantially 20 to 30 percent of the seeds delivered through a planting tube will strike the piezoelectric sensor.
Accordingly, the number of "active" memory states stored by the microprocessor 400 for 180 scans of a given transfer cell, and its associated seed planting tube or row, will be on the order of 144 to 162 for soy beans and on the order of 36 to 54 for wheat. Accordingly, the rate selection switch 437 permits the operator to set in a signal to the microprocessor 400 which is interpreted thereby as the appropriate number for the grain being planted. For example, moving the selection switch 437 to a given position will signal the microprocessor that an alarm is to be given for any row in which the register accumulates fewer than 144 counts over 180 scans, and hence is useful in monitoring the planting of soy beans. A different setting of the rate selection switch 437 signals the microprocessor to give an alarm for any row in which the register does not accumulate at least 36 counts per 180 scans, thus providing suitable monitoring for the planting of wheat.
This rate selection switch may have up to 31 such settings, being binary-encoded at the four-bit input 4-0, 4-1, 4-2, 4-3 of the microprocessor 400. An operator's manual may suggest one or more appropriate settings for each grain crop to be planted. Preferably, the operator will select one of the suggested settings, but if an excessive number of alarms are given, the operator may modify the setting downwardly to correspond more closely to the seed dispensing operation experienced when all planting units are observed to be operating properly. An alarm will then be given only when this experienced or "expected" seed dispensing operation is not achieved by any planting unit or units.
Bits 5-0, 5-1 and 5-2 of the microprocessor 400 are programmable inputs for setting in a predetermined factor for calibrating the fan rotation speed or RPM. In this regard, it will be remembered that a fan is conventionally utilized to provide pressurized air in conventional grain drills or planting machines of this type. A suitable RPM sensor (not shown) associated with such a fan preferably comprises an inductive pickup positioned so as to produce an output pulse each time a bolt on the rotating fan passes thereby. Hence, a suitable binary code may be set into these inputs 5-0, 5-1 and 5-2 to indicate the number of bolts on a given fan, thereby providing a reference point from which RPM may be calculated in response to the number of pulses received from the inductive pickup.
Referring also to FIG. 11B, the fan RPM sensor feeds an interrupt terminal (INT) of the microprocessor 400 by way of a suitable circuit including an operational amplifier 440, and a pair of back-to-back diodes 442 for setting a predetermined signal swing or peak-to-peak value to be fed through.
Suitable supply voltages are provided by a power supply circuit 449 including a pair of conventional integrated circuit voltage regulator components 450 and 452. In the illustrated embodiment the voltage regulator 450 is of the type generally designated 7805, and the voltage regulator 452 is of the type generally designated 7806. A suitable power-up, power-down control circuit is provided and includes a pair of operational amplifiers 454 and 456 which receive inputs from the power supply circuit 449. These operational amplifiers feed inputs 4-5 and 4-6 of the microprocessor 400. The power supply receives an input from a suitable source such as a 12 volt tractor battery of a tractor which pulls the seed planting machine, by way of an on-off switch 458.
What has been illustrated and described herein is a novel and improved monitoring system for a grain or seed planting machine. This monitoring system comprises: a seed presence sensing device (piezoelectric sensor 10); a one-bit finite duration memory (one-shot circuit 36); a sequence circuit (circuits 30 and 32, preferably as shown in FIG. 10); a sequence controller (monitoring circuit 22, and preferably, the circuit of FIG. 11); a time integrator (a function of microprocessor 400); and an adjustable reference (switch 437 and a function of microprocessor 400).
Seed presence is detected by the piezoelectric sensor element 10 which in turn feeds the presence information to the memory (one-shot circuit 36) which retains the seed strike information for approximately 34 ms.
The sequence circuit 30, 32 in each transfer cell 14 responds to the negative going edge of a parallel clock signal from the microprocessor 14 and an enable signal from the previous cell (from microprocessor 400, in the case of the first transfer cell). If the previous cell has been scanned, the following cell will transfer the state of the memory onto the common (single) data line 18. When the clock line 235 returns high, the sequencer 30, 32 removes the memory from the data line 18 (by disabling the gate 34) and feeds an enable signal to the next transfer cell. Once scanned, a sequence circuit will not output its memory again until it receives a reset command from the microprocessor 14.
The remaining system components are formed by the microprocessor 400. The microprocessor 400 cycles the parallel clock line at a 3.007 kHz rate which allows 3060 cell scans in 1.0176 seconds or 102 cell scans 30 times each in 1.0176 seconds. Of the 102 scan cycles, 99 are active seed monitoring cells; one is used for hopper levels; one for end of line detect; and the last to reset. Since 1.0176/30≈34 ms, the time interval between interrogation of a given sensor memory is established.
In one second each sensor memory has been examined 30 times and the memory state has been added to its respective integrator register plus an RPM (fan speed) input has been scanned and its data has been logged in its summing location. At the end of the 1.076 second cycle the microprocessor 400 takes a short "time out" to update visual and audible (i.e., display) outputs. A second line scan is then restarted after syncing to the master crystal oscillator 402.
This sequence is repeated six times for a total of 180 examinations of each sensor. At this point (6+ seconds) "time out" is again taken to fetch each integrator value and compare it against the operation selected adjustable reference number. If the integrator value falls below the reference, that location is noted as a row fail for output display in the ensuing seconds.
The feature of counting (integrating) the sensor (memory) states over time gives the system the ability to monitor machines seeding different grains at different seed populations. Moreover, this feature accommodates the generally random seed strike nature.
Referring now to FIG. 12, in accordance with one practical and preferred embodiment of the invention, a novel area counter module is also provided for cooperating with the microprocessor 400 of FIG. 11. Advantageously, the circuit of FIG. 12 is arranged to retain, independently of the microprocessor 400, the cumulative count of area or acreage covered a given implement such as a grain drill.
In this regard, a 16-bit memory is provided in the form of a pair of 8-bit shift registers 500, 502 which in the illustrated embodiment comprise 8-stage static shift registers of the type generally designated CD4021. These shift registers are tied together for serial exchange of data with the microprocessor 400 by way of data in (DI) and data out (DO) terminals 504 and 506. Additionally, parallel input lines, designated generally 508 are arranged for carrying a 16-bit code for indicating to the microprocessor or microcomputer 400 a predetermined constant M for use in calculating area covered by the implement, as will be described hereinbelow. In the illustrated embodiment a plurality of switches are provided on the parallel inputs to the shift registers 500-502 for selectively establishing a binary code (by closing selected switches to the positive voltage supply). Other suitable means may be utilized for producing logic levels at the respective parallel inputs to represent a desired binary encoded constant or factor M.
A distance input terminal 510 and implement status input terminal 512 feed respective inputs of a two-input AND gate 514 by way of suitable intervening signal shaping networks. Briefly, the distance input 510 receives pulses from a suitable distance or ground speed sensor (not shown) which may be any of a number of types known in the arts. Essentially, this distance input 510 receives a known number of pulses per given increment of distance traveled by the implement being monitored. The implement status inputs 512 is arranged to receive a signal indicating whether an implement is in a working or "down" condition, during which area covered is to be counted or in a transport or "up" position, in which case distance or area traveled is not to be counted. Hence the implement status input 512 serves to enable or disable the gate 514 in this regard.
The output of the gate 514 feeds a 12-stage divider 516, which in the illustrated embodiment comprises a 12-stage ripple-carry binary counter/divider of the type generally designated CD4040. This divider 516 has sixteen binary output terminals, one of which is chosen as the output. This choice operates to scale the distance pulses, by dividing by a number N as explained below. Hence one pulse is produced at the selected output of the divider 516 for every N pulses received at the input thereof. This scaled output is fed to the microprocessor at a frequency input (fin) 518 by way of a suitable buffer 520. This buffer 520 is fed from the output of a two-input NAND gate 522 which receives one of its inputs from the selected binary output of the divider 516. The other input of the gate 522 is enabled from a suitable logic network or circuit 523 for controlling the sequence of operation in selecting and monitoring the frequency input 518, as will be described later.
The circuit of FIG. 12 also receives suitable control signals from the microcomputer 400 by way of a clock line 524 (not to be confused with the clock line 235 previously discussed) and a parallel/serial (P/S) control line 526, both of which feed corresponding clock and parallel/serial select inputs of the respective shift registers 500, 502 by way of suitable intervening logic. Additionally, a write enable line (We) 528 feeds a suitable write enable signal to the microcomputer 400 for enabling or disabling writing from the microcomputer 400 into the shift registers 500, 502 by way of the data input (DI) line 504. This latter write enable line 528 is fed from a suitable buffer 530 by way of the logic network 523 previously mentioned. This logic network 523 also feeds a reset terminal (R) 532 to the microcomputer 400. Briefly, this logic network 523 is responsive to the on/off switch 458 for disabling the writing of area or acreage data from the microcomputer 400 into the registers 500, 502 when the power to the console is switched off. This prevents loss of the accumulated, stored area data in the registers 500, 502 in the absence of updated or replacement data from the microcomputer 400 due to power shut off to the console.
Advantageously, the memory capability provided by the 16-bit shift register comprising registers 500, 502 is retained with but minimum power drain on the vehicle battery or other power source even during prolonged periods of non-use of the console and/or vehicle when the main power switch 458 is turned off. In this regard, a suitable voltage regulation network designated generally by the reference numeral 536 is coupled to the positive and ground terminals of a vehicle battery for providing a +5 volt supply, in the illustrated embodiment, to the shift registers 500, 502 at all times. This circuit 536 also advantageously coordinates this 5 volt supply with the 5 volt supply regulation provided by the circuits 449 of FIG. 11 when the on/off switch 458 is actuated to its on position.
It will be recognized in this regard that the power requirements of the two shift register circuits 500, 502, which in the illustrated embodiment are CMOS circuits, is on the order of several microwatts, whereas the power requirement for a microcomputer such as the microcomputer 400 of FIG. 11 for similarly retaining its memory after power shutdown is on the order of several milliwatts. Hence, battery drain of the vehicle is held to a negligible level by the provision of the circuit of FIG. 12 for retaining cumulative area or acreage memory. Additionally, the retention of volatile memory (e.g., RAM) in a microcomputer or microprocessor such as the microcomputer 400 requires relatively complex and expensive power-up and power-down control circuits for preventing any changes in the volatile memory components during power-up and power-down cycling. This additional circuitry is eliminated by provision of the relatively simple and inexpensive circuit of FIG. 12.
Advantageously, the circuit of FIG. 12 also may be characterized as a "generic" area counter and memory counter module, readily usable with any system employing a microprocessor or microcomputer which is programmed with suitable subroutines for interacting with the circuit of FIG. 12. In this regard, the presence or absence of the circuit of FIG. 12 may be readily detected by conventional means to respectively enable or disable execution of the associated subroutines for area monitoring and accumulation. Hence, the circuit of FIG. 12 may readily be advantageous provided as a simple "add-on" circuit card to any system whose microprocessor or microcomputer is programmed with suitable subroutines. This circuit of FIG. 12 thus provides monitoring of total acreage or area covered by any sort of farm implement which is provided with suitable distance or ground speed and implement status sensors to feed the inputs 510, 512 thereof. In this regard, as will be seen presently, selection of the constant M, as set in at the parallel inputs of the shift registers 500, 502 and the number N as set by selection of one of the parallel binary outputs of the divider 516 automatically accommodates the circuit of FIG. 12 and the microcomputer 400. These numbers M and N enable accurate monitoring of the area covered by an implement having a given known width and equipped with a distance sensor which provides a known number of pulses per unit of distance traveled.
In operation, the distance input 510 is initially scaled at the divider 516 to define a scale number N such that one pulse is given at its output for each N pulses received at the distance input 510. This number is selected to take into account capacity of the microcomputer 400, which in the illustrated embodiment is capable of scanning the frequency input (fin) 518 substantially once per second. Hence, the maximum frequency rate permissible at this output 518 is substantially 1/2 Hz. Accordingly, a binary output terminal n of the divider 516 is chosen such that:
N=2.sup.n ≦0.0075WX in English units; or
N=2.sup.n ≦0.01WX in Metric units;
where n is the binary output selected of the divider 516, W is the width of the implement whose area coverage is to be monitored, and X is the number of pulses produced by the distance sensor per 0.1 units of area covered at the given width W. The microcomputer 400 is then programmed by initially reading out the parallel data set in on the lines 508 of the shift registers 500, 502 for reconverting each pulse or given number of pulses N into units of area by application of a constant M, where
This constant M will be read into the microcomputer each time power is initiated by actuation of the on/off switch 458. At the same time the microcomputer RAM, which in the illustrated embodiment has a 32-bit configuration, reads in the area or acreage currently accumulated in the register 500, 502 as a starting point for accumulating further acreage or area. The 32-bit memory of the microprocessor 400 is preferably arranged to accumulate area in such a fashion that the sixteen lower order bits accumulate any fractional units of the constant M while the higher order order sixteen bits accumulate units of M. In this regard, the constant M given above is equivalent to 1/10 of a unit of area, whether in acres (English system) or hectares (Metric system). Hence, only increments of at least 1/10 of an unit area will be added to the registers 500, 502, thus further reducing demands on computer time in this regard. The microcomputer 400 will therefore write in new cumulative totals to the registers 500, 502 upon accumulation of M units or some multiple of some M units, as time is permitted for the write procedure in the monitoring process. Accordingly, the accumulated area stored in the shift registers 500, 502 is periodically updated in this fashion.
When the microcomputer 400 is powered-up the onboard RAM reads out the total stored in the registers 500, 502 and increments this total in accordance with the pulses received on the fin terminal 518, periodically updating the data in the outboard memory registers 500, 502. When the power switch 458 is switched off, the most recent updated cumulative area total is therefore retained in the outboard memory registers 500, 502, although some fractional area count (less than 1/10 unit of area) may be lost in the power-off cycle. Advantageously, the CMOS registers 500, 502 and relatively large capacitor 537 provided in the power supply circuit 536 therefor, will function to retain the memory data even in the event of disconnection thereof from the battery for on the order of several minutes, thus adding substantially to the reliability of the memory provided thereby. In this regard, it will be recognized that the circuit arrangement of FIG. 12 may be utilized as an outboard memory for any data which is to be retained and/or periodically updated in similar fashion.
In order to fully describe a specific embodiment of the invention, an exemplary program for the microprocessor 400 of FIG. 11 is reproduced on the following pages. ##SPC1## ##SPC2## ##SPC3## ##SPC4##
What has been illustrated and described herein is a novel system for monitoring the performance of a field planting machine having a plurality of planting units. While specific embodiments have been illustrated and described herein, the invention is not limited thereto. On the contrary, various alternatives, changes and modifications may become apparent to those skilled in the art upon reading the foregoing descriptions. The invention includes such alternatives, changes and modifications insofar as they fall within the spirit and scope of the appended claims.
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|U.S. Classification||221/3, 377/6, 340/520, 702/128, 340/684, 221/8|
|Jun 1, 1982||AS||Assignment|
Owner name: DICKEY-JOHN CORPORATION, AUBURN, ILL. 62615 A CORP
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:KNEPLER, JOHN T.;BACHMAN, WESLEY J.;REEL/FRAME:003995/0405
Effective date: 19820524
|Jun 6, 1988||FPAY||Fee payment|
Year of fee payment: 4
|Jan 9, 1989||AS||Assignment|
Owner name: FLEET CREDIT CORPORATION, A CORP. OF RI, RHODE ISL
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:DICKEY-JOHN CORPORATION, A CORP. OF DE;DICKEY-JOHN INTERNATIONAL, LTD., A CORP. OF CT;DICKEY-JOHN INTERNATIONAL, LTD., A CORP. OF DE;AND OTHERS;REEL/FRAME:005016/0010
Effective date: 19880419
|Mar 29, 1991||AS||Assignment|
Owner name: DICKEY-JOHN CORPORATION
Free format text: RELEASED BY SECURED PARTY;ASSIGNOR:FLEET CREDIT CORPORATION;REEL/FRAME:005650/0235
Effective date: 19910328
|Jun 30, 1992||FPAY||Fee payment|
Year of fee payment: 8
|Feb 16, 1995||AS||Assignment|
Owner name: FIRST BANK NATIONAL ASSOCIATION, MINNESOTA
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Effective date: 19941115
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