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Publication numberUS4496860 A
Publication typeGrant
Application numberUS 06/361,934
Publication dateJan 29, 1985
Filing dateMar 25, 1982
Priority dateMar 27, 1981
Fee statusPaid
Publication number06361934, 361934, US 4496860 A, US 4496860A, US-A-4496860, US4496860 A, US4496860A
InventorsAkio Tokumo
Original AssigneePioneer Electronic Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Voltage-controlled attenuator
US 4496860 A
Abstract
A voltage-controlled attenuator achieves lower distortion and noise through a construction wherein collector currents of a driving differential amplifier are linearized by employing a current mirror configuration. The circuit design lends itself to IC fabrication by lowering current requirements.
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Claims(4)
What is claimed is:
1. A voltage-controlled attenuator comprising:
a pair of differential amplifiers for generating a pair of output signals for attenuation gain control, each of said differential amplifiers comprising a pair of first and second transistors having commonly connected emitters; and a driver differential amplifier comprising a third pair of transistors wherein each transistor in said third pair has its respective collector connected to one of the commonly connected emitters of one of said first and second pairs of transistors in said pair of differential amplifiers for driving said pair of differential amplifiers, first and second emitter followers respectively connected to first and second input terminals of said driver differential amplifier; and first and second control transistors connecting said respective emitter followers to transistors of said driver differential amplifier in a current mirror mode such that the operating current of said first emitter follower and the operating current of a first transistor of said third pair of transistors in said driver differential amplifier and the operating current of said second emitter follower and the operating current a second transistor of said third pair of transistors in said driver differential amplifier are proportional, and
an operational amplifier, said output signals from said pair of differential amplifiers being applied to said operational amplifier for subtraction, an output of said operational amplifier being substantially distortion free.
2. A voltage controlled attenuator as claimed in claim 1, said first input terminal being coupled to a first control transistor of said driver differential amplifier and said second input terminal being coupled to said second control transistor of said driver differential amplifier, said first emitter follower being connected to said second transistor of said driver differential amplifier in a current mirror mode, by said first control transistor and said second emitter follower being connected to said first transistor of said driver differential amplifier in a current mirror mode, by said second control transistor.
3. A voltage-controlled attenuator as claimed in claim 1, said first and second emitter followers comprising PNP transistors, said differential amplifier being connected to said pair of differential amplifiers by way of a pair of intermediate transistors, each interposed between the collectors of one of said first and second transistors of said driver differential amplifier and one of said commonly connected emitters of said pair of differential amplifiers, driven by outputs of said differential amplifier.
4. A voltage-controlled attenuator as claimed in claim 3, further including a pair of diodes, each connected across the base-emitter junction of one of said pair of intermediate transistors, which in combination with said intermediate transistors, comprise current mirror circuits.
Description
BACKGROUND OF THE INVENTION

This invention relates to a voltage-controlled attenuator which is made low in noise and distortion.

A conventional voltage-controlled attenuator is arranged as shown in FIG. 1.

More specifically, an input voltage EIN is converted into a current by a differential amplifier having transistors Q1 and Q2, and the current is used to drive the common emitters of a pair of differential amplifiers which include transistors Q3 and Q4, and Q5 and Q6, respectively. The base biases of the transistors Q3 through Q6 forming the pair of differential amplifiers are controlled by a voltage Vc, so that the collector current of one of the transistors Q3 and Q4 is increased as the collector current of the other is decreased, and so that the collector current of one of the transistors Q5 and Q6 is increased while that of the other is decreased.

That is, the currents in the load resistors R1 and R2 are controlled, and the output voltages are also controlled by the bias voltage.

Let us consider the operation when the transistors Q4 and Q5 are conductive (on), i.e. where the attenuation factor of the attenuator is 0 dB. The distortion and noise characteristics are determined by the transistors Q1 and Q2, the load resistors R1 and R2 are emitter resistors R3 and R4 only. That is, the distortion characteristic is determined by the steady voltage VR applied to the emitter resistors R3 and R4 and the ratio of the VBE characteristics KT/q of the transistors Q1 and Q2. The noise characteristic is governed by the square by the square average value of the terminal noises Vn=√4KTBR of the load resistors R1 and R2 and the emitter resistors R3 and R4.

Accordingly, a level which meets both distortion and noise characteristics cannot be obtained without increasing the current value of the constant current source I. However, increasing the current of the constant current source I is disadvantageous in that the transistors must be increased in size.

SUMMARY OF THE INVENTION

In view of the foregoing, an object of this invention is to provide a voltage-controlled attenuator in which the above-described difficulty is eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a conventional voltage-controlled attenuator;

FIG. 2 is a circuit diagram of a first example of a voltage-controlled attenuator according to the invention; and

FIG. 3 is a circuit diagram of a second example of the voltage-controlled attenuator according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 is a circuit diagram illustrating a first embodiment of the invention.

In FIG. 2, a pair of differential amplifiers comprising transistors Q3 through Q6 are similar to those shown in FIG. 1, and are driven by a differential amplifier comprising transistors Q1, Q2 and Q7 through Q10.

That is, emitter followers comprising transistors Q7 and Q8 are connected to the input terminals of the transistors Q1 and Q2 forming the differential amplifier, respectively. The transistor Q9 is connected so that the operating currents of the transistors Q7 and Q2 are coupled in a current mirror mode, and the transistor Q10 is connected so that the operating currents of the transistors Q1 and Q8 are coupled in a current mirror mode.

On the other hand, the collector outputs of the transistors Q4 and Q5 are applied to an operational amplifier OP1, so that the difference between these collector outputs is provided at the output terminal OUT of the operational amplifier OP1.

In the voltage-controlled attenuator thus organized, the input voltage Ein can be represented by the following expression (1):

Ein =-VBE7 -VBE1 +2(RE Ie)+VBE2 +VBE8 (1)

where RE =r3 =r4, resistances of the emitter resistors R3 and R4 being r3 and r4, respectively; and Ie =Ie1 =Ie2, the emitter currents of the transistors Q1 and Q2 being Ie1 and Ie2, respectively.

When only the AC variation components are taken into consideration, then expression (1) can be rewritten as follows:

ei=-ΔVBE7 -ΔVBE1 +2(RE ie)+ΔVBE2 +ΔVBE8     (2)

where ΔVBE7 =ΔVBE2 and ΔVBE8 =ΔVBE1, because the operating currents of the transistors Q2 and Q7 are coupled in current mirror fashion through the transistor Q9, and the operating currents of the transistors Q1 through Q8 are coupled in current mirror fashion through the transistor Q10.

Therefore, expression (2) can be rewritten as follows:

Ein =2RE ie 

Thus, the VBE characteristics of the transistors are cancelled out, and the collector currents of the differential amplifier comprising the transistors Q1 and Q2, which is adapted to drive the pair of differential amplifiers having the transistors Q3 through Q6 are linearized.

Accordingly, even when the resistances of the emitter resistors R3 and R4 of the transistors Q1 and Q2 and those of the emitter resistors R5 and R6 of the transistors Q9 and Q10 are decreased and the current of the constant current source I is reduced, no distortion is produced, and the noise is low.

Thus, the pair of differential amplifiers comprising the transistors Q3 through Q6 are driven by the collector currents of the transistors Q1 and Q2, which are made distortion-less. Therefore, voltages developed across the load resistors R1 and R2 suffer mainly from secondary distortions.

However, since the outputs of the pair of differential amplifiers are subjected to subtraction in the operational amplifier OP1, the secondary distortions are cancelled out; that is, no distortion is provided at the output of the operational amplifier OP1. Thus, the voltage-controlled attenuator is, as a whole, low in noise and distortion.

FIG. 3 is a circuit diagram illustrating another embodiment of the invention.

In this embodiment, a pair of differential amplifiers, which are made up of transistors Q3 and Q4 and transistors Q5 and Q6, respectively, are driven by transistors Q11 and Q12, respectively. A linearized difference amplifier comprising transistors Q1 ', Q2 ', Q7 ', Q8 ', Q9 ' and Q10 ' constructed similarly to that in the embodiment of FIG. 2, employs PNP transistors. The transistors Q1 ', Q2 ', Q7 ', Q8, Q9 ' and Q10 ' correspond to the transistors Q1, Q2, Q7, Q8, Q9 and Q10 in FIG. 2, respectively. The transistor Q11 is driven by the output of the transistor Q1 ', and the transistor Q12 is driven by the output of the transistor Q2 '.

In the embodiment of FIG. 3, the transistors Q7 ' and Q8 ' form emitter followers connected to the input terminals of the transistors Q1 ' and Q2 ', respectively. The operating currents of the transistors Q2 ' and Q7 ' are coupled in the current mirror mode through the transistor Q9 '. Similarly, the operating currents of the transistors Q1 ' and Q8 ' are coupled in the current mirror mode through the transistor Q10 '. Transistors Q11 and Q12, in combination with diodes D1 and D2, form current mirror circuits, respectively.

The effect of the second embodiment of FIG. 3 is similar to that of the first embodiment of FIG. 2, and therefore a detailed description thereof will be omitted.

However, it should be noted that the power utilization rate is improved, because the transistors Q1 ', Q2 ', Q7 ', Q8 ', Q9 ' and Q10 ' forming the differential amplifier are PNP transistors.

As is apparent from the above description, the voltage-controlled attenuator of the invention has less distortion and noise, and can be operated with a small current. As the attenuator can be operated with a small current, it can easily be provided in the form of an integrated circuit. Furthermore, the voltage-controlled attenuator can be operated with a low voltage, because the voltage loss due to the emitter resistors is small.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3241078 *Jun 18, 1963Mar 15, 1966Honeywell IncDual output synchronous detector utilizing transistorized differential amplifiers
US3681614 *Feb 4, 1971Aug 1, 1972Siemens AgEcl gate switching network
US3689752 *Apr 13, 1970Sep 5, 1972Tektronix IncFour-quadrant multiplier circuit
US3875522 *Apr 13, 1973Apr 1, 1975Signetics CorpIntegrated direct-coupled electronic attenuator
US4019118 *Mar 29, 1976Apr 19, 1977Rca CorporationThird harmonic signal generator
US4197505 *Feb 7, 1978Apr 8, 1980Hitachi, Ltd.Limiter circuit
US4327333 *Mar 17, 1980Apr 27, 1982National Semiconductor CorporationAGC Current source
US4331929 *Mar 26, 1980May 25, 1982Nippon Gakki Seizo Kabushiki KaishaGain-controlled amplifier
US4396891 *Feb 20, 1980Aug 2, 1983Telefonaktiebolaget L M EricssonGain control circuit
JPS5563112A * Title not available
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6054897 *Oct 14, 1998Apr 25, 2000Nec CorporationDifferential amplifier constituted of bipolar transistors
US6320425 *Jul 12, 2000Nov 20, 2001Motorola, Inc.Dual FET differential voltage controlled attenuator
US8198932 *May 6, 2010Jun 12, 2012Texas Instruments IncorporatedVoltage generating circuit for an attenuator
US20110273217 *Nov 10, 2011Texas Instruments IncorporatedVoltage generating circuit for an attenuator
EP2683080A1 *Jul 6, 2012Jan 8, 2014Nxp B.V.Operational transconductance amplifier
WO2002005430A1 *Jul 10, 2001Jan 17, 2002Motorola IncDual fet differential voltage controlled attenuator
Classifications
U.S. Classification327/308, 327/310
International ClassificationH03G3/10, G05F3/16, H03G1/00
Cooperative ClassificationH03G1/0023
European ClassificationH03G1/00B4D
Legal Events
DateCodeEventDescription
Nov 19, 1984ASAssignment
Owner name: PIONEER ELECTRONIC CORPORATION, NO. 4-1, MEGURO 1-
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:TOKUMO, AKIO;REEL/FRAME:004328/0123
Effective date: 19820310
Jun 29, 1988FPAYFee payment
Year of fee payment: 4
Jun 17, 1992FPAYFee payment
Year of fee payment: 8
Jul 29, 1996FPAYFee payment
Year of fee payment: 12