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Publication numberUS4506299 A
Publication typeGrant
Application numberUS 06/368,005
Publication dateMar 19, 1985
Filing dateApr 13, 1982
Priority dateApr 16, 1981
Fee statusPaid
Also published asDE3273406D1, EP0064890A1, EP0064890B1
Publication number06368005, 368005, US 4506299 A, US 4506299A, US-A-4506299, US4506299 A, US4506299A
InventorsJean-Luc Berger, Patrick Descure
Original AssigneeThomson-Csf
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Device for scanning an image in successive lines, utilizing the electrical charge transfer, incorporating a line memory and a television camera incorporating such a device
US 4506299 A
Abstract
A device for the electric scanning of luminous images. It includes a matrix of N lines and M columns of photosensitive points. A system incorporating a line memory of M points receives in parallel the electric charges supplied by the M points of the same line parasitic charge are removed by diodes. The system insures the injection of the same predetermined quantity of charges between each of the photosensitive points and the output of the device. An output shift register receives in parallel the charges supplied by the line memory and supplies in series a picture scanning electric signal. This device is particularly intended for use in a television camera.
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Claims(19)
What is claimed is:
1. An area image sensory device comprising:
(a) a semiconductor substrate,
(b) a plurality of elementary photosensitive areas formed on said substrate and separated from one another and formed in a matrix of N lines and M columns, and in said areas electrical charge signals are produced proportional to received illumination of an image;
(c) a charge transfer device formed on said substrate having line memory means with M areas for receiving in parallel the electrical charge signals from M photosensitive areas which are all in a same line and periodically supplying said charge signals to an output; said line memory means having
(i) first grid means (G1) adapted to be connected to a constant potential (V1) and located between the matrix and said areas of the memory for insuring decoupling between said areas of the matrix and the charge transfer device,
(ii) at least one charge storage grid adapted to be connected to a periodic amplitude alternating potential for maintaining the electrical charge signals,
(iii) supplementary grid means adjacent to said storage grid for receiving a periodic amplitude alternating potential,
(iv) parasitic charge removal means having a plurality of removal diodes for draining parasitic charges from each of said columns, and
(v) control grid means for receiving a periodic amplitude alternating potential and for controlling access to said removal diodes, a training charge (Qo) being maintained beneath said storage grid during said parasitic charge drawing and during receiving said electrical charge signals only by a potential barrier beneath said supplementary grid means being caused by said periodic potential received by said grid means reaching a predetermined amplitude; and
(d) analog shift register means for receiving in parallel said charge signals supplied by said line memory and for supplying in series an output picture scanning signal.
2. A device according to claim 1 wherein the line memory means further comprises a further storage grid located between said first grid means and said one charge storage grid and separated from said one charge storage grid by a supplementary grid, said two storage grids means storing the electrical charge signal.
3. A device according to claim 1 wherein the line memory means further comprises second grid means located between the storage grid and said first grid means for fixing a potential at column connections between said row memory and said matrix and insuring charge transfer from the matrix to the line memory means.
4. A device according to claim 3 wherein said second grid means is adapted to be connected to a periodic amplitude alternating potential for authorizing a charge transfer of electrical charge signals from said M photosensitive areas to said line memory.
5. A device according to claim 3 wherein said second grid means (G2) is adapted to be raised to a rising potential for transferring electrical charge signals (QS) coming from an overlighting (QB) from said M photosensitive areas and the column connections to the line memory means, a charge quantity (QO) being added to the electrical charge signals when there is a transfer from the column connections to the line memory means.
6. A device according to claim 2 wherein the line memory also comprises second grid means located between the storage grid and said first grid means for fixing a potential at column connections between said matrix and said line memory and insuring charge transfer from the matrix to the line memory means.
7. A device according to claim 6 wherein the second grid means is adapted to be raised to a periodic amplitude alternating potential for authorizing a charge transfer from said column connection to said line memory means.
8. A device according to claim 6 wherein said second grid means is adapted to be raised to a rising potential for transferring signal charges (QS) coming from an overlighting (QB) from said column connections to said line memory; a charge quantity (QO) being added to the signal charges and to the overlighting charges during transfer from said column connections to said line memory means.
9. A device according to claim 1 wherein said storage grid has notches in which are placed said charge removal diodes.
10. A device according to claim 9 wherein said notches are positioned with each charge removal diode being common to two channels.
11. A device according to claim 9 wherein said storage grid has one notch per channel.
12. A device according to claim 1 further comprising connecting means for supplying in parallel said electrical charge signals produced in M elementary photosensitive areas of the same line of the matrix, successively for N lines; said connecting means having a plurality of reading diodes and reception diodes, said reading diodes being arranged in columns between said elementary selective areas and M reception diodes located at an input to said charge transfer device from said matrix; each of said reading diodes being electrically coupled to a corresponding reception diode.
13. A device according to claim 12 wherein each of said elementary sensitive areas of said matrix comprises a MOS capacitance having a first charge election zone including a grid, common to capacitances of a same line, and a second charge election zone electrically coupled to said capacitances, and means for forming a screen for the electrical charge signals positioned between each of said elementary sensitive areas and said connecting means, said screen means having a plurality of grids adapted to be raised to a constant potential and arranged in columns between said reading diode and said photosensitive points.
14. A device according to claim 1 wherein said periodic amplitude alternating potentials are such that the injection of the previously defined charge quantity is brought about beneath the storage grid by the charge transfer removal diode.
15. A device according to claim 14 wherein the periodic potentials are such that charges are injected beneath the storage grid by the charge removal diode, the quantity of charges beneath the storage grid being brought to a previously defined charge quantity by means of a supplementary grid controlling the access to the shift register, the residual charge quantity being eliminated on the charge removal diode after transit in the shift register.
16. A device according to claim 2 wherein the electrical charge signal is maintained beneath the storage grid at all times except during a transfer of the electrical charge signal to the line memory.
17. A device according to claim 12 further comprising a screen which is opaque to received illumination and which screen covers those portions of the device having the diodes.
18. A device according to claim 1 wherein an insulating layer covers semiconductor substrate.
19. A device according to claim 18 wherein said insulating layer comprises an overdoping from the semiconductor substrate.
Description
BACKGROUND OF THE INVENTION

The invention relates to the electrical scanning of luminous images in successive lines forming frames, using a charge transfer device incorporating a line memory.

Various solid state devices scan an image and supply a television camera with a video electrical signal. They differ in the way in which the photosensitive zone is formed and in the system for reading and removing the charges produced by the image.

Charge transfer devices perform these, as described, for example, by SEQUIN and TOMPSETT, in "Charge Transfer Devices", pp. 152 to 169. In "frame transfer" or "interline structure" organisations the light radiation is received on charge transfer registers. The charge transfer then takes place over large areas, which is a disadvantage, since it is difficult to obtain high efficiency levels for such large areas. CID's (charge injection devices), do not have these disadvantages, but generally require reinjection of the charges into the semiconductor substrate, resulting in noise and difficulties in connecting with the capacitance values during and after reading.

There is also the question of compatibility between the time necessary for light integration and for charge transfer when the latter solution is adopted e.g. with the sweep time of the television screen. A 625 line standard, these times are generally about 52 μs for the display time of a line and 12 μs for the line return time.

In order to meet these different requirements, the Applicant Company has proposed a so-called "line transfer" structure, described in U.S. Pat. No. 4,430,672. This structure has a matrix of N lines×M photosensitive zones or points onto which an image to be scanned is projected and converted into electric charges called signal charges; a memory of M points, called the line memory, for successively receiving the signal charges stored by each line; a device for removing the parasitic charges associated with the line memory; and a CCD-type (charge coupled device) shift register receiving in parallel the content of the line memory and supplying in series the image scanning electric signal.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to a picture scanning device of the line transfer type, as described above, in which improvements have been made to insure the storage of successive lines and the removal of parasitic charges, in order to improve the processing of small signals and reduce noise.

The device according to the invention has many of elementary photosensitive zones, called points, formed on the same semiconductor substrate in accordance with N lines and M columns, which are isolated from one another and form a matrix in which are created electrical charges, called signal charges, as a function of the illumination received; a charge transfer system with M columns incorporating a memory of M points, called the line memory, formed in the same semiconductor substrate and receiving in parallel the signal charges supplied by the M points of the same line; the line memory including a first grid (G1), placed on the path of the charges and receiving a constant potential (V1), which ensures the decoupling of this grid from the upstream part of the device; a parasitic charge removal device incorporating a many diodes and draining the parasitic charges from each of the columns, which insures the injection of the same predefined quantity of charges into each of the points of the line memory; and an analog shift register receiving in parallel the charges supplied by the line memory and supplying in series a picture scanning electric signal.

The invention also relates to a television camera incorporating such a picture scanning device.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in greater detail hereinafter relative to non-limitative embodiments and the attached drawings, which show:

FIG. 1 is a block diagram of the general organisation of a line transfer structure.

FIG. 2 a plan view of a first embodiment of the device according to the invention.

FIGS. 3 (a to h) a sectional view of the device of FIG. 2, illustrating the potentials at different times.

FIGS. 4 (a to f) signals which can be applied to the device of FIG. 2.

FIG. 5 a plan view of a second embodiment of the device according to the invention.

FIGS. 6 (a to h) a sectional view of the device of FIG. 5 illustrating the potentials at different times.

FIGS. 7 (a to f) signals which can be applied to the device of FIG. 5.

FIG. 8 a plan view of a third embodiment of the device according to the invention.

FIGS. 9 (a to i) a sectional view of the device of FIG. 8 illustrating the potentials at different times.

FIGS. 10 (a to d) signals which can be applied to the device of FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the various drawings, the same references designate the same elements.

FIG. 1 shows the general organisation of a line transfer structure, as described in U.S. Pat. No. 4,430,672. This structure includes a photosensitive zone 1, a line memory 2 and an analog output shift register 3.

The photosensitive zone 1 receives the luminous image to be scanned and converts it into electrical charges, called signal charges. The term "luminous image", relates not only to the detection of visible wavelengths, but also the surrounding wavelengths, particularly in the infrared. The photosensitive zone has many elementary zones 15, which are also called points, arranged in N lines, designated L1, L2 . . . LN and M columns, designated C1, C2 . . . CM and forming a matrix. The photosensitive points of the same line are interconnected and connected to a control device 14, which enables successive addressing of the lines. This device has e.g. a MOS-type shift register. The photosensitive points 15 of the same column are connected to the same connection, subsequently called the column connection towards line memory 2.

Thus, in parallel, line memory 2 receives the signal charges produced at each of the photosensitive points 15 of the same line and then transfers them in parallel to register 3. A device for restoring the level of the column connections (RAN connection in the drawing) and a device for eliminating parasitic charges (not shown in FIG. 1) are also associated with line memory 2.

Register 3 is an analog shift register supplying the information received in parallel in the series mode. This information constitutes the optical image scanning video signal received in photosensitive zone 1. The register is preferably of the charge transfer or CCD type.

The coordination of the different picture integration operations in photosensitive zone 1, the transfer of lines into line memory 2 and then the transfer of signals into register 3 for the different lines are effected in the following manner.

The integration of the image is permanently carried out over the entire photosensitive matrix 1, except for the line addressed by register 14. During the line return time, the content of line memory 2 is transferred into shift register 3, and the input of the line memory is then closed. During the following line time, the content of register 3 is removed in series and the connection between line memory 2 and register 3 is interrupted. During this time, in a first phase there is a level restoring of the reader of points 15 (RAN connection), connected to line memory 2; and in a second phase one of the lines L of zone 1 is transferred to line memory 2, with the selection (or addressing) of a line being insured by register 14.

The following stage corresponds to the line return time during which the content of line memory 2 is discharged into register 3, the latter having been entirely scanned during the preceding stage.

According to another embodiment, the selection of a line, its transfer into the line memory and then into the shift register takes place entirely during the line return time, the line time being reserved for the level restoring of the reader, which improves as it becomes longer, and for the series removal from the shift register.

FIG. 2 shows a plane view of a first embodiment of the device according to the invention. The connections coming from the M column C of the photosensitive matrix (Ci-1, Ci, Ci+1), each lead to a receiving diode D2, of the signal charges Qsi coming from the matrix. It is produced, for example, by doping a semiconductor substrate, which is advantageously the same as that on which the photosensitive matrix 1 is formed. Thus, the device has M charge transfer columns, delimited by insulating barriers 42, corresponding respectively to the M column connections of the photosensitive matrix.

The diodes D are aligned and are adjacent on the underside to electrode or grid G1 in strip form, which forms a screen for the charges between diodes D2 and the remainder of the device shown in FIG. 2, which prevents parasitic charges from being transmitted on column connection C. In charge transfer devices it is particularly important to provide protection against parasitic charges, whose amplitude can vary from one point to another of the circuit as a function of the geometrical variations of the elements, and which limit the dynamics of the signal. To this end, grid G1 is connected to a constant potential V1.

Following the screen grid G1, there is a grid G2 in the form of a strip parallel to G1 and raised to a second potential V2, this has the function of fixing the potential of the column connections.

There is then a grid G4, whose function is to store the charges, and is in strip form having e.g. rectangular notches 24 between two columns and every other column. In at least part of each of the notches 24, there is a diode D5 having the function of removing the parasitic charges. The diodes D5 are connected to a periodic potential VD5.

It may be seen on FIG. 3 that grid G2 is surrounded by two coplanar grids G1 and G4. So the width of grid G2 is defined in a single photogravure operation by the distance between grids G1 and G4. A better homogeneity is thus obtained on the width of grid G2 which can greatly be reduced.

The parasitics due to a variable penetration of diodes D2 under the grid G2 for the different photosensitive points are eliminated. This variable penetration produces variable transfer times for the charge signal of each diode D2 towards the memory; moreover, it increases the rapidity of the charge signal transfer from D1 and D2 to the memory, because of the small width of G2.

The device also has a grid G5 in the form of a strip covering storage grid G4 with an insulating layer level with notches 24, so as to be adjacent to above diodes D5. Grid G5 receives a periodic potential V5 and makes it possible to control the access of the charges to diodes D5.

Parallel to grid G5 and slightly covering the lower part of diodes D5 there is a grid G7 to which is applied a periodic potential V7 making it possible to control the access to shift register 3.

The insulating barriers 42 are interrupted level with the notches 24 or are terminated, if there is no notch, by an extension, e.g. in the form of a triangle 43. Diodes D5 are surrounded by a U-shaped insulating barrier 44 in such a way that diode D5 remains accessible to charges coming from the diodes D2 of each of the columns. In this way, two channels per column are defined: a first channel CL1 limited by an insulating barrier 42, its extension 43 and a U-shaped branch 44 on the outside; and a second channel CL2 limited by the inside of the same U-shaped branch 44 and the second insulating barrier 42 limiting the column in question.

Register 3 is a C.C.D. register with two phases φ1 and φ2. It has two series of storage electrodes 31, 32 and two series of transfer electrodes 33, 34, all having a substantially rectangular shape and positioned perpendicular to grids G1 to G7. Grids 31 are connected to the periodic potential φ1 and grids 32 to the periodic potential φ2. Grids 33 and 34 are respectively placed between the grid pairs 32, 31 and 31, 32 in the charge transfer direction on an extra thickness of insulant and are respectively connected to potentials φ1 and φ2. Moreover, the electrodes of register 3 are positioned in such a way that electrodes 31 originate on insulating barriers 43 or 44, electrodes 32 being located in the extension of channel CL1. The registers 3 is bounded at the bottom by a horizontal insulating barrier 44, in the same way as the device is bounded at the top, also by an horizontal insulating barrier 41.

In this embodiment, as in the following embodiments, the various insulating barriers described can be constructed in a known manner, e.g. by overdoping a substrate having the same type of conductivity as the latter, or a localized extra-thickness of the insulating layer (generally oxide) covering the substrate. The latter solution is possibly accompanied by an overdoping of the substrate formed beneath the extra-thick insulation. The various electrodes can also be formed in known manner using e.g. metal or polycrystalline silicon. Finally, to prevent the formation of interference charges, each diode and part of the adjacent grids is covered with a layer which is opaque to light beams, such as an aluminium layer.

FIG. 3a is a sectional view of the device of FIG. 2 and diagrams 3b to 3h illustrate the surface potential in the semiconductor substrate at different times, the surface potential being represented on these and the following diagrams as increasing in the downward direction. To facilitate the understanding of the operation of the device, the diagram of FIG. 3a is a section made at different locations.

To the left of an axis XX is shown a photosensitive point of matrix 1. For example, it is constituted by a grid GL formed by an electrode with a photodetecting MOS capacitance raised to a periodic potential VGL and which slightly overlaps the following grid GE. This is a screen for the charges, separating the actual photosensitive zone from the column connection and is raised to a constant potential VGE. The screen grid GE is followed by reading diode DL formed in the substrate, which constitutes the starting point for the column connection ci. In a variant not shown, the photosensitive point has a second image detection zone, whose frequency sensitivity is complementary to the MOS capacitance realised e.g. by a photodiode.

To the right of axis XX is shown a section in the device of FIG. 2 along a line AA passing through diode D2, grid G1, grid G4 and the second channel CL2. Grid G4 is followed by grid G5, which also slightly overlaps it, G5 is followed by diode D5. It can be seen that grid G2 slightly overlaps the surrounding grids G1 and G4. It is also possible to see the column connections ci connecting diodes DL and D2.

Following diode D5, it is possible to see a section in the device of FIG. 2 along a line BB along the first channel CL1 and separated in FIG. 3a from what precedes it by an axis YY. The section of the first channel starts level with grid G4 and continues up to an electrode 32 of register 3, G4 and 32 being separated by grid G7, which slightly overlaps them. It should be noted that, both in this and the following embodiments, the operation of the device is compatible with a "volume" charge transfer into output register 3. As is known, the charge transfer in the volume of the semiconductor substrate is faster than the surface transfer and its efficiency is better. Volume transfer differs from surface transfer mainly through the higher potentials applied and a doping of that part of the semiconductor substrate where there is a transfer having a conductivity type which is opposite to that of the remainder of the substrate.

The drawings show a volume transfer operation and consequently a "hatched" doped area, designated T.V., extending beneath the electrodes of register 3 up to half of grid G7.

These different elements are preferably formed on the same semiconductor substrate 21, covered with a insulating layer which is not shown. The various electrodes are separated, in the case where they overlap, by an insulating layer, which, for reasons of clarity, also is not shown.

The various diagrams (a to e) of FIG. 4 show the evolution in time of control signals applied to the device of FIG. 3.

FIG. 4a represents the potential VGL, which is at a constant high level (VH), except during a time interval T4 to T7 corresponding to the time for the transfer of the charges accumulated in a considered photosensitive point to the line memory and then to register 3 of FIG. 2 and which essentially corresponds to the line return time.

FIG. 4d represents potential V4, which is at a constant high level (VH), except between times T3 and T5 surrounding time T4.

FIG. 4c represents the potential V5, which is at a high level (VH) up to time T0, when it passes to an intermediate level (VI) and remains there up to a time T2, T0 and T2 being before time T3. As from time T2, V5 remains at a low level VB up to a time T8, which is after time T7, when it again rises to the high level VH.

FIG. 4d represents potential VD5, which is at a constant high level (VH) , except between time T0 and a time T1 between T0 and T2 during which it is at a low level (VB).

FIG. 4e represents potential V7, which is at a constant low level, except between time T6, which precedes time T7, and T7, during which it is at a high level (VH).

In FIG. 3b, at a time to between time T0 and T1, diode D5 is at low level permitting the injection of charges beneath grid G4. This injection is limited by a constant potential V2 applied to grid G2, which implies that the low level of VD5 exceeds potential V2. Thus, it would appear that grid G2 fixes the potential level of the column connections ci. Moreover, to the left of line XX, a signal charge quantity Qsi is present beneath grid GL (hatched area).

The diagram of FIG. 3c shows the potentials at a time t1 between T1 and T2. At this time, potential VD5 is at high level and therefore a charge quantity Q0 is isolated beneath grid G4 (hatched area) by potentials V2 and V5 respectively applied to grids G2 and G5. This charge quantity Q0 is dependent on the potential V1, which is then applied beneath grid G5, potential V2 being assumed lower than VI.

At a time t2 between T3 and T4, voltages V4 and V5 are returned to low level, which has the effect of transferring the charge quantity Q0 to diodes D2 and, via connections ci, to diodes DL. This is represented by an arrow 51 on the part of diagram 3d between lines XX and YY.

At a subsequent time t3, between T4 and T5, the potential applied to grid GL of the MOS capacitance of the photosensitive zone is brought to a low level, which has the effect of transferring charge quantity Qsi to diodes DL (arrow 52 in the left-hand part of FIG. 3d).

Diagram 3e represents the situation at a time t4, between times T5 and T6. During this time, the potential applied to grid G4 is raised to a high level, which makes it possible to transfer (arrow 53) charges Q0 +Qsi beneath grid G4 in two channels, which is illustrated to the right and left of axis YY.

Diagram 3f represents the situation at a time t5 between T6 and T7 during which the potentials of channel CL2 are unchanged, while the potential of grid G7 placed on channel CL1 rises enabling the transfer (arrow 54) of the charges Q0 +Qsi present beneath grid G4 to shift register 3, materialised by one of its electrodes 32. Thus, the known charge quantity Q0 is effectively transferred into register 3 at the same time as signal charge Qsi.

Generally, it is possible to avoid the transfer of the charge Q0 into register 3, in which case only signal charge Qsi is transferred. This makes it possible to eliminate the so-called spatial noise on Q0 from one column to the next, the noise being due to variations in the changes caused by variations in the oxide thickness covering the substrate, variations in the threshold voltages, etc. This can be brought about by raising grid G7 to an intermediate potential V1, represented in diagram 4f and whose amplitude is between VB and VH during times T6 to T7. The value VI of this intermediate potential is advantageously equal to the intermediate potential applied to grid G5 between times T0 and T2. In this way, an operation described by diagram 3g is obtained, where it is possible to see that the potential applied to grid G7 is such that only the signal charge Qsi (arrow 55) can be transferred from grid G4 to electrode 32 above grid G7, charge Q0 remaining beneath grid G4. It should be noted that in this variant, the phase corresponding to diagram 3b can be eliminated. This stage is an injection stage of Q0 into the device, which is no longer necessary because this charge is no longer eliminated.

It is essential that the charge signal transfer Qsi from diodes D2 under grid G2 then under grid G4 includes the addition of a charge quantity Qo, the capacity of the diodes D2 being quite important. But the transfer of the charge signal Qsi to the reading register doesn't necessitate the addition of the charge quantity QO, the capacity of the grid G4 being small, of the same dimension as the capacity of the register.

At a time t6, following time T8 and at a random point during the line time, the potential applied to grid G5 being raised to the high level VH, there is an elimination of any parasitic charge (QB) from a column connection, by channel CL2 to diode D5. These parasitic charges result e.g. from overilluminated points of the photosensitive matrix.

On referring to the variant described by diagrams 4f and 3g, it is necessary that at time t6, the potential applied to grid G5 is equal to the intermediate level V1 and not to VH in order to ensure that only charge Q0 is beneath grid G4 and to eliminate possible parasitic charges by D5.

In this latter variant, the residual spatial noise can only be due to variations of the threshold, doping or insulation thickness between grids G7 and G5, which is minimal in practice, bearing in mind the geometrical proximity of these grids.

Thus, this structure permits the injection of a predetermined quantity of Q0, first beneath the storage grid G4 and then onto diodes DL and D2 establishing the connection between photosensitive matrix and the line memory, in order to improve the transfer of signal charges Qsi. This quantity of charges Q0 is consequently injected by using the structure of the line memory and the parasitic charge elimination device, so that no auxiliary device is required.

Moreover, in this embodiment, each parasitic charge removal diode D5 is common to both columns making it possible either to increase the storage capacity of the line memory (more extensive grid G4) or to permit a smaller horizontal spacing and consequently a reduced overall size of the device.

FIG. 5 is a plan view of a second embodiment of the invention, where the generation of the charge quantity Q0 is completely free from spatial noise.

In FIG. 5, it is possible to see diodes D2, grid G1, grid G2 and G4, which in this case has a notch 25 level with each of the columns and, as before, each of these notches contains a diode D5. Grids G5 and G7 are arranged parallel to the other grids on either side of diodes D5. Perpendicular to these, it is possible to see the electrodes 31 to 34 of register 3.

Once again, there are vertical insulating barriers 42 between the columns which extend up to electrodes 34 of register 3. Moreover, each of the columns is vertically subdivided by an insulating barrier 45, defining to its left a first channel CL1 extending from grid G4 to an electrode 32, and to its right a second channel CL2 containing diode D5, which then extends between barriers 45 and 42, and finally a third channel CL3 extending from electrode 31 of register 3 to diode D5, i.e. opposite to channel CL2.

To the left of axis ZZ, FIG. 6a shows a section along a closed line CC formed as from diode D5 around the insulating barrier 45 of FIG. 5; to the right of axis ZZ there is a section along a line DD from grid G4 to diode D2, these two sections being joined to make it easier to explain the operation of the device of FIG. 5.

In succession starting from the left, FIG. 6 shows channel CL2 represented by diode D5, grid G5 slightly overlapping the following grid G4, the latter being common to channel CL2 and CL1, then channel CL1 represented by grid 32 separated from grid G4 by grid G7, which slightly overlaps both of them. Grid 31 is separated from grid 32 by grid 33, which slightly overlaps them and which forms the separation between channels CL1 and CL3, then channel CL3 constituted by grid G7 and diode D5. To the right of line ZZ are successively provided grid G4, grid G1 separated from G4 by grid G2 which slightly overlaps them, followed by diode D2, which receives column connections ci.

As before, there is a doping zone extending from grid G7 to electrodes 31, 32 and 33 of register 3 corresponding to the volume transfer type of operation of the register.

The various diagrams (a to f) of FIG. 7 show the evolution in time of the various control signals applied to the device of FIG. 5. These control signals are periodic potentials, whose amplitude varies between a low level VB for all the diagrams and a high level VH for all the diagrams, but these different potentials are not necessarily equal.

Diagram 7a represents potential V5 which is at a high level, except from a time T2 and up to a time T8, the time between T2 and T8 being essentially that of the line return.

Diagram 7b represents potential VD5 which is at a high level, except between times T1 and T3 surrounding time T2, when it is at a low level.

Diagram 7c represents potential V7 which is at a low level up to a time T4 after time T3 at which it passes to a high level, up to a subsequent time T5 when it again passes to a low level, up to a subsequent time T6 when it again passes to a high level, up to T8 when it again passes to a low level.

Diagram 7d represents potential φ2, which is a square wave signal of cycle or period T up to a time T0 preceding time T1 at which it passes to a high level up to time T5. It then passes to a low level, which it maintains up to a time T6, when it passes to a high level up to a time T8, and then it again becomes a square wave signal of the same period as before.

Diagram 7e shows potential φ1, which is complementary to potential φ2.

Diagram 7f represents potential V4 which is at a high level up to time T5, at which it passes to a low level up to time T7 between T6 and T8, when it again passes to a high level.

FIG. 6b shows the surface potential in the semiconductor level with FIG. 6a at a time t0 between T1 and T2. For reasons of clarity in this and the following diagrams, each of them shows the surface of the semiconductor substrate 22. At this time t0, potential VD5 applied to diode D5 is at a low level, but potential V5 applied to grid G5 is at a high level. As a result, it is possible for the charges to invade the area located beneath grid G4, but this invasion (hatched area) is limited by grid G7 raised to potential V7, which is at low level.

FIG. 6c shows the surface potential at a time t1 between T2 and T3. The only change from the preceding drawing is the passage of potential V5 to low level, which isolates a charge quantity Q'0 beneath grid G4.

Diagram 6d represents the surface potential at a time t2 between times T4 and T5. The difference from the previous diagram is that potential V7 applied to grid G7 passes to a high level, which has the effect of subdividing the charge quantity Q'0 beneath electrode G4 into a quantity Q0 remaining beneath this grid as a function of the potential level VH of V7, and defined by the surface potential beneath G7 out of the doped zone T.V., and a residual charge quantity Qr, which is transferred beneath grid 32 to which is applied potential φ2, which at this instant is at high level.

Diagram 6e shows the surface potential at time t3 between times T5 and T6. During this period, potential φ2 is brought to low level, which has the effect of transferring charge Qr beneath electrode 31, potential φ1 then being at high level. Moreover, as the potential V4 of grid G4 is at low level, the charge quantity Q0 is transferred to diode D2 and to column connections ci, which is shown to the right of axis ZZ, reference again being made to the fact that potentials V1 and V2 are constant and higher than the low level of V4. The potential V7 applied to grid G7 is at a low level during this time, so that access to register 3 is impossible.

Moreover, at time t3 the presence of charges Qsi are shown on the column connection ci. The transfer of Qsi from a photosensitive point of column ci takes place in the manner described relative to FIG. 3d. This transfer can take place at any time before t5 (FIG. 6g) but it is preferable for Q0 to be transferred before or at the same time as Qsi on column connection ci.

Diagram 6f represents the surface potential at a time t4 between times T6 and T7. During this period, the passage of potential V7 to a high level makes it possible to remove the charges Qr, previously beneath electrode 31, to diode D5 via channel 3. During this same period, φ2 returns to a high level and φ1 to low level.

Diagram 6g represents the surface potential at a time t5 between T7 and T8. During this period, the potential applied to grid G4 returns to high level, so that the charge quantity Q0 +Qsi present on connection ci (right-hand part of the drawing) is transferred beneath grid G4 and then partly beneath electrode 32, while charge quantity Q0 is held back by the potential barrier beneath grid G7 in the same way as at time t2. In this way, only Qsi is transferred beneath electrode 32 of output register 3.

Diagram 6h represents the surface potential at a time t6 following time T8, potentials φ1 and φ2 then being respectively at high level and at low level. During this time, potential V4 applied to grid G4 is at high level, which makes it possible to eliminate all the parasitic charges Qp present on column connection ci, the charges being transferred over grid G2 to grid G4 and from grid G4 to the parasitic charge elimination diode D5, grid G5 then being raised to a high level potential V5. Throughout this period, charge Qsi is transferred beneath the following electrode 31 of output register 3.

This second embodiment described in FIGS. 5 and 7 consequently permits the generation of charge Q0 at the line memory in a completely spatial noise-free manner, because it is determined by the potential applied to grid G7 and then stopped by the same grid during the transfer of the signal charges Qsi to output register 3. The residual charges Qr or parasitic charges Qp are eliminated before any scan by diode D5 by means of channel CL2 or channel CL3 and in this case via register 3.

FIG. 8 shows a third embodiment of the device according to the invention, which also makes it possible to eliminate the spatial noise in the generation of charge Q0 by means of a two-stage line memory structure. Here the two functions previously fulfilled by storage grid G4 are realised by two separate grids.

FIG. 8 shows a structure identical to that of FIG. 2, one diode D2 per column receiving the column connection ci-1, ci and ci+1, followed by grid G1, which is itself followed by grid G2, respectively raised to constant potentials V1 and V2. Grid G4 is now replaced by a first grid G41 in the form of a strip and raised to a periodic potential V41. Its function is to maintain charge Q0, whose value is determined by a grid G3 which follows G41 and raised to a periodic potential V3. Grid G3 is followed by a second grid such as G4, designated in this case G42 and having notches 26 identical to the notches 24 of FIG. 2 in which are formed diodes D5. It has the function of branching charges between register 3 and the parasitic charge elimination diodes D5. G42 is raised to a periodic potential, V41 and the diodes D5 are raised to a constant potential VD5.

The columns are separated from one another, as before, by an insulation barrier 42 and diodes D5, surrounded by U-shaped insulation barriers 44 arranged in such a way that one diode D5 is common to two columns and the flow of charges transferred into a column is divided into two channels CL1 and CL2 at grid G5, which is adjacent to diodes D5, as before. The device also has grid G7, raised to potential V7, and output register 3, constructed in the same way as hitherto. Insulation barriers 42 either terminate before diodes D5 or beneath grid G7 by an e.g. square extension 46, in such a way that the charges transferred into channel CL1 can only be transferred towards electrode 32.

FIG. 9a represents a sectional view of the device of FIG. 8 along with a line EE extending from diode D2 to diode D5, then from diode D5 to an electrode 32 of the reading register.

Thus, in FIG. 9a and starting from the left, it is possible to see diode D2 receiving column connection ci, grid G1, grid G41, grid G2 between grids G1 and G41 and slightly overlapping the latter, grid G42, grid G3 placed between grids G41 and G42 and slightly overlapping them, grid G5 slightly overlapping the latter and diode D5, then grid G5 and grid G42, and then grid G7 and grid 32 of the reading register 3.

The various diagrams (a to d) of FIG. 10 represent the control signals which can be used in the device of FIG. 8. These control signals are periodic potentials, whose amplitude varies between a high level and a low level, designated VH and VB respectively for all the diagrams. However, these different potentials are not necessarily equal to one another or equal to the potentials of the previous drawings.

Diagram 10a shows potentials V41 and V42 applied to grids G41 and G42. It is at low level, except at times t1, t2, t3 and t6, t7, t8, when it is at high level.

Diagram 10b represents potentials V3 and V2 applied to grids G3 and G2 ; it is at high level during times t2 and t7.

Diagram 10c represents potential V5 applied to grid G5. It is at low level VB, except during times t1, t2, t3 and t4.

Diagram 10d represents potential V7 applied to grid G7. It is at low level except during times t6, t7, t8 and t9, when it is at high level.

Diagrams 9b to 9i represent the potential on the surface of the semiconductor substrate, at different times and increasing in the downward direction.

FIG. 9b represents the surface potential during time t1. Grid G2 is at a low level VB and isolates the photosensitive zone from the remainder of the device. On the columns, there is the training charge quantity Qo and a charge quantity QB due to a possible overlighting.

FIG. 9c represents the surface potential during time t2. Grids G2 and G3 are at a high level. The charge quantity Qo +QB is transferred in the line memory. Charge quantity Qo fullfils the potential well beneath grid G41 and charge quantity QB is transferred under grids G42.

FIG. 9d represents the surface potential during time t3. Grid G2 is at a low level. The photosensitive zone is isolated from the remainder of the device. Grid G3 is at a low level separating the grids G41 and G42.

FIG. 9e represents the surface potential during time t4. Grids G41 and G42 are at a low level. Charge quantity Qo is transferred from columns and charge quantity QB is evacuated by drain D5.

FIG. 9f represents the surface potential during times t5 and t6.

At time t5, grid G5 is at a low level and isolates the line memory from the drain D5. Moreover a clock signal, not shown on the figure, produces the arrival of the charge quantity QS on the column connections. There is then on the columns connections Qo +QS.

At time t6, grid G7 and grids G41 and G42 are at a high level.

FIG. 9g represents the surface potential during time t7. Grid G3 is at a high level and there is communication between grids G41 and G42. Grid G2 is at a high level and there is transfer from charge quantity Qo +QS from the column connections in the line memory. The charge quantity Qo is blocked under grid G41 and the signal charge quantity QS is transferred under grid G42.

FIG. 9h represents the surface potential during time t8. Grid G2 is at a low level; so is grid G3.

FIG. 9i represents the surface potential during time t9 : Grids G41 and G42 are at a low level and there is transfer of the signal charge quantity QS in the reading register 32 and transfer of the charge quantity Qo on the columns. The transfer of Qo on the columns at time t9 explains that at time t1 the charge quantity Qo +QB is on the columns.

In the embodiments of FIGS. 5 and 8, the generation of the charge quantity Qo in the line memory is quite independent from the spatial noise because this charge is created then stopped by the same grid receiving the same potential. For FIGS. 6d and g, it is the grid G7 at the potential V7. For FIG. 9d and g, it is the grid G3 at potential V3.

In the embodiment of FIG. 8, the transfer from the columns to the line memory of the signal charge quantity QS and of the charge quantity QB constituted by overlighting charges is made by adding the training charge Qo, independent from the spatial noise, to these charge quantities.

In the embodiments of FIGS. 2 and 5, it would be also possible to add the charge quantity Qo to the charge quantities QS and QB when there is transfer of the charges from the columns to the line memory.

In the operating mode of FIG. 8, the grid G2 is no longer at a constant potential as it was in the operating modes of FIGS. 2 and 5.

Where G2 is at a constant potential, after signal charges QS have been transferred from D2 to G4, the surface potential at diode D2 is equal to that of grid G2. New signal charges will arrive under D2 only at the time of the next line return. During the time interval between these two arrivals of charges, there is a leakage current which, although the MOS transistor formed by diode D2, grid G2 and the potential well under G3 is blocked, evacuates some charges from D2 to G4. This leakage current is known as subthreshold current. The surface potential at D2 increases slightly from ΔV compared with that of G2. When the signal charges of the following line are transferred on the column, they must first fill the potential "pocket" ΔV before charge Qsi can be transferred to G4. A quantity of charges Qp =C1 ·ΔV, where C1 is the column capacity, is blocked on the column and only the difference Qsi -QP is transferred, so there is a diminution of the useful signal. Sometimes, there is even QP >Qsi. In the operating mode of FIG. 8, the leakage current is delated by applying to grid G2 not a continuous voltage V2, but a periodic signal V2 having periodically a high and a low level.

So, during the line time, the signal V2 is at a low level. There is a large potential barrier between the potential at D2 and the potential under grid G2. The leakage current is then negligible.

During the line return time when charges have to be transferred from the columns to G4, the signal V2 is at a high level. The potential barrier becomes zero, so the potential at D2 equals that of grid G2.

This pulse on G2 occurs each time there is transfer from the columns to the line memory, of reading signal charges or of overlighting charges QB at the end of the line time, for example.

The amplitude of the pulse on G2 is approximately 1V to efficaciously reduce the leakage current, and it is approximately 10 to 15 Volts for the different control signals referred to hereinbefore.

Grid G1 is quite important in this mode of operating. It deletes the parasitic coupling between G2 and D2 which would have maintained the potential barrier when there is a pulse on G2. The diode D2, whithout the grid G1, whould follow the potential of G2 because of its coupling capacity with G2.

In the embodiments of FIGS. 2 and 5, it is also possible to maintain the grid G1 at a constant potential and to apply to grid G2 a periodic signal so as to maintain it at a low level, except when there is transfer of charges to the line memory.

The above description has been given relative to a non-limitative embodiment. Thus, the relative positioning of grids G1, G5 and G7 of diodes D2 and D5, as well as their dimensions, have no particular function and instead only devolve from the technological construction procedure. In the same way, the shape of the insulation barriers 43 and 46 are of a random nature, which also applies with respect to the shape of notches 24 and 26.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4620231 *Jun 18, 1984Oct 28, 1986Rca CorporationCCD imager with photodetector bias introduced via the CCD register
US4638354 *Feb 21, 1985Jan 20, 1987ProgeRapid profile recording device
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US4819067 *May 6, 1987Apr 4, 1989Thomson-LsfLine-transfer photosensitive device
US5038215 *Jan 17, 1990Aug 6, 1991Eev LimitedImaging apparatus with improved synchronization
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Classifications
U.S. Classification348/308, 348/E03.022, 257/E27.133, 348/E03.021, 348/248
International ClassificationH04N5/30, H01L27/148, H04N3/15, H01L27/14, H04N5/335, H01L27/146
Cooperative ClassificationH01L27/14643, H04N3/1575, H04N3/1568
European ClassificationH01L27/146F, H04N3/15E6, H04N3/15F
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Aug 10, 1992FPAYFee payment
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Aug 20, 1996FPAYFee payment
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