|Publication number||US4531285 A|
|Application number||US 06/477,692|
|Publication date||Jul 30, 1985|
|Filing date||Mar 21, 1983|
|Priority date||Mar 21, 1983|
|Publication number||06477692, 477692, US 4531285 A, US 4531285A, US-A-4531285, US4531285 A, US4531285A|
|Inventors||Michael R. Lucas|
|Original Assignee||The United States Of America As Represented By The Secretary Of The Navy|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Referenced by (9), Classifications (16), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to integrated circuit fabrication techniques, and more particularly to a method for interconnecting integrated circuit chip packages having package leads on very close centers to an interconnect board such that the leads are formed and soldered on very close centers, yet are protected from handling damage and lead-to-lead shorting.
2. Description of the Prior Art
The trend in integrated circuit manufacture is toward greater intergration of functions on a single chip. This results in more gates on the chips and higher input/output (I/O) pin counts. I/O requirements of over 200 leads on a single chip are projected. Packaging of these chips into a single chip package is desirable due to the high cost of the chip, the requirement for testing the chip before committing to an assembly, and the desire to easily remove and replace a defective chip in an assembly. However, current packages require extremely large sizes due to the package perimeter required for the large number of leads. A 200 lead flatpackage with leads on four sides with a standard 50 mil lead spacing would have a size over 1.5 inches square, resulting in an expensive, low-density package. Lead centers as small as 12.5 or 10 mils on a chip package are desirable. As the lead center decrease, however, the leads become more fragile and susceptible to being bent which causes alignment problems when mounting the package to a board, or even electrical shorting if the leads are so badly bent as to touch one another. Also, after the package is mounted the fragile leads are still susceptible to handling damage and possible shorts.
Accordingly, the present invention provides a method for interconnecting close lead center integrated circuit packages to boards by forming the leads as follows: (1) bonding the lead frame material to a thin insulating film, and then (2) forming the leads. Next, the film base is removed selectively where connections to the package and board will be made. The lead material is then plated and formed to provide stress relief in the package-to-board interconnect. Finally, the lead frame is attached to the package and board.
Therefore, it is an object of the present invention to provide a method for interconnecting close lead center integrated circuit packages to interconnecting boards which will avoid damage and possible shorting of leads during handling.
Other objects, advantages and novel features of the present invention will be apparent from the following detailed description read in conjunction with the appended claims and attached drawing.
FIG. 1 is a perspective view of a lead frame with close center leads according to the present invention.
FIG. 2 is a perspective view of the lead frame of FIG. 1 after selective film removal.
FIG. 3 is a perspective view of an integrated circuit package interconnected to a board by the lead frame of FIG. 2.
FIG. 4 is a top plan view of a lead frame for four-sided lead attachment.
The first step in a method for interconnecting close lead center integrated circuit packages to an interconnect board is to form a lead frame 10. Lead frame material is sheet form, such as Kovar sheet or copper sheet, is bonded using standard methods to a thin insulating film 12, such as Kapton. The lead frame material and thickness, and the film base material and thickness, are so chosen to allow the lead frame 10 to be later formed in the "Z" axis and maintain its shape due to the deformation of the metal leads, yet maintain lead-to-lead spacing in the "X" direction due to the film base. The leads 14 are then formed by some means such as etching the lead frame material, resulting in the lead frame 10 shown in FIG. 1.
Next, the film base 12 is selectively removed by some means such as laser ablation to remove material where connections to the package and interconnect board will later be made. The resulting lead frame 10 is illustrated in FIG. 2. At one end 16 a small strip of material has been removed so only a short length of leads 14 are cantilever supported. An alternate method is shown at the other end where a small strip 18 of material has been left so there is no cantilevered, or unsupported, lead ends. The lead material is plated with a suitable material such as gold or solder to prevent corrosion and to aid future soldering operations.
The lead frame 10 is formed in an "S" profile in the "Z" axis as shown in FIG. 3 to provide stress relief in the package-to-board interconnect. A typical interconnect board 20 has a plurality of mounting pads 22. A chip 24 is mounted on a chip package 26, the package in turn being bonded to the interconnect board 20. A single metalization layer 28 on the package 26 is etched to form leads from the chip 24 to the edge of the package. The lead frame 10 can be either (1) attached to the package 26 first, and then package and lead frame attached to the board 20; or (2) the package can be bonded to the board with an adhesive and the lead frame attached to both the package and board. The lead bonding may be accomplished by soldering, using a gang bonding technique to solder a whole side of leads at once, or even all sides at once. A lead frame 10' for attaching leads to all four sides of a package 26 is shown in FIG. 4.
Thus, the present invention provides a method for interconnecting close lead center integrated circuit packages to an interconnect board which uses an inexpensive, unleaded package with a single metalization layer, and which via a film support minimizes the possibility of lead damage while leaving connection joints visible for inspection after soldering.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
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|U.S. Classification||29/827, 428/459, 428/54|
|International Classification||H01L21/683, H05K3/34, H01L21/00|
|Cooperative Classification||Y02P70/613, Y10T428/31685, Y10T29/49121, H05K3/3426, H01L21/6835, H01L21/67144, Y10T428/18|
|European Classification||H01L21/67S2T, H05K3/34C3B, H01L21/683T|
|Mar 21, 1983||AS||Assignment|
Owner name: UNITED STATES OF AMERICA AS REPRESENTED BY THE SE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:LUCAS, MICHAEL R.;REEL/FRAME:004137/0158
Effective date: 19830209
|Aug 5, 1988||FPAY||Fee payment|
Year of fee payment: 4
|Mar 2, 1993||REMI||Maintenance fee reminder mailed|
|Aug 1, 1993||LAPS||Lapse for failure to pay maintenance fees|
|Oct 19, 1993||FP||Expired due to failure to pay maintenance fee|
Effective date: 19930801