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Publication numberUS4539744 A
Publication typeGrant
Application numberUS 06/576,665
Publication dateSep 10, 1985
Filing dateFeb 3, 1984
Priority dateFeb 3, 1984
Fee statusPaid
Also published asCA1232368A, CA1232368A1, DE3587238D1, DE3587238T2, EP0154573A2, EP0154573A3, EP0154573B1
Publication number06576665, 576665, US 4539744 A, US 4539744A, US-A-4539744, US4539744 A, US4539744A
InventorsGreg Burton
Original AssigneeFairchild Camera & Instrument Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor planarization process and structures made thereby
US 4539744 A
Abstract
A silicon substrate having a silicon dioxide bird's head is provided. A thermal oxide layer is grown on the exposed silicon surface. A layer, e.g., 4000 A, of phosphogermanosilicate glass is deposited on the thermal oxide and on the silicon dioxide bird's head. The structure is heated to 950 C., causing a reflow of the glass which results in a planar surface. The thermal oxide and the phosphogermanosilicate glass are then wet etched at the same rate with a solution of hydrofluoric acid, ammonium fluoride, and deionized water. The wet etch is terminated when the exposed silicon surface is reached, resulting in a smooth surface as defined by the planar reflow surface. Other embodiments are disclosed.
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Claims(19)
What is claimed as new and desired to be secured by Letters Patent of the United States is:
1. A method of making a semiconductor structure, comprising the steps of:
(a) providing a semiconductor substrate having at least one substantially planar surface, said substrate comprising silicon,
(b) forming an electrically insulating pattern adjacent said surface, said insulating pattern comprising silicon dioxide and including at least one portion thereof which extends outward beyond and away from said remaining planar surface,
(c) depositing a film of electrically insulating material over said surface and said portions, said material comprising germanosilicate glass,
(d) planarizing said film of step (c),
(e) wet etching said film of step (c) and said electrically insulating pattern of step (b) at substantially the same rate, and
(f) terminating the etching step when a predetermined thickness of said film of step (c) and said electrically insulating pattern of step (b) have been etched.
2. A method in accordance with claim 1 in which step (b) comprises oxidizing said surface of said substrate.
3. A method in accordance with claim 2 which comprises forming an oxide film on said remaining planar surface between steps b and c.
4. A method in accordance with claim 2 in which said glass includes P2 O5.
5. A method in accordance with claim 4 in which said glass comprises SiO2 in the range of from about 5% to about 80%, GeO2 in the range of from about 10% to about 100% and P2 O5 in the range of from about 0% to about 10%.
6. A method in accordance with claim 2 in which step (d) comprises heating said glass to cause a reflow thereof and provide a planar surface.
7. A method in accordance with claim 6 which comprises heating said glass in the range of from about 850 C. to about 1100 C.
8. A method in accordance with claim 6 in which step (e) comprises wet etching with an etchant which does not react with silicon.
9. A method in accordance with claim 9 in which the step of wet etching utilizes an etchant which comprises hydrofluoric acid, ammonium fluoride, and deionized water.
10. A method in accordance with claim 10 in which said etchant comprises hydrofluoric acid in the range of from about 3% to about 30%, ammonium fluoride in the range of from about 10% to about 95%, and deionized water in the range of from about 0% to about 90%.
11. A method in accordance with claim 10 in which said etchant is maintained at a temperature of from about 15 C. to about 30 C.
12. A method in accordance with claim 4 in which said glass comprises SiO2 in the range of from about 5% to about 80%.
13. A method in accordance with claim 4 in which said glass comprises GeO2 in the range of from about 10% to 100%.
14. A method in accordance with claim 4 in which said glass comprises P2 O5 in the range of from about 0% to about 10%.
15. A method in accordance with claim 1 in which step (f) comprises terminating the etching step when said planar surface of the substrate is reached.
16. A method of making a semiconductor structure, comprising the steps of:
(a) providing a semiconductor substrate having at least one substantially planar surface, said substrate comprising silicon,
(b) forming an electrically insulating pattern adjacent said surface, said insulating pattern comprising silicon dioxide and including at least one portion thereof which extends outward beyond and away from said remaining planar surface,
(c) depositing a film of electrically insulating material over said surface and said portions, said material comprising germanosilicate glass,
(d) planarizing said film of step (c),
(e) wet etching said film of step (c) and said electrically insulating pattern of step (b) at predetermined different rates, and
(f) terminating the etching step when a predetermined thickness of said film of step (c) and said electrically insulating pattern of step (b) have been etched.
17. A method in accordance with claim 16 in which step (f) comprises terminating the etching step prior to reaching said planar surface of the substrate.
18. A method in accordance with claim 1 in which said one portion comprises a bird's head.
19. A method of making a semiconductor structure, comprising the steps of:
(a) providing a semiconductor substrate having at least one substantially planar surface, said substrate comprising silicon,
(b) forming an electrically insulating pattern adjacent said surface, said insulating pattern comprising silicon dioxide and including at least one portion thereof which extends outward beyond and away from said remaining planar surface,
(c) depositing a film of electrically insulating material over said surface, and said portions, said material comprising germanosilicate glass,
(d) planarizing said film of step (c)
(e) wet etching said film of step (c) and said electrically insulating pattern of step (b), and
(f) terminating the etching step when a predetermined thickness of said film of step (c) and said electrically insulating pattern of step (b) have been etched.
Description
BACKGROUND OF THE INVENTION

The present invention relates generally to a planarization process, and more particularly, to such a process for use in the manufacture of semiconductor structures.

A well known technique for creating dielectrically isolated integrated circuits through the use of oxidation is disclosed in U.S. Pat. No. 3,648,125, issued Mar. 7, 1972, assigned to the assignee of the present invention and hereby incorporated by reference. This commonly employed technique is often referred to as LOCOS (Local Oxidation Of Silicon).

Although the LOCOS technique provides a simple and effective means to dielectrically isolate semiconductor integrated circuits, use of this technique typically results in a topographical surface which is non-planar. In the case of silicon semiconductor material, the resulting non-planar structure on the surface is referred to as a "bird's head". Such a non-planar surface is undesirable for high density applications where the non-planar surface is further processed to include additional structure, e.g., metallization, thereon. For example, in such high density applications, the presence of the bird's head creates problems in defining photoresist and etching of thin films in subsequent process steps.

Current techniques to planarize the bird's head typically provide a planar layer of organic material, e.g., photoresist, over the bird's head which layer is subsequently etched, along with the underlying bird's head. The etching employs a dry etch which is intended to etch both materials at the same rate. The dry etch techniques are undesirable inasmuch as they require expensive equipment and provide a low wafer throughput. In addition, the dry etch technique is difficult to apply successfully as the etch rate typically exhibits non-uniformity across the wafer surface. Also, the dry etch process requires careful control inasmuch as the underlying silicon surface is easily damaged by the dry etch.

Accordingly, a general object of the present invention is to provide an improved planarization process.

Another object of the present invention is to provide such a process which does not require the use of a dry etch.

Another object of the present invention is to provide such a process which can be easily added to a conventional semiconductor fabrication procedure.

Another object of the present invention is to provide improved semiconductor structures made by such process.

SUMMARY

In one form of the invention, I provide a method of making a semiconductor structure. The method includes the step of providing a semiconductor substrate having at least one planar surface and forming an insulating pattern adjacent the surface, with the insulating pattern including at least one portion thereof which extends outward beyond the remaining planar surface. The method includes the step of depositing a film of electrically insulating material over the surface and the portions which extend outward and the step of planarizing the film. In one form, the method includes the step of wet etching the film and the electrically insulating material at substantially the same rate and the step of terminating the etching step when a predetermined thickness of the film and the electrically insulating material have been etched, e.g., when the planar surface of the substrate is reached.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partially sectioned elevational view of a semiconductor structure having a non-planar surface in the form of a bird's head.

FIGS. 2-4 are elevational views, taken as in FIG. 1, showing the structure of FIG. 1 as it is processed in accordance with one form of the method of the present invention.

FIGS. 5 and 6 are elevational views, taken as in FIG. 1, showing other forms of the method of the present invention in which a predetermined degree of planarity is achieved.

DETAILED DESCRIPTION

Referring initially to FIG. 1, an exemplary semiconductor structure is generally designated 10. The structure 10 is in the form of a substrate and includes a portion 12 of silicon and an immediately contiguous portion 14 of silicon dioxide. The combined surfaces 12A and 14A presented by the silicon 12 and silicon dioxide 14 are non-planar, with the silicon dioxide 14 in the form of the well known "bird's head".

Referring now to FIG. 2, in one form of the method of the present invention, a relatively thin, e.g., 1000 Å, film 16 of thermal oxide is preferably first grown on the exposed silicon surface 12A. Next, a layer 18 of electrically insulating material, such as a germanosilicate glass, is deposited on the film 16 and on the silicon dioxide surface 14A. A preferred germanosilicate glass comprises 54% SiO2, 42% GeO2, and 4% P2 O5 (hereinafter PVX-II). Glass composition, as used in this Application, is expressed as a mole percentage. Typically, the layer 18 has a thickness in the range of from about 3000 Å to about 5000 Å. Further information on suitable germanosilicate glasses can be found in U.S. application Ser. No. 362,322, entitled "Smooth Glass Insulating Film Over Interconnects On An Integrated Circuit", filed Mar. 26, 1982, now U.S. Pat. No. 4,490,737, and assigned to the assignee of the present invention.

Next, as shown in FIG. 3, the layer 18 of electrically insulating material is planarized. In the case of germanosilicate glass, this planarizing step is conveniently performed through reflow thereof initiated by heat treatment. Typically, heat treatment in the range of from about 850 C. to about 1100 C. for a time period of about 30 minutes provides a satisfactory planar surface 18A.

Next, as shown in FIGS. 3-4, the layer 18 of electrically insulating material and the bird's head portion 14 are wet etched in an etch solution such that the etch rate of the insulating material 18 and the bird's head portion 14 are substantially the same. This wet etching is shown schematically in FIG. 3 through the use of horizontal dashed lines. It is to be appreciated that the resulting surface, after etching, reproduces the same degree of planarity as the layer 18, subsequent to its planarization. In one form of the invention this wet etching step is terminated when the silicon surface 12A is again exposed, as shown in FIG. 4.

When using germanosilicate glass for the insulating layer 18 in the form of PVX-II, a preferable wet etch solution comprises 11.8% hydrofluoric acid (49% solution), 45.4% ammonium fluoride (40% solution), and 42.7% deionized water, with the etchant maintained from about 15 C. to about 30 C., preferably at about 20 C. Wet etch composition, as used in this Application, is expressed as a volume percentage. This wet etch solution attacks the silicon dioxide 14 and PVX-II at the rate of about 1000 Å/minute.

In another form of the invention, the previously described wet etching step may be terminated prior to reaching the silicon surface 12A. For example, as shown in FIG. 5, the wet etching step may be terminated when a predetermined thickness of the bird's head 14 has been etched. The remaining PVX-II layer 18 may then be conveniently and selectively removed from the silicon surface 12A by exposing the structure to a weak hydrofluoric acid solution e.g., 10:1 ratio, such that the PVX-II etch rate is substantially faster than the thermal oxide etch rate. The remaining oxide layer 16 can then be removed by conventional wet etch techniques. This form of the invention may be desired in order to reduce the possibility of exposing the silicon sidewall through over etching of the thermal oxide.

In still another form of the invention, the relative etch rates of the PVX-II and thermal oxide films can be varied to provide a desired result. Such variation is conveniently accomplished by changing the composition of the wet etching solution. In this connection, in general, as the hydrofluoric acid concentration is decreased, the PVX-II etch rate becomes significantly faster than the thermal oxide etch rate. Thus, the selection of the wet etch composition can be used to provide various degrees of planarization. For example, as shown in FIG. 6, one application may require that only two thirds (2/3) of the bird's head 14 is to be removed. For such an application, the composition of the wet etch solution would be chosen to etch PVX-II at a rate which is three-halves (3/2) greater than that of the thermal oxide.

Of course, the method of the present invention is not limited to the specific materials discussed above. For example, further information on suitable germanosilicate glasses can be found in U.S. application Ser. No. 362,322, entitled "Smooth Glass Insulating Film Over Interconnects On An Integrated Circuit", filed Mar. 26, 1982, and assigned to the assignee of the present invention. In this connection, preferable germanosilicate glasses include those having: SiO2 in the range of from about 5% to about 80%; GeO2 in the range of from about 10% to about 100%; and P2 O5 in the range of from about 0% to about 10%.

Similarly, the invention is not limited to the hydrofluoric wet etch solution discussed above. In this connection, preferable hydrofluoric etch solutions include those having: hydrofluoric acid in the range of from about 3% to about 30%; ammonium fluoride in the range of from about 10% to about 95%; and deionized water in the range of from about 0% to about 90%.

Further, the method of the present invention is not limited to the use of planarizing germanosilicate glass in combination with a silicon dioxide bird's head. Indeed, the present invention is generally applicable to any semiconductor fabrication in which a non-planar surface is presented by at least two different materials and in which it is desirable to planarize the non-planar surface. Thus, in multilevel semiconductor structures, the method of the present invention can be repeated at some or all of the various levels. Similarly, the non-planar surface need not be in the form of a bird's head, as in the case of a thermally grown oxide but may, for example, be in the form of a deposited pattern such as that produced by a deposition of silicon dioxide through sputtering or chemical vapor deposition.

Use of the method of the present invention requires little additional expense in the fabrication of semiconductors inasmuch as the preferred phosphogermosilicate glass is formed by low temperature, e.g., 430 C.; deposition at atmospheric pressure while the planarizing heat treatment and the wet etch are routine semiconductor fabrication procedures. Further, the semiconductor structure, e.g., wafer, throughput is high inasmuch as the steps involved in the method can be easily performed simultaneously, i.e., batch processed, on a plurality of wafers. The method does not require a higher degree of operator skill inasmuch as the individual steps involved are essentially classical fabrication procedures.

Semiconductor structures made by the method of the present invention present a uniform result across a wafer surface particularly because the planarizing layer e.g., PVX-II, is relatively thin, e.g., 4000 Å while the wet etch process displays acceptable uniformity, e.g., +2%, across a wafer. Also, referring to FIGS. 4-6, the integrity of the silicon surface 12A is preserved inasmuch as the wet etch solution is selected to be non-reactive with silicon.

While the present invention has been described with reference to specific embodiments thereof, it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the invention in its broader aspects. It is contemplated in the appended claims to cover all such variations and modifications of the invention which come within the true spirit and scope of the invention.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
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Non-Patent Citations
Reference
1Tenney, A. S. et al., "Etch Rates of Doped Oxides in Solutions of Buffered HF", in J. Electrochem. Soc., 120 (8), pp. 1091-1095, 8-1973.
2 *Tenney, A. S. et al., Etch Rates of Doped Oxides in Solutions of Buffered HF , in J. Electrochem. Soc., 120 (8), pp. 1091 1095, 8 1973.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4612701 *Mar 12, 1984Sep 23, 1986Harris CorporationMethod to reduce the height of the bird's head in oxide isolated processes
US4649638 *Apr 17, 1985Mar 17, 1987International Business Machines Corp.Construction of short-length electrode in semiconductor device
US4708767 *Oct 5, 1984Nov 24, 1987Signetics CorporationMethod for providing a semiconductor device with planarized contacts
US4721548 *May 13, 1987Jan 26, 1988Intel CorporationSemiconductor planarization process
US4721687 *Feb 6, 1987Jan 26, 1988Kabushiki Kaisha ToshibaMethod of increasing the thickness of a field oxide
US4780429 *May 13, 1986Oct 25, 1988Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux EfcisMethod of fabrication of MOS transistors having electrodes of metallic silicide
US4935095 *Jun 21, 1985Jun 19, 1990National Semiconductor CorporationGermanosilicate spin-on glasses
US4952525 *Dec 11, 1989Aug 28, 1990U.S. Philips CorporationMethod of manufacturing a semiconductor device in which a silicon wafer is locally provided with field oxide regions
US4983537 *Nov 24, 1989Jan 8, 1991General Electric CompanyMethod of making a buried oxide field isolation structure
US4986878 *Jul 19, 1988Jan 22, 1991Cypress Semiconductor Corp.Process for improved planarization of the passivation layers for semiconductor devices
US5006476 *Nov 20, 1989Apr 9, 1991North American Philips Corp., Signetics DivisionTransistor manufacturing process using three-step base doping
US5014107 *Aug 29, 1989May 7, 1991Fairchild Semiconductor CorporationProcess for fabricating complementary contactless vertical bipolar transistors
US5114867 *Sep 17, 1990May 19, 1992Rockwell International CorporationSub-micron bipolar devices with method for forming sub-micron contacts
US5212116 *Feb 28, 1992May 18, 1993At&T Bell LaboratoriesMethod for forming planarized films by preferential etching of the center of a wafer
US5252143 *Feb 18, 1992Oct 12, 1993Hewlett-Packard CompanyBipolar transistor structure with reduced collector-to-substrate capacitance
US5413953 *Sep 30, 1994May 9, 1995United Microelectronics CorporationMethod for planarizing an insulator on a semiconductor substrate using ion implantation
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US5554560 *Sep 30, 1994Sep 10, 1996United Microelectronics CorporationMethod for forming a planar field oxide (fox) on substrates for integrated circuit
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Classifications
U.S. Classification438/443, 438/698, 257/E21.552, 257/E21.243, 438/699, 257/E21.274, 257/647, 257/506, 257/E21.251
International ClassificationH01L21/302, H01L21/306, H01L21/762, H01L21/3105, H01L21/316, H01L21/3065, H01L21/311
Cooperative ClassificationH01L21/31111, H01L21/31051, H01L21/31604, H01L21/76202
European ClassificationH01L21/762B, H01L21/311B2, H01L21/316B, H01L21/3105B
Legal Events
DateCodeEventDescription
Feb 3, 1984ASAssignment
Owner name: FAIRCHILD CAMERA AND INSTRUMENT CORPORATION 464 EL
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:BURTON, GREG;REEL/FRAME:004230/0837
Effective date: 19840126
Mar 2, 1989FPAYFee payment
Year of fee payment: 4
Sep 28, 1992FPAYFee payment
Year of fee payment: 8
Aug 5, 1996ASAssignment
Owner name: NATIONAL SEMICONDUCTOR CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FAIRCHILD SEMICONDUCTOR CORPORATION;REEL/FRAME:008059/0846
Effective date: 19960726
Feb 25, 1997FPAYFee payment
Year of fee payment: 12