|Publication number||US4546329 A|
|Application number||US 06/424,816|
|Publication date||Oct 8, 1985|
|Filing date||Sep 27, 1982|
|Priority date||Sep 27, 1982|
|Publication number||06424816, 424816, US 4546329 A, US 4546329A, US-A-4546329, US4546329 A, US4546329A|
|Inventors||John D. Unger|
|Original Assignee||Motorola, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (16), Classifications (8), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to frequency synthesizers, and more particularly to an improved dual-bandwidth loop filter for use in frequency synthesizers of the type containing digital phase comparators.
In radio frequency synthesizers, it is desirable to have fast frequency locking characteristics when switching to a desired radio signal frequency, while at the same time, adequately attenuating reference signal feedthru and modulating the synthesizer output with signals having frequencies as low as 200 Hz once the synthesizer has locked onto the desired radio signal frequency. In order to provide fast frequency locking characteristics, prior art synthesizers, such as the described in U.S. Pat. No. 4,330,758, provide a wide loop bandwidth in order to lock quickly to a desired radio signal frequency and a narrower loop bandwidth once frequency lock has been obtained in order to attenuate reference signal feedthru. However, in switching from a wide to a narrow loop bandwidth, such prior art synthesizers typically introduce voltage transients which result in undesirable noise on the synthesizer output signal, the duration of which is stretched and emphasized due to the narrower loop bandwidth. Furthermore, much more costly and complex circuitry is required in the sample-and-hold phase comparator used in the synthesizer in U.S. Pat. No. 4,330,758 than in a digital phase comparator. In prior art synthesizers containing digital phase comparators, an extended modulation signal bandwidth has been obtained by modulating both the reference oscillator and the voltage-controlled oscillator. However, this scheme not only requires an expensive reference oscillator, but also results in excessive reference signal feedthru.
Accordingly, it is an object of the present invention to provide an improved adaptive loop filter for frequency synthesizers that greatly attentuates noise due to bandwidth switching and reference signal feedthru.
It is another object of the present invention to provide an improved adaptive loop filter for frequency synthesizers that locks on frequency quickly and is also modulatable at audio signal frequencies as low as 200 Hz.
Briefly described, the present invention encompasses an improved loop filter for frequency synthesizers of the type including a signal source for generating a reference signal, a phase detector coupled to the reference signal and a first feedback signal for generating an error signal, a voltage-controlled oscillator (VCO) coupled to the loop filter, and a divider coupled to the VCO for providing the first feedback signal. The improved loop filter includes a current limiter coupled to the error signal from the phase detector for generating a current-limited output signal; a first resistor coupled to the current limiter output signal; a filter coupled to the first resistor and including a series-coupled second resistor and capacitor for filtering the current limiter output signal to provide a steering signal which is coupled to the VCO; an amplifier coupled to the junction between the series-coupled second resistor and the capacitor for generating a second feedback signal; and a third resistor coupling the second feedback signal to the current limiter output signal for substantially reducing the duration of voltage transients on the current limiter output signal.
A frequency synthesizer including a detailed circuit diagram of an adaptive loop filter embodying the present invention is illustrated in the drawing.
Referring to the drawing, there is illustrated a frequency synthesizer or a radio transmitter that includes an improved adaptive loop filter 114, 150 and 140 embodying the present invention. The adaptive loop filter 114, 150 and 140 is responsive to a bandwidth control signal for switching the loop bandwidth of the synthesizer between a wide bandwidth for locking the loop quickly and a narrow bandwidth once lock is obtained. In the preferred embodiment, the loop bandwidth is switched between a wide bandwidth of 600 Hz and a narrow bandwidth of 80 Hz. The narrow bandwidth has been selected to be 80 Hz so that the frequency response of the synthesizer will be relatively flat at audio signal frequencies as low as 200 Hz. As a result, the synthesizer can be modulated by a modulation signal, such as audio signals or digital data signals, having frequencies ranging from as low as 200 Hz to 3,000 Hz or higher.
In addition to loop filter 114, 150 and 140, the synthesizer includes a voltage-controlled oscillator (VCO) 112 having a steering input coupled to the output of the loop filter, a mixer 156 coupled to an external reference signal and the output signal of VCO 112, a divider 108 coupled to the output of mixer 156, a reference oscillator 102 providing a reference signal of a predetermined frequency, a reference divider 106 coupled to the reference signal, and a phase detector 110 coupled to the outputs of reference divider 106 and divider 108. In a radio transceiver, the external reference signal can be provided by another synthesizer in the receiver. In such radio transceivers, mixer 156 is used to maintain a constant offset between the frequencies of the output signals from the transmitter synthesizer and receiver synthesizer. In other applications, the VCO output signal can be connected directly to divider 108.
Reference divider 106, divider 108 and phase detector 110 can be provided by commercially available frequency synthesizer integrated circuits 104, such as the Motorola type MC145146 and MC145156 frequency synthesizer integrated circuits manufactured by Motorola Semiconductor Products, Inc., Austin, Texas. Specifications describing the operation and circuitry of the MC145146 and MC145156 frequency synthesizer are published by an available from Motorola Semiconductor Products, Inc. Separate integrated circuits are also commercially available for reference divider 106, divider 108 and phase detector 110.
The output signal provided by the synthesizer is taken from VCO 112 and may be coupled to the transmitting circuitry of a conventional radio transceiver. VCO 112 may also be coupled to a modulation signal, which may be an audio signal such as voice signals from a microphone or a digital signal such as a binary data signal. The synthesizer and transmitting circuitry are described in further detail in Motorola instruction manual no. 68P81061E10 entitled "MCR 1200 Nordic Mobile Telephone", published by and available from the Technical Writing Services Department, Motorola, Inc., 1301 East Algonquin Road, Schaumburg, Illinois.
Adaptive loop filter 114, 150 and 140 includes a current limiter 114, lag filter 150 and reference filter 140. Current limiter 114 includes transistors 116 and 122 which generate a current-limited output signal by bleeding off excess current from the error signal output of phase detector 110 to the +V supply through resistor 123 or to signal ground through resistor 117. This operation is possible since the tri-state output of phase detector 110 in MOS synthesizer integrated circuits 104 possesses inherent current limiting characteristics. A relatively small current through resistor 120 biases either transistor 116 or transistor 122 into the on state in response to a high or low pulse, respectively, from the error signal output of phase detector 110. The error signal from phase detector 110 is a high or low pulse having a repetition rate equal to the frequency of the reference signal from reference oscillator 102 divided by the pre-selected modulus of divider 106.
The synthesizer has two operational states, a 600 Hz bandwidth state or acquisition mode, and an 80 Hz bandwidth state or tracking mode. During the quiescent 80 Hz bandwidth state, the output of phase comparator 110 spends most of the time in a high impedance tri-state mode, and generates high or low pulses as required to keep the loop in phase lock during minor perturbations, such as noise generated in the internal circuitry, or voltage variations due to leakage current through capacitors in the loop filter. This is true in general of digital phase comparators having a tri-state output. These pulses result in necessary reference signal energy at the phase detector output, which is filtered and greatly attenuated by the loop filter before reaching the steering input of VCO 112. Additional unnecessary reference signal energy is generated by the residual capacitance in the phase comparator output due to the fact that the voltage at its output will usually remain near +V or ground after each pulse since most conventional phase comparators (such as those in the MC145146 and MC145156 synthesizer integrated circuits) do not switch the pull-up and the pull-down transistors in the tri-state output circuit to the tri-state mode at exactly the same time. In prior art synthesizers, the energy stored in the residual capactance of the phase detector output is discharged into a typically large value resistor 124, causing substantial unnecessary reference energy which appears as undesirable spurious energy on the VCO output signal.
According to an important feature of the present invention, the inclusion of resistor 132 and amplifier 138 discharges the residual capacitance of the phase detecter output rapidly, thus minimizing unnecessary reference signal energy and substantially eliminating reference signal feedthru. When the output of phase comparator 110 is in the tri-state mode, the residual capacitance is discharged by amplifier 138 through resistor 132 and current limiter 114. Due to the fact that the average voltage on each end of resistor 132 is the same in the quiescent state, the presence of the resistor 132 does not disturb the high impedance tri-state mode of the output of phase detector 110. This is necessary to maintain proper operation of phase detector 110.
The loop bandwidth of the synthesizer is switched between a wide bandwidth of approximately 600 Hz in the acquisition mode and a narrow bandwidth of approximately 80 Hz in the tracking mode by turning on and turning off transmission gates 126 and 128. Although transmission gates 126, 128 and 146 are shown functionally as blocks, they are field effect transistors in the preferred embodiment of the present invention. In the signal acquisition mode, transmission gates 126 and 128 turn on providing a wide loop bandwidth when the bandwidth control signal has a binary zero state. When turned on, transmission gate 126 substantially shorts out resistor 124. When transmission gate 128 is turned on, current limiter 114 is coupled to capacitor 136 by resistor 130. The value of resistor 130 is preferably chosen to be much smaller than the value of resistors 124 and 134. As a result, in the acquisition mode, the amount of current coupled to capacitor 136 during each error pulse from phase detector 110 is increased. Therefore, the magnitude of the control voltage signal can be changed more quickly, and in turn the frequency of VCO 112 is correspondingly changed more quickly in the acquisition mode. For example, current pulses of as much as two milliamps may be generated for charging and/or discharging capacitor 136 when transmission gates 126 and 128 are turned on. The maximum amount of current is limited only by the current output capacity of phase detector 110, and is held constant over varying steering line voltages by current limiter 114.
In the tracking mode, transmission gates 126 and 120 turn off providing a narrow loop bandwidth when the bandwidth control signal has a binary one state. When transmission gates 126 and 128 are turned off, capacitor 136 is charged by much smaller current pulses by means of resistors 124 and 134. For example, when the desired frequency of the output signal from VCO 112 is reached, the bandwidth control signal may be switched from the binary zero state to the binary one state by other circuitry, such as a loop-lock detector (not shown). When the loop is locked, the steering line voltage stored on capacitor 136 and the frequency of VCO 112 is changed in much smaller increments via resistors 124 and 134. For example, the current pulses coupled through resistors 124 and 134 to capacitor 136 may be on the order of fifty microamps or less when the loop is locked.
Resistor 130 and resistors 124 and 134 essentially provide constant charging and discharging currents to capacitor 136 in response to each low or high pulse, respectively, of the error signal output of phase detector 110. The magnitude of the charging/discharging current is limited by, but not directly determined by, current limiter 114. The current from current limiter 114 is divided by resistor 132 and either resistor 124 or 130 depending upon whether the acquisition or tracking mode is active. In the tracking mode, most of the current goes through resistor 132 since resistor 124 is greater in value than resistor 132, and produces a voltage drop across resistor 132 which is independent of the steering line voltage. In this case, the charrging/discharging current into capacitor 136 is determined by resistors 124 and 132 and the voltage drop across resistor 132. This configuration allows resistor 124 to be very large in value, without creating unnecessary reference feedthru. In the acquisition mode, most of the current goes through resistor 130 since resistor 130 is smaller than resistor 132. The voltage drop produced across resistors 132 and 130 is also independent of the steering line voltage. The charging/discharging current into capacitor 136 is now determined by the resistance of, and voltage drop across, resistor 130.
In the signal tracking mode, the magnitude of the current pulses applied to capacitor 136 is primarily determined by resistor 124, assuming resistor 124 is much greater than resistor 134. In this mode, the natural frequency Wn and dampening factor D for the loop can be expressed as follows:
D=(Wn R134 C136)/2;
where G is the open-loop gain, R134 is resistor 134, and C136 is capacitor 136. The open-loop gain G is a function of resistors 120, 132, 124 and 134. In the signal acquisition mode, the magnitude of the current pulses applied to capacitor 136 is primarily determined by resistor 130, assuming resistor 134 is much greater than resistor 130. In this mode, the natural frequency Wn and dampening factor D for the loop can be expressed as follows:
D=(Wn R130 C136)/2;
where R130 is resistor 130, and C136 is capacitor 136. The open-loop gain G is now a function of resistors 120, 132 and 130.
In order to be able to modulate the synthesizer with signals having frequencies as low as 200 Hz, it is necessary that the natural frequency Wn be rather small. The natural frequency Wn is made small by making the current pulses from phase detector 110 small. Therefore, in the tracking mode, the current pulses from phase detector 110 are made small (e.g. fifty microamps) by making resistor 124 large. Resistor 124 can be made very large in value, since most of the current from each phase detector pulse goes through resistor 132.
Referring to reference filter 140, reference signal feedthru is further attenuated by a two-section filter, the first section of which is comprised of resistor 142 and capacitor 144 and the second section of which is comprised of resistor 148 and capacitor 154. Another feature of the present invention is that the phase shift produced by reference filter 140 is changed when switching bandwidths in response to the bandwidth control signal. Transmission gate 146 is turned on in response to a binary one state of the bandwidth control signal in the signal tracking mode, and is turned off in response to a binary zero state of the bandwidth control signal to provide less phase shift at low signal frequencies so that the loop will remain stable in the acquisition mode. For example, the phase shift may be reduced from forty-nine degrees for signals having a frequency of 600 Hz when transmission gate 146 is on and maximum reference signal attenuation is desired in the tracking mode, to a phase shift of twenty-eight degrees for signals having a frequency of 600 Hz when transmission gate 146 is off and loop stability is desired in the acquisition mode.
In addition, according to another feature of the present invention, transmission gate 146 is coupled in parallel across resistor 152 to provide transient free switching. That is, resistor 152 is coupled between capacitors 154 and 144 and signal ground for establishing a voltage substantially equal to signal ground at the terminals of capacitors 154 and 144 that are coupled to transmission gate 146. Therefore, when transmission gate 146 turns on to switch to the tracking mode, no transients are generated since capacitors 154 and 144 have reached signal ground during the acquisition mode. In contrast, resistors 148 and 142 are shorted out during the acquisition mode in some prior art synthesizers. Thus, when switching to the tracking mode, such prior art synthesizers generate a voltage transient on the steering line voltage. Switching between the acquisition mode and tracking mode is transient free in reference filter 140 since the voltages across resistors 148 and 142 developed due to leakage currents in the steering input of VCO 112 will reach quiescent value during the acquisition mode and remain the same when switching to the tracking mode.
In summary, an improved adaptive loop filter for frequency synthesizers has been described that is modulatable over a wide range of audio signal frequencies, while at the same time obtaining lock quickly when the synthesizer frequency is changed. The unqiue adaptive loop filter also provides enhanced noise rejection characteristics, so that reference signal feedthru and switching transients are greatly attentuated. The adaptive loop filter of the present invention provides a wide loop bandwidth for signal acquisition and a narrow loop bandwidth for signal tracking once frequency lock has been obtained. The unique adaptive loop filer can be used in any suitable frequency synthesizer, such as those typically employed in the transmitter and receiver portions of radio transceivers.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4007429 *||Jan 19, 1976||Feb 8, 1977||Gte International Incorporated||Phase-locked loop having a switched lowpass filter|
|US4135165 *||Jun 30, 1977||Jan 16, 1979||Coe Thomas F||Phase-locked loop oscillator|
|US4167711 *||May 26, 1978||Sep 11, 1979||Motorola, Inc.||Phase detector output stage for phase locked loop|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4752749 *||Dec 22, 1986||Jun 21, 1988||Rockwell International Corporation||Fast response tuner|
|US4912434 *||Feb 27, 1989||Mar 27, 1990||Honeywell Inc.||Digital control for analog phase locked loop|
|US5052032 *||Jul 16, 1990||Sep 24, 1991||Nakamichi Corporation||Clock formation circuit|
|US5055803 *||Dec 14, 1990||Oct 8, 1991||Motorola, Inc.||Parameter tolerant PLL synthesizer|
|US5142246 *||Jun 19, 1991||Aug 25, 1992||Telefonaktiebolaget L M Ericsson||Multi-loop controlled VCO|
|US5146187 *||Jul 1, 1991||Sep 8, 1992||Ericsson Ge Mobile Communications Inc.||Synthesizer loop filter for scanning receivers|
|US5281930 *||Jun 3, 1992||Jan 25, 1994||Matsushita Electric Industrial Co., Ltd.||Frequency modulator|
|US5317285 *||Feb 26, 1993||May 31, 1994||Motorola, Inc.||Frequency synthesizer employing a continuously adaptive phase detector and method|
|US5347233 *||Mar 30, 1993||Sep 13, 1994||Mitsubishi Denki Kabushiki Kaisha||PLL circuit apparatus and phase difference detecting circuit apparatus|
|US5373259 *||May 5, 1993||Dec 13, 1994||Qualcomm Incorporated||Voltage controlled oscillator with dissimilar varactor diodes|
|US5418503 *||Mar 8, 1993||May 23, 1995||Ericsson Ge Mobile Communications Inc.||Compensation of transient frequency drift in oscillator circuits|
|US7398071 *||Dec 17, 2004||Jul 8, 2008||Broadcom Corporation||Loop filter with gear shift for improved fractional-N PLL settling time|
|US8027461||Oct 11, 2007||Sep 27, 2011||Adtran, Inc.||Systems and methods for splitting telecommunication signals with reduced noise|
|US8437111||Nov 17, 2008||May 7, 2013||Adtran, Inc.||Systems and methods for current limiting with overload protection|
|DE4498750C2 *||Oct 14, 1994||Apr 12, 2001||Motorola Inc||Fehlerunterdrückungsschaltung und zugehöriges Verfahren für einen PLL-Kreis|
|DE4498750T1 *||Oct 14, 1994||Jan 11, 1996||Motorola Inc||Fehlerunterdrückungsschaltung und zugehöriges Verfahren für eine PLL-Kreis|
|U.S. Classification||331/16, 331/DIG.200, 331/25, 331/17|
|Cooperative Classification||Y10S331/02, H03L7/107|
|Sep 27, 1982||AS||Assignment|
Owner name: MOTOROLA, INC., SCHAUMBURG, ILL., A CORP. OF DEL.
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:UNGER, JOHN D.;REEL/FRAME:004058/0797
Effective date: 19820923
Owner name: MOTOROLA, INC., ILLINOIS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UNGER, JOHN D.;REEL/FRAME:004058/0797
Effective date: 19820923
|Mar 7, 1989||FPAY||Fee payment|
Year of fee payment: 4
|Oct 29, 1992||FPAY||Fee payment|
Year of fee payment: 8
|Mar 3, 1997||FPAY||Fee payment|
Year of fee payment: 12