|Publication number||US4558233 A|
|Application number||US 06/467,075|
|Publication date||Dec 10, 1985|
|Filing date||Feb 16, 1983|
|Priority date||Feb 16, 1982|
|Also published as||DE3365050D1, EP0086671A1, EP0086671B1|
|Publication number||06467075, 467075, US 4558233 A, US 4558233A, US-A-4558233, US4558233 A, US4558233A|
|Original Assignee||Fujitsu Limited|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Non-Patent Citations (2), Referenced by (18), Classifications (12), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a voltage detecting circuit. More particularly, the present invention relates to a circuit for detecting the buildup of the power source voltage and which is used when an internal circuit is automatically reset at the time the power source is switched on.
When electronic equipment is operated, functional blocks constituting the electronic equipment are first reset to the initial state and then operated normally. Accordingly, each functional block is provided with a signal input terminal for resetting an internal circuit within a certain time after the power source voltage reaches a predetermined level, and, furthermore, a circuit for detecting the build up of the power source voltage is arranged in each functional block to output reset pulses before the power source voltage reaches the predetermined level. An integrated circuit consisting of a capacitor and a resistor is often utilized as a power source voltage buildup detecting circuit of this type.
Recently, with the development of the integrated circuit, this type of power source voltage build up detecting circuit has been built into the integrated circuit, and thus the integrated circuit per se is automatically reset. The technique is generally adopted in microprocessors which are used in various fields, and various modes are considered for the power source voltage buildup detecting circuit. Ordinarily, however, there is adopted a type of mode in which the output of a series circuit consisting of a capacitor, a resistor, and a metal-oxide semiconductor (MOS) transistor is amplified by using an inverter stage.
However, in the above-mentioned circuit, the threshold voltage of the transistor is practically 0.8 V, and therefore the output voltage of the circuit is only 1.6 V at the highest. As a result, the level of the circuit is low, and operation of the functional blocks can not be guaranteed. This is a problem in the conventional technique.
An object of the present invention is to provide a circuit for detecting the buildup of the power source voltage, in which erroneous operation is greatly reduced and normal operation can be guaranteed.
The above-mentioned object can be achieved by providing a source voltage buildup detecting circuit which detects, after the source is switched on, whether the source voltage is higher than the predetermined voltage and which outputs a detecting signal. The source voltage buildup detecting circuit includes a complementary metal-oxide semiconductor (CMOS) inverter, a level shifting element which is connected between the source voltage and the CMOS inverter, and a voltage generating circuit which is connected to an input of the CMOS inverter. The level shifting element supplies a voltage lower than the source voltage to the CMOS inverter as a working voltage. When the source voltage becomes lower than the predetermined voltage after the source voltage is switched on, the voltage generating circuit outputs a voltage higher than the threshold voltage of the CMOS inverter. When the source voltage becomes higher than the predetermined voltage, the voltage generating circuit outputs a voltage lower than the threshold voltage of the CMOS inverter, and, therefore, when the source voltage reaches a predetermined value, the output of the CMOS inverter is inverted.
Further features and advantages of the present invention will be apparent from the ensuing description, made with reference to the accompanying drawings, to which, however, the scope of the invention is in no way limited.
FIG. 1 is a circuit diagram of a conventional circuit for detecting the buildup of the power source voltage;
FIG. 2, including FIGS. 2(a)-2(d); is a timing chart of voltage changes at respective points in the circuit shown in FIG. 1;
FIG. 3 is a circuit diagram of an embodiment of a circuit according to the present invention for detecting the buildup of the power source voltage;
FIG. 4, including FIGS. 4(a)-4(e), is a timing chart of voltage changes at respective points in the circuit shown in FIG. 3;
FIG. 5 is a block diagram of a practical utilization of the present invention;
FIG. 6 is an example of the frequency divider circuit shown in FIG. 5; and
FIG. 7, including FIGS. 7(a)-7(f), is a timing chart of voltage changes at respective points in the circuits shown in FIGS. 5 and 6.
A conventional circuit for detecting the buildup of the power source voltage is shown in FIG. 1. This circuit consists of a series circuit 1 consisting of a capacitor C, a resistor R and an N-channel MOS transistor TR1, an amplifying stage 2 consisting of two CMOS inverter stages, and an output stage 3 having a NOR flip-flop circuit. In FIG. 1, for simplification, a P-channel MOS transistors are indicated by a thick solid line.
The operation of the conventional circuit will now be described with reference to FIG. 2. When the power source voltage Vcc to be applied to the entire system, which includes the circuit of FIG. 1, is gradually elevated, as is shown in FIG. 2(a), buildup of the voltage level at point A through the capacitor, as is shown in FIG. 2(b), results. Also, the voltage at point B is elevated together with the voltage at point A, but the voltage at point B is clamped so that it is equal to the threshold voltage (about 1 V) of the transistor TR1. The CMOS inverter comprises the P-channel transistor TR2 and the N-channel transistor TR3, which have a threshold voltage of Vcc /2. The transistor TR3 is maintained in the on state until the Vcc /2 line reaches the clamped level at points A and B. Then, the transistor TR2 is turned on, and the output at point C contributes to the buildup of the power source voltage Vcc, as is shown in FIG. 2(c). The transistor TR5 is turned on due to the buildup of the output at point C, while the output at point D drops, as is shown in FIG. 2(d).
In the above-mentioned conventional circuit, since the voltage at point A is clamped to about 1 V, the output at point D is 2 V at the highest. Incidentally, since the threshold voltage of the transistor TR4 is practically 0.8 V, the output at point D is only 1.6 V at the highest. Since the level of the output at point D is relatively low, operation of the flip-flop circuit 3 cannot be guaranteed. This is a problem involved in the conventional technique.
This problem can be solved only by elevating the clamped voltage at point A, and elevation of the clamped voltage at point A can only be achieved by increasing the threshold voltage of the transistor TR1. However, since the voltage at point A is retained even after the power source voltage is stabilized, if the voltage at point A is increased, both the P-channel and N-channel transistors of the CMOS inverter are turned on, and, therefore, a direct current flows.
FIG. 3 is a circuit diagram of a circuit according to the present invention for detecting the buildup of the power source voltage. In FIG. 3, the output of the inverter stage 2 can be increased without elevation of the clamped voltage of the series circuit 1 shown in FIG. 1.
In FIG. 3, the same reference numerals as those used in FIG. 1 represent the same members as in FIG. 1. In this embodiment, a P-channel transistor TR16, used as the threshold value element, is connected in series between the P-channel transistor TR2 of the CMOS inverter located in the input stage of the inventer stage 2 and the Vcc terminal. The resistive element formed by the MOS transistors TR14 and TR15 can be used in place of the pure resistor shown in FIG. 1.
The operation of the circuit of this embodiment will now be described with reference to FIG. 4. Due to the buildup of the power source voltage Vcc, the voltage at point A is elevated, as is shown in FIG. 4(a). Due to utilization of the transistor TR16, the voltage between the terminals of the transistors TR2 and TR3 is adjusted to Vcc -Vth, as is shown in FIG. 4(b). Vth represents the threshold voltage (practically 0.8 V) of the transistor TR16. Accordingly, the threshold value of the CMOS inverter of the transistors TR2 and TR16 is (Vcc -Vth)/2, as is shown in FIG. 4(b). Since the voltage at points A and B is maintained at the level clamped by the transistor TR1 (about 1 V), the transistor TR3 is turned on before the voltage intersects the (Vcc -Vth)/2 line, and the output is equal to ground voltage, as is shown in FIG. 4(c). When the value of (Vcc -Vth)/2 is increased beyond the voltage at point B, the transistor TR2 is turned on. By turning on the transistor TR2, the output at point D is reduced from about 3 V (experimentally, 2.6 to 2.4 V) to ground voltage, as is shown in FIG. 4(d).
In the above-mentioned embodiment, the P-channel transistor TR16 is used as the threshold value element, but another threshold value element, such as a diode or a Schottky diode, may be used instead of the transistor TR16. Furthermore, a plurality of threshold value elements may be used. Incidentally, if the output at point D falls after the power source voltage Vcc reaches a predetermined level, there is the risk of elevation of the lower limit of the power source voltage range where the element as a whole can be operated.
When the output at point D is in a conductive state, the transistor TR8 is also in a conductive state, the transistors TR6 and TR7 are in an off state, and a voltage equal to the power source voltage Vcc appears at the output terminal OUT. When a positive pulse is applied to the gate of the transistor TR13, the transistor TR13 is turned on and the output OUT falls to ground state, as is shown in FIG. 4(e).
FIG. 5 is a block diagram of the present invention as a control circuit of a frequency divider circuit. In FIG. 5, the frequency divider circuit 12 divides the output of an oscillator 11, and the divided output is supplied to an internal circuit of an operational portion 13. The circuit 10 of the present invention is used to automatically reset the frequency divider circuit 12 when the power source voltage is switched on.
FIG. 6 is an example of the frequency divider circuit 12 shown in FIG. 5. The circuit shown in FIG. 6 comprises flip-flop circuits FF1, FF2, FF3, FF4, and FF5 which receive clock pulses φ1 and φ2, alternately. The Q outputs of the flip-flop circuits FF2 and FF4 are fed back via a gate G to a D input of the flip-flop circuit FF1. The Q outputs of the flip-flop circuits FF1, FF3 and FF5 are supplied via inverters INV1, INV2 and INV3 to the internal circuit of the operational circuit 13, and the Q output of the flip-flop circuit FF5 is supplied to the input terminal of the circuit 16 shown in FIG. 5. In FIG. 6, it should be noted that the signal corresponding to the potential at point D in FIG. 4(d) is supplied to the flip-flop circuits FF1 to FF5 as a reset signal or a preset signal alternately.
FIG. 7 is a timing chart showing the operation of the circuits shown in FIGS. 5 and 6. In FIG. 7, (a), (b), (c), (e) and (f) correspond respectively to FIG. 4(a), FIG. 4(b), FIG. 4(c), FIG. 4(d) and FIG. 4(e) on a different scale. When the signal shown in FIG. 7(e) is supplied to the frequency divider circuit 12, the initial values of the flip-flop circuits FF1 to FF5 are set, and the flip-flop circuits FF1, FF3 and FF5 supply the outputs Q1, Q2 and Q3 to the internal circuit of the operational portion 13. Also, the output Q3 is supplied to the circuit 10 so as to reset the output shown in FIG. 7(f). The signal shown in FIG. 7(f) is supplied to the operational portion 13 as an internal reset signal.
As is apparent from the foreging description, according to the present invention, since the threshold value element is inserted into the lead of the first inverter stage of the power source voltage buildup detecting circuit, the buildup of the output of the inverter can be delayed, and the output of the second inverter stage can be reduced sharply from the desired relatively high level to ground voltage. Accordingly, the output of the power source voltage buildup detecting circuit can be made more reliable and operation of the circuits of the electronic equipment can be guaranteed.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4013902 *||Aug 6, 1975||Mar 22, 1977||Honeywell Inc.||Initial reset signal generator and low voltage detector|
|US4103187 *||Sep 20, 1976||Jul 25, 1978||Kabushiki Kaisha Suwa Seikosha||Power-on reset semiconductor integrated circuit|
|US4140930 *||Jul 29, 1977||Feb 20, 1979||Sharp Kabushiki Kaisha||Voltage detection circuit composed of at least two MOS transistors|
|US4173756 *||Dec 7, 1977||Nov 6, 1979||Tokyo Shibaura Electric Co., Ltd.||Abnormal voltage detection circuit|
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|US4300065 *||Jul 2, 1979||Nov 10, 1981||Motorola, Inc.||Power on reset circuit|
|US4322639 *||Mar 14, 1978||Mar 30, 1982||Hitachi, Ltd.||Voltage detection circuit|
|US4405871 *||May 1, 1980||Sep 20, 1983||National Semiconductor Corporation||CMOS Reset circuit|
|US4409501 *||Jul 20, 1981||Oct 11, 1983||Motorola Inc.||Power-on reset circuit|
|DE2600197A1 *||Jan 5, 1976||Jul 8, 1976||Hitachi Ltd||Einschaltsetzschaltung|
|GB2059707A *||Title not available|
|JPS5460849A *||Title not available|
|1||*||Patents Abstracts of Japan, vol. 3, No. 82, Jul. 14, 1979, p. 75 E 123 & JP A 54 60849 (Fujitsu K.K.), 16 05 1979, Abstract; figure.|
|2||Patents Abstracts of Japan, vol. 3, No. 82, Jul. 14, 1979, p. 75 E 123 & JP-A-54 60849 (Fujitsu K.K.), 16-05-1979, Abstract; figure.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4633107 *||Nov 20, 1984||Dec 30, 1986||Harris Corporation||CMOS power-up reset circuit for gate arrays and standard cells|
|US4634904 *||Apr 3, 1985||Jan 6, 1987||Lsi Logic Corporation||CMOS power-on reset circuit|
|US4670676 *||Jan 15, 1985||Jun 2, 1987||Mitsubishi Denki Kabushiki Kaisha||Reset circuit|
|US4746822 *||Mar 20, 1986||May 24, 1988||Xilinx, Inc.||CMOS power-on reset circuit|
|US4985641 *||Feb 24, 1989||Jan 15, 1991||Mitsubishi Denki Kabushiki Kaisha||Semiconductor integrated circuit device having selectable operational functions|
|US5030845 *||Oct 2, 1989||Jul 9, 1991||Texas Instruments Incorporated||Power-up pulse generator circuit|
|US5055706 *||Feb 17, 1989||Oct 8, 1991||Kabushiki Kaisha Toshiba||Delay circuit that resets after pulse-like noise|
|US5065045 *||Oct 4, 1990||Nov 12, 1991||Atmel Corporation||Multistage offset-cancelled voltage comparator|
|US5111067 *||Apr 29, 1991||May 5, 1992||Intel Corporation||Power up reset circuit|
|US5323067 *||Apr 14, 1993||Jun 21, 1994||National Semiconductor Corporation||Self-disabling power-up detection circuit|
|US5446403 *||Feb 4, 1994||Aug 29, 1995||Zenith Data Systems Corporation||Power on reset signal circuit with clock inhibit and delayed reset|
|US5467039 *||Jul 6, 1994||Nov 14, 1995||Samsung Electronics Co., Ltd.||Chip initialization signal generating circuit|
|US5508649 *||Jul 21, 1994||Apr 16, 1996||National Semiconductor Corporation||Voltage level triggered ESD protection circuit|
|US5801561 *||Apr 21, 1997||Sep 1, 1998||Intel Corporation||Power-on initializing circuit|
|US6744291||Aug 30, 2002||Jun 1, 2004||Atmel Corporation||Power-on reset circuit|
|DE10121649B4 *||May 4, 2001||Apr 29, 2010||Fujitsu Ltd., Kawasaki||Auswahlsignal-Erzeugungsschaltung mit einer Klemmschaltung zum Klemmen von Auswahlsignalen beim Einschalten|
|EP0631389A2 *||Jun 24, 1994||Dec 28, 1994||Sony Corporation||Power-on reset circuit|
|WO1986005933A1 *||Jan 23, 1986||Oct 9, 1986||Lsi Logic Corporation||Cmos power-on reset circuit|
|U.S. Classification||327/77, 327/143, 327/142|
|International Classification||H03K17/22, G06F1/24, G01R19/165|
|Cooperative Classification||G06F1/24, H03K17/223, G01R19/16519|
|European Classification||H03K17/22B, G01R19/165E4, G06F1/24|
|Feb 16, 1983||AS||Assignment|
Owner name: FUJITSU LIMITED 1015, KAMIKODANAKA, NAKAHARA-KU, K
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:NAKAMORI, TUTOMU;REEL/FRAME:004098/0161
Effective date: 19830205
|Apr 1, 1986||CC||Certificate of correction|
|Apr 4, 1989||FPAY||Fee payment|
Year of fee payment: 4
|Jun 3, 1993||FPAY||Fee payment|
Year of fee payment: 8
|Jul 15, 1997||REMI||Maintenance fee reminder mailed|
|Dec 7, 1997||LAPS||Lapse for failure to pay maintenance fees|
|Feb 17, 1998||FP||Expired due to failure to pay maintenance fee|
Effective date: 19971210