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Publication numberUS4628218 A
Publication typeGrant
Application numberUS 06/463,420
Publication dateDec 9, 1986
Filing dateFeb 3, 1983
Priority dateFeb 3, 1982
Fee statusPaid
Also published asDE3364806D1, EP0086090A1, EP0086090B1
Publication number06463420, 463420, US 4628218 A, US 4628218A, US-A-4628218, US4628218 A, US4628218A
InventorsKazuo Nakaizumi
Original AssigneeNippon Electric Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Driving circuit suppressing peak value of charging current from power supply to capacitive load
US 4628218 A
Abstract
A buffer circuit, which supplies current to a capacitive load, has a first circuit for reducing the power supply charging current to the capacitive load during switching intervals. The first circuit includes a charge storage device precharged between inverter switching intervals to produce at least a portion of the load charging current during the switching intervals. A second circuit includes a switching element connected between the power supply and the capacitive load to electrically connect the power supply through the second circuit to the load at a selected time in the switching interval to supplement the charging current produced by the charge storage device.
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Claims(11)
What is claimed is:
1. An inverter circuit comprising a first field effect transistor of one conductivity type, a second field effect transistor of the opposite conductivity type connected with said first transistor in series between two terminals of a power supply, an input terminal coupled to the gates of said first and second transistors, an output terminal coupled to the connection point of said first and second transistors, a capacitive load coupled to said output terminal, a capacitor, first means coupled to said capacitor and to one of said two terminals of the power supply for charging said capacitor at a time other than a transient time when a potential at said output terminal transfers from a first level to a second level, and a second means coupled to said capacitor and said capacitive load for charging said capacitive load with a discharging current from said capacitor during said transient time.
2. The inverter of claim 1, further comprising a third means coupled to said one terminal of the power supply and said capacitive load for charging said capacitive load with a current from said power supply during said transient time after the discharging current from said capacitor starts to flow.
3. An inverter as claimed in claim 1, in which said first means includes a first switch transistor connected between said one terminal of the power supply and said capacitor and said second means includes a second and a third switch transistors connected in series between a connection point of said first switch transistor and said capacitor and said capacitive load, said second switch transistor being controlled by the voltage at said output terminal, and said third switch transistor being controlled by an input signal at said input terminal.
4. An inverter as claimed in claim 2, in which said third means includes a delay circuit for delaying an input signal at said input terminal and a fourth switch transistor connected between said one terminal of the power supply and said output terminal.
5. An inverter comprising an inverter circuit responsive to an input signal for producing an output signal that is inverted relative to the input signal, a first auxiliary circuit and a second auxiliary circuit connected in parallel between an output terminal of said inverter circuit and a power supply, respectively, said first auxiliary circuit including an auxiliary capacitor and including means to discharge electric charge stored in said auxiliary capacitor during a transient period where the output of the inverter goes from a "0" level to a "1" level, said second auxiliary circuit including means for applying a current to the output terminal of said inverter circuit in a predetermined period during said transient period.
6. An inverter as claimed in claim 5, in which said inverter circuit includes a first P-channel type field effect transistor and a first N-channel type field effect transistor connected in series and inserted between the power supply and a circuit ground terminal, the gates of said two transistors being connected in common to form an input terminal, a common junction point between said two transistors being coupled to an output terminal, said first auxiliary circuit including second, third and fourth P-channel type field effect transistors connected in series with each other and having their gates connected to the ground terminal, said output terminal and said input terminal, respectively, and an auxiliary capacitor inserted between the common junction point of said second and third P-channel type field effect transistor and the ground terminal, said second auxiliary circuit including a delay circuit and a fifth P-channel type field effect transistor having its gate connected through the delay circuit to said input terminal.
7. An inverter as claimed in claim 6, in which said second auxiliary circuit includes a sixth P-channel type field effect transistor inserted between said fifth P-channel type field effect transistor and said output terminal and having its gate connected to said input terminal.
8. In an inverter circuit for applying an output signal to a load, first means responsive to an input signal for applying a first charging current to said load during selected switching intervals of said inverter circuit, a charge storage device, and second means responsive to said input signal for charging said charge storage device between said switching intervals of said inverter circuit and for causing said charge storage device to discharge into said load during said selected inverter circuit switching intervals.
9. In the inverter circuit of claim 8, further including a third means for applying a second charging current to said load during selected periods within inverter switching intervals, said third means including a delay circuit responsive to said input signal and a switching means responsive to said delay circuit for applying said second charging current a predetermined time after the input signal begins to switch from a first level causing said output signal to assume a relatively low voltage state to a second level causing said output signal to assume a relatively high voltage state.
10. A circuit for driving a capacitive load, comprising first means responsive to an input signal for charging and discharging said capacitive load, a capacitor, second means coupled between said capacitor and a power supply terminal for charging said capacitor before said first means charges said capacitive load, and third means coupled between said capacitor and said capacitive load for charging said capacitive load by a discharge current from said capacitor when said first means charges said capacitive load.
11. The circuit as claimed in claim 10, further comprising fourth means coupled between said power supply terminal and said capacitive load for charging said capacitive load after said discharge current from said capacitor starts to flow.
Description
BACKGROUND OF THE INVENTION

The present invention relates to an inverter or switching circuit making use of complementary insulated gate field effect transistors (hereinafter abbreviated as CMOSFET's). More particularly, it relates to an inverter circuit with a capacitive load connected to the output terminal thereof in which a heavy transient current flows from a power supply under a transient condition where an input signal is changed to invert the inverter output.

Since an inverter circuit using CMOSFET's (hereinafter abbreviated as CMOS inverter) consumes little power in the steady state condition, its use in large-scale integrated circuits (thereinafter abbreviated as IC) is desirable. Under the transient condition, however, a considerably large power supply current (hereinafter abbreviated as IDD) flows through the CMOS inverter due to a charging current flowing to a capacitive component of the load. Accordingly, the peak value of IDD in the CMOS inverter is large during the transient period. Therefore, it is necessary to take measures, such as lowering the impedance of power supply wirings to the CMOS inverter to reduce this transient current. But such a measure would deteriorate a valuable feature of the CMOS circuit; namely, that it can use fine wirings because of the low steady state power consumption. This problem becomes more remarkable in a memory IC where a large number of address inverters operate simultaneously. For instance, in a 64K-bit memory, an address input is 16-bits, which means that at least 16 address inverters operate simultaneously in response to 16 address input signals applied in parallel. In that case, IDD is multiplied by a factor of 16, causing an extremely large peak current to flow from the power supply of this memory IC. Consequently, a noise is generated in the power supply lines, causing many faults in the operation of the memory IC.

It has been proposed to reduce the peak current by prolonging the CMOS inverter switching time to thereby gradually charge the load capacitance. However, this method has a drawback that speed-up of the whole IC is prevented because of the prolonged response time of the inverter.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an inverter circuit, in which the peak value of the load capacitance charging current component of the power supply current can be largely reduced while maintaining high-speed operation.

According to one feature of the present invention, there is provided an inverter circuit responsive to an input signal for outputting an inverted signal of the input signal, with a first auxiliary circuit connected to the inverter circuit. The first auxiliary circuit includes an auxiliary capacitor which is charged at a time other than the transient time when the output transfers from the low level to the high level (e.g. when the input signal is "1" (or "0") level), and is discharged during the transient period when the input signal is changed from the low level to the high level. Since the discharge current from the auxiliary capacitor is added to the power supply current from the power supply for charging the capacitive load in the transient period, the peak power supply current during the transient period can be greatly reduced. The power supply current for charging the auxiliary capacitor flows at a time other than the transient period and contributes to the reduced peak current.

According to another feature of the invention, a second auxiliary circuit is added to the inverter circuit in parallel with the first auxiliary circuit to feed a part of the output current of the inverter circuit at least after the discharging current from the auxiliary capacitor starts to flow and favorably after the mentioned discharging current ends during the transient period.

The inverter circuit may comprise a first P-channel type field effect transistor (hereinafter abbreviated as Pch-FET) and a first N-channel type field effect transistor (hereinafter abbreviated as Nch-FET) connected in series between the two power supply terminals, the gates of these FET's being commonly connected to an input terminal, and the common junction point therebetween being used as an output terminal. The first auxiliary circuit may include second, third and fourth Pch-FET's (or Nch-FET's) connected in series between one of the power supply terminals and the output terminal of the inverter circuit with their respective gates connected to the other power supply terminal, the output terminal of the inverter circuit and the input terminal of the inverter circuit, respectively. An auxiliary capacitor is inserted between the common junction point between the second and third FET's and the other power supply terminal. The second auxiliary circuit may include a fifth Pch-FET (or Nch-FET) inserted between the one of the power supply terminals and the output terminal of the inverter circuit and a delay circuit coupled between the input terminal of the inverter circuit and the gate of the fifth FET. The second auxiliary circuit may further include a sixth Pch-FET (or Nch-FET) inserted between the drain of the fifth FET and the output terminal of the inverter circuit and having its gate connected to the input terminal of the inverter circuit. With the first and second auxiliary circuits, the inverter circuit according to this invention can reduce the peak value of the capacitive load charging current component of the power supply current as compared to the prior art inverter circuit, while maintaining a high-speed operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a basic inverter circuit in the prior art making use of CMOSFET's.

FIG. 2 illustrates the waveforms of an input signal φIN, an output signal φOUT, and a charging current component IDDL of the power supply current IDD as functions of time for the inverter circuit shown in FIG. 1,

FIG. 3 is a circuit diagram showing one preferred embodiment of the present invention,

FIG. 4 illustrates the waveforms of the input voltage φIN the output voltage φOUT and the charging current component IDDL of the power supply current as functions of time as the inverter circuit of FIG. 3 goes from the "1" level to "0" level.

FIG. 5 illustrates the waveforms of the input voltage φIN, the output voltage φOUT and the charging current components of the power supply current as functions of time as the inverter circuits of FIGS. 3 and 6 are changed from "0" level to "1" level.

FIG. 6 is a circuit diagram showing another preferred embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to FIG. 1, a prior art inverter circuit comprises an Nch-FET Q1 and a Pch-FET Q2 with their drains connected in common to form an output terminal 3. The source of the FET Q1 is connected to a VSS power supply terminal (in the illustrated example, to the ground terminal) and the source of the FET Q2 is connected to a VDD power supply terminal 4 (in the illustrated example, VDD represents a positive voltage). The gates of both FET's are connected in common and form an input terminal 2. It is to be noted that a load capacitor CL is present between the output terminal 3 and the ground terminal.

Referring also to FIG. 2, when the input signal φIN is at "1" level (in the illustrated example, a high voltage VDD level) at a time to, the Nch-FET Q1 is ON, and hence the output signal φOUT maintains "0" level (VSS level). Since the Pch-FET Q2 is OFF at this time, the power supply current IDD does not flow. Subsequently, the input signal φIN begins to transfer from the "1" level to the "0" level (in the illustrated example the low voltage VSS is the 0 volt level), and when the voltage of the input signal has lowered to VDD -|VTP | (VTP : a threshold voltage of the Pch-FET Q2) at a time t1, the Pch-FET Q2 is turned ON and a power supply current IDD begins to flow. As a result, the voltage of the output signal φOUT begins to rise, determined by the capability ratio between the Nch-FET Q1 and the Pch-FET Q2. As the voltage of the output signal φOUT rises, the load capacitor CL is driven, and a charging current IDDL flows from the VDD power supply terminal through the Pch-FET Q2 into the load capacitor CL. Therefore, the power supply current IDD which is the sum of the charging current IDDL and a current IDDO flowing through the FET Q1 to the ground becomes large. Then, the input signal φIN approaches the "0" level, and when the voltage reaches VTN (a threshold voltage of the Nch-FET Q1), the Nch-FET Q1 is turned OFF, and the power supply current component flowing through the Nch-FET Q1 (IDDO) stops. When the input signal φIN reaches "0" level at a time t2, the output signal φOUT also reaches "1" level, so that the IDDL also stops flowing. Thus the charging current component IDDL has a nearly symmetric waveform with a large peak value. The peak value of the charging current IDDL become larger as the load capacitor CL is increased. As described previously, an important problem to be solved is how best to reduce the peak value of this IDDL.

With reference to FIG. 3, the circuit of a preferred embodiment of the present invention comprises a basic inverter circuit 11 which includes a first Pch-FET Q12 and a first Nch-FET Q11 connected in series at an output terminal 17. The source of the Nch-FET Q11 is connected to VSS terminal (the ground terminal in this example) and the source of the Pch-FET Q12 is connected to a VDD power supply terminal 16. The gates of the Nch-FET Q11 and the Pch-FET Q12 are both connected to an input terminal 15. A first auxiliary circuit 12 is added to the inverter circuit 11, which in turn includes second, third and fourth Pch-FET's Q14, Q15 and Q16 connected in series between the VDD power supply terminal 16 and the output terminal 17. The respective gates of Q14, Q15 and Q16 are connected to the input terminal 15, the output terminal 17, and the ground terminal, respectively. The first auxiliary circuit further includes an auxiliary capacitor CA inserted between the common junction point N2 of the Pch-FET's Q15 and Q16 and the ground terminal. A second auxiliary circuit 13 is also added, which includes a fifth Pch-FET Q13 inserted between the VDD power supply terminal 16 and the output terminal 17 and a delay circuit 14 inserted between the input terminal 15 and the gate of Q13. The delay circuit 14 is used to delay the input signal φIN by a predetermined period. Since precision is not required, the delay circuit 14 can be easily constructed using known techniques.

Now description will be made of the operation of this circuit when the input signal φIN transfers from "1" level (VDD) to the "0" level (ground), with reference to FIG. 4. Since the basic inverter circuit 11 has the same construction as the circuit in the prior art shown in FIG. 1, its operation is basically the same as that of the prior art circuit.

At first, when the input signal φIN is at the "1" level (VDD) at a time between to and t11, the Pch-FET's Q15 and Q16 of the first auxiliary circuit 12 are ON and the Pch-FET Q14 is OFF. Hence the auxiliary capacitor CA is charged via the Pch-FET Q16 by VDD and stores electric charge therein. Accordingly, the charging current IDDA for this capacitor CA flows from the VDD power supply terminal 16 as a component of the power supply current IDD, during the period of time to to t11. At this moment, the Nch-FET Q11 is ON and the Pch-FET's Q12 and Q13 are OFF. Therefore, the output voltage φOUT at the output terminal 17 is at the "0" level, and the power supply current IDDO through the Nch-FET Q11 and the charging current IDDL for the load capacitor CL are both zero.

Within the period of t0 to t11, the input signal φIN starts to fall. When the voltage of the input signal φIN is lowered to VDD -|VTP | at the time t11, the Pch-FET Q12 and the Pch-FET Q14 are turned ON, and hence a current IDDO through the Pch-FET Q12 and the Nch-FET Q11 and a charging current IDDL1 through the Pch-FET Q12 and load capacitor CL for charging the load capacitor CL begin to flow. Furthermore, the electric charge previously stored in the auxiliary capacitor CA begins to discharge as a part of the charging current for the load capacitor CL through the Pch-FET Q14 (this component being represented by IDDL2). Since this discharge current IDDL2 is based on the discharge of electric charge that has been preliminarily stored in the auxiliary element CA, an increment of the power supply current IDD that is necessary for I.sub. DDL2 after the time t11 is very small. If the conductance of the Pch-FET Q16 is chosen less than about 1/10 of that of the Pch-FET Q12, then the IDD component passing through the Pch-FET Q16 is very small, and therefore it can be neglected. Moreover, if the auxiliary capacitor CA is chosen nearly the same size as the load capacitor CL, then about one-half of the charging current IDDL can be obtained from IDDL2.

Subsequently, the voltage of the input signal φIN is further lowered after t11 and accordingly the voltage of the output signal φOUT rises, and when the output voltage value reaches about VDD /2 at a time t12, the input signal φ'IN delayed by the delay circuit 14 in the second auxiliary circuit is applied to the Pch-FET Q13, so that the Pch-FET Q13 is turned ON and sends out an output current to the output terminal 17 which forms another part of the charging current for the load capacitor CL (this component being called IDDL3). As a result the power supply current IDD now includes the IDDL3 component. On the other hand, the potential at the node N2 which serves as one terminal of the auxiliary capacitor CA becomes nearly the same level as the φOUT when the voltage of the output signal φout exceeds VDD /2, and hence the Pch-FET Q15 is turned OFF, so that the charging current IDDL2 from the auxiliary capacitor CA is eliminated. Therefore, at this time the charging current for the load capacitor CL is comprised of two components; that is, the IDDL1 passing through the Pch-FET Q12 and the IDDL3 passing through the Pch-FET Q13. This IDDL3 component compensates for the loss of the above-described IDDL2 component to promote charging of the load capacitor CL and serves to quickly raise the voltage of the output signal φOUT. Therefore, it is favorable to select the conductance of the Pch-FET Q13 larger than that of the Pch-FET Q12.

Next, when the input signal φIN approaches the "0" level and its voltage becomes equal to or lower than VTN, then the Nch-FET Q11 is turned OFF, and hence the IDDO component passing through the Nch-FET stops. Then, the input signal φIN reaches the "0" level and the output signal φOUT reaches the "1" level at a time t13, and as a result, the IDDL1 component passing through the Pch-FET Q12 as well as the IDDL3 component passing through the Pch-FET Q13 are also eliminated.

As will be apparent from the above description, in the circuit of the illustrated embodiment, the charging current IDDL for the load capacitor CL is formed in such a manner that until the voltage of the output signal φOUT becomes nearly equal to VDD /2, the charging current is comprised of the IDDL1 passing through the Pch-FET Q12 and the discharging current IDDL2 of the auxiliary capacitor CA which has been preliminarily charged, and after the output signal φOUT nearly exceeds VDD /2, the IDDL2 is eliminated and instead the IDD3 passing through the Pch-FET Q13 is newly added. Consequently, the load capacitor charging current component IDDL of the power supply current of the circuit would flow over the entire region of operation, and its peak value during the period t11 to t13 becomes very small as shown in FIG. 4. The extent of this reduction of the peak value depends upon the design of the first and second auxiliary circuits such as the magnitude of the auxiliary capacitor CA and the conductance of the Pch-FET Q13. However, it is quite easy to reduce the peak value of the charging current to 1/2 or less of the peak value in the prior art inverter circuit.

Furthermore, since those auxiliary charging currents can be subjected to appropriate adjustment by varying the delay characteristics of the delay circuit 14 in the second auxiliary circuit 13 so as to meet the response time of the circuit, there is no need to prolong a response time of the inverter circuit 11, and the response time may be rather shortened by selecting appropriate timing.

Now description will be made of the case where the input signal transfers from the "0" level to the "1" level, with reference to FIG. 5 which shows waveforms of the input signal φIN, the output signal φOUT and the power supply current IDD for this case.

At first, during the period t0 to t20, when the input signal φIN is at the "0" level (ground), the Pch-FET's Q12, Q13, Q14 and Q16 are ON and the Nch-FET Q11 and the Pch-FET Q15 are OFF. Accordingly, the auxiliary capacitor CA is charged, and a power supply charging current IDDA flows.

Next, the input signal φIN starts to rise at a time t20. When it rises up to VTN at a time t21, the Nch-FET Q11 is turned ON and the discharging current of the load capacitor CL begins to flow through the Nch-FET Q11. Furthermore the power supply current IDDO flows through the Pch-FET Q12 and the Nch-FET Q11, and the power supply current IDDO ' flows through the Pch-FET Q13 and the Nch-FET Q11. At this moment, since the Pch-FET Q15 is kept OFF, only the IDDA flows through the first auxiliary circuit.

Subsequently, when the input signal φIN reaches VDD -|VTP |, at a time t23, the Pch-FET Q13 is turned OFF and the IDDO stops flowing, but since the voltage of the delayed signal φIN for the input signal φIN which is a driving voltage for the Pch-FET Q13 does not rise as shown in FIG. 5, the Pch-FET Q13 is still kept ON, and so the IDDO ' continues to flow. Thereafter when the φ'IN becomes VDD -VTP at a time t24, the Pch-FET Q13 is turned OFF and the IDDO ' stops flowing. The input signal φIN reaches the "1" level, and the output signal φOUT reaches the "0" level.

In other words, in the transient period when the input signal φIN transfers from the "0" level to the "1" level, the IDDO ' passing through the Pch-FET Q13 is added to the power supply current IDDO which flows together with the discharge current of the load capacitor CL in the circuit known in the prior art, and therefore, the overall power supply current I'DD takes the form shown in FIG. 5. As described, the circuit of the illustrated embodiment of FIG. 3 has a problem that although the peak value of the load capacitor charging current component IDDL of the power supply current IDD can be greatly reduced when the input signal φIN transfers from the "1" level to the "0" level, the power supply current IDDO ' caused by the second auxiliary circuit is added to the power supply current when the input signal φIN transfers from the "0" level to the "1" level.

The circuit of another preferred embodiment of the present invention shown in FIG. 6 solves the above-mentioned problem. The only difference from the circuit shown in FIG. 3 and described previously resides in that the second auxiliary circuit 13' includes another Pch-FET Q17 inserted between the drain of the Pch-FET Q13 and the output terminal 17 and having its gate connected to the input terminal 15. In this circuit of the modified embodiment, the Pch-FET Q17 is turned OFF in response to the input signal φIN and the IDDO ' also ceases to flow at the same time when IDDO ceases to flow through Q12. Therefore, the IDD in this modified embodiment becomes small as indicated by I"DD in FIG. 5.

It is to be noted that in the above-described embodiments, the conductivity type of the respective FET's can be changed if necessary. For instance, in place of the Pch-FET an Nch-FET can be used for the FET Q14, and an inverted input signal φIN would then be applied to the gate of this FET. The Pch-FET's and Nch-FET's may be replaced by Nch-FET's and Pch-FET's, respectively, with the terminals of the power supply voltage being reversely connected.

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US4682047 *Aug 18, 1986Jul 21, 1987Siemens AktiengesellschaftComplementary metal-oxide-semiconductor input circuit
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Classifications
U.S. Classification326/33, 326/98, 326/87
International ClassificationH03K19/0185, H03K19/017, H03K17/12, H03K19/0948, H03K17/687, H03K5/02, G11C8/08, H03K19/003, H03K19/0944, H03K17/16
Cooperative ClassificationG11C8/08, H03K19/00315, H03K19/01721, H03K5/023
European ClassificationH03K19/017B2, G11C8/08, H03K5/02B, H03K19/003C
Legal Events
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Feb 25, 2003ASAssignment
Owner name: NEC ELECTRONICS CORPORATION, JAPAN
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Effective date: 20021101
Jun 8, 1998FPAYFee payment
Year of fee payment: 12
Jan 24, 1994FPAYFee payment
Year of fee payment: 8
May 9, 1990FPAYFee payment
Year of fee payment: 4
Apr 21, 1987CCCertificate of correction
Jul 23, 1986ASAssignment
Owner name: NIPPON ELECTRIC CO., LTD., 33-1, SHIBA GOCHOME, MI
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:NAKAIZUMI, KAZUO;REEL/FRAME:004580/0506
Effective date: 19830202
Owner name: NIPPON ELECTRIC CO., LTD.,JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NAKAIZUMI, KAZUO;REEL/FRAME:004580/0506