|Publication number||US4628442 A|
|Application number||US 06/808,665|
|Publication date||Dec 9, 1986|
|Filing date||Sep 22, 1982|
|Priority date||Sep 22, 1981|
|Also published as||DE3280023D1, EP0088804A1, EP0088804A4, EP0088804B1, WO1983001129A1|
|Publication number||06808665, 808665, PCT/1982/379, PCT/JP/1982/000379, PCT/JP/1982/00379, PCT/JP/82/000379, PCT/JP/82/00379, PCT/JP1982/000379, PCT/JP1982/00379, PCT/JP1982000379, PCT/JP198200379, PCT/JP82/000379, PCT/JP82/00379, PCT/JP82000379, PCT/JP8200379, US 4628442 A, US 4628442A, US-A-4628442, US4628442 A, US4628442A|
|Inventors||Shinichi Isobe, Kazuo Sawada|
|Original Assignee||Fanuc Ltd|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (20), Referenced by (9), Classifications (10), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of co-pending application Ser. No. 499,163 filed on May 18, 1983 and now abandoned.
1. Technical Field
This invention relates to a numerical control apparatus and, more particularly, to a numerical control apparatus well-suited for application to a numerical control system in which a numerical control apparatus and a machine tool are united into a mechanical-electronics arrangement.
2. Background Art
A computerized numerical control apparatus includes a numerical control unit comprising a microprocessor or the like and is connected to various input/output units by a data bus. FIG. 1 is a block diagram of such a numerical control apparatus. In the drawing, numeral 11 denotes a numerical control unit including a read/write data memory (RAM) 11a for storing machining program data and the results of processing, a read-only memory (ROM) 11b for storing a control program which controls all numerical control processing, a processor 11c for executing various kinds of processing such as processing for sensing and receiving signals, a pulse distributor 11d which receives a position command as an input and produces distributed pulses by performing known pulse distribution computations, and a servo circuit 11e for controlling the rotation of a motor. Numeral 12 designates a bus line having an address bus for transferring address signals and a data bus for transferring data. Numeral 13 denotes a paper tape reader for reading machining program data punched in a paper tape that is to be stored in the data memory 11a. Numeral 14 denotes a paper tape puncher for recording the machining program data by punching the data, stored in the data memory 11a, into a paper tape serving as an external storage medium. It should be noted that a magnetic cassette tape device and magnetic bubble cassete device may be connected to the unit in place of the date reader 13 and tape puncher 14. Numeral 15 designates a power magnetics circuit (data input/output circuit) for sending and receiving data between a machine tool and the numerical control unit. Specifically, the power magnetics circuit 15 delivers signals indicative of M-, S- and T-function instructions and the like from the numerical control unit 11 to a machine 19. This circuit also supplies the numerical control unit with various limit switch signals, relay contact signals and operation completion signals concerning the M-, S- and T-function instructions that are received from the machine 19. Numeral 16 represents a manual data input unit (MDI unit) equipped with a CRT. The MDI unit 16 allows manual entry of single blocks of machining data, and also permits correcting a machining program, partial deletion of and addition to the machining program, and other functions. Numeral 17 designates an operator's pendant provided with various switches and buttons such as a cycle start button, a mode selection switch, a jog feed button and a zero-point return button. Numeral 18 is a manual pulse generator for generating pulses in response to a manual operation. As shown in FIG. 2, an arrangement is also possible wherein the MDI unit 16 and operator's pendant 17 are connected to the bus line 12 through the power magnetics circuit (data input/output circuit) 15.
The numerical control unit 11 controls the machine tool by executing numerical control processing under the control of the control program on the basis of the machining program data stored in the data memory 11a. Simultaneously with the numerical control processing, the numerical control unit 11 monitors the status of the machine tool (such as the on/off state of various limit switches) received via the power magnetics circuit; monitors the state of the switches and buttons on the operator's pendant; and performs processing in accordance with the status of the machine tool and the states established by the operator's pendant. The reading of, e.g., data and operating states from the various devices 13 through 18 connected to the bus line 12, or the outputting of data to each of these devices is initiated by an interrupt or by applying address signals to an address bus to successively identify the devices and to read the data from or place the data on the data bus.
Recent systems use a so-called mechanical-electronics construction wherein a numerical control apparatus and machine are unified. In such a mechanical-electronics system, the numerical control unit 11 is located at the back of the machine tool 19 while the data input/output units such as the tape reader 13 and tape puncher 14, as well as the operator-manipulated devices such as the MDI unit 16, operator's pendant 17 and manual pulse generator 18, are located at an easily accessible location remote from the numerical control unit 11. Accordingly, if the arrangement of FIG. 1 or FIG. 2 is employed without making any change in the numerical control apparatus of the mechanical-electronics system, the various devices must be connected to the numerical control unit 11 by connecting cables of considerable length. This complicates the system, and results in higher cost and in misconnections.
Accordingly, an object of the present invention is to provide a numerical control apparatus wherein connecting cables can be reduced even in a mechanical-electronics system, and wherein it is possible to achieve remote control with excellent operability and to lighten the processing burden of the numerical control unit.
To achieve this and other objects, the present invention includes a numerical control apparatus comprising a numerical control unit; a data input/output circuit for sending and receiving data between a machine and the numerical control unit; a data input unit such as a tape reader for entering NC data; a manual data input unit for manually entering NC data; and an operator's pendant, wherein there is provided a local control circuit, separate from the numerical control unit, for centrally controlling the data input unit, the manual data input unit and the operator's pendant, etc. The local control circuit is connected to the numerical control unit directly through a data transfer line, or through the data input/output circuit.
With the numerical control apparatus of the present invention, connecting cables can be markedly reduced in a mechanical-electronics system even when the numerical control unit is remote from each of the operator-manipulated devices. This simplifies the system arrangement and prevents the occurrence of misconnections. Further, since each of the operator-manipulated devices is controlled by the local control circuit, the numerical control unit need only exchange data with a power magnetics circuit or with the power magnetics circuit and the local control circuit, thereby lightening the processing burden of the numerical control unit. Since the operator-manipulated devices are collected together at a single location in accordance with the present invention, the operator can perform his tasks with greater efficiency and remote control can be performed with facility.
FIGS. 1 and 2 illustrate arrangements of a conventional numerical control apparatus;
FIG. 3 shows an arrangement of a numerical control apparatus according to the present invention; and
FIG. 4 is a block diagram of an essential portion of the arrangement of FIG. 3.
An embodiment of the present invention is described with reference to the drawings.
FIG. 3 is a block diagram illustrating one embodiment of the present invention. Portions similar to those shown in FIG. 1 are designated by like reference characters. In FIG. 3, numeral 101 denotes a local control circuit connected to the tape reader 13, the tape puncher 14, the MDI unit 16 including a CRT, the operator's pendant 17 and the manual pulse generator 18. The control circuit 101 is connected to the numerical control unit 11 through the power magnetics circuit 15, or directly to an interface circuit 11f of the numerical control unit 11 without the intermediary of the power magnetics circuit 15, as indicated by the dashed line. Numeral 11g denotes a direct memory access controllor (referred to as a DMAC).
FIG. 4 is a block diagram showing an essential portion of FIG. 3. This illustrates the case where the numerical control unit 11 and local control circuit 101 are interconnected directly without using the power magnetics circuit 15.
In the interface circuit 11f, SFR1 represents a shift register capable of both parallel and serial writing and reading. GT denotes a gate circuit for controlling the writing of data into the shift register SFR1 and the reading of data out of SFR1. TRCN represents a transmission control circuit for generating block pulses CLK and a synchronizing signal SYNC when a serial data transfer takes place. The transmission control circuit TRCN receives an address signal from the address bus AB1 and responds by generating a gate signal GS for controlling the status of the gate circuit GT.
In the local control circuit 101, TRCC represents a transmission control circuit, and SFR2 denotes a shift register capable of both parallel and serial writing and reading of data, similar to the shift register SFR1. BTC denotes a bit counter having a capacity equivalent to the number of bits (e.g., eight) in one item of parallel data. The bit counter BTC counts the clock pulses CLK received from the numerical control unit 11 and generates a single carry pulse CP when eight clock pulses CLK have arrived, namely in response to transmission of eight bits of data. ADC represents an address counter for generating an address signal. The address counter ADC counts the carry pulses CP and transmits the counted value as an address signal on an address bus AB2. RV1 through RVm denote receivers and DV1 through DVn represent drivers, these being connected to the tape reader 13, tape puncher 14, MDI unit 16, operator's pendant 17 and manual pulse generator 18. L1 through Ln designate latch circuits, and DSL1, DSL2 represent data selectors for reading data and for transmitting data, respectively. The data selector DSL1 reads data from eight of the receivers in accordance with an address received from the address counter ADC via the address bus AB2, and delivers the data to a data bus DB2. For example, let receivers RV1 through RV8 correspond to an i-th address and let receivers RV9 through RV16 correspond to an (i+1)-th address. Then, when an address i is transmitted on the address bus AB2, data received by RV1 through RV8 is delivered to the data bus DB2. When an address (i+1) is transmitted on the address bus AB2, data received by RV9 through RV16 is delivered to the data bus DB2. This operation proceeds in the manner described to read the data. The data selector DSL2 stores the data on the data bus DB2 in eight of the latch circuits in accordance with an address received on the address bus AB2 from the address counter ADC. For example, let latch circuits R1 through L8 correspond to a j-th address and let latch circuits L9 through L16 correspond to a (j+1)-th address. Then, when an address j is transmitted on the address bus AB2, the data on the data bus DB2 is stored in the latch circuits L1 through L8. When an address (j+i) is transmitted on the address bus AB2, the data on the data bus DB2 is stored in the latch circuits L9 through L16.
The following describes a sequence of data transfers to first, second and subsequent addresses. The data being sent from the numerical control unit 11; latch circuits L1 through L8 correspond to the first address, latch circuits L9 through L16 correspond to the second address, and so on.
First, prior to a direct memory access operation, which is performed by the direct memory access controller 11g, the transmission control circuit TRCN of the numerical control unit 11 generates the synchronizing signal SYNC which is transmitted to the local control circuit 101 through a cable LN2. The synchronizing signal SYNC is applied to the address counter ADC and to the bit counter BTC to clear the contents thereof. Thereafter, the direct memory access controller 11g responds to a command from the processor 11c by starting a direct memory access operation to transfer data. When a transfer command for reading N-bytes of data from a prescribed address of the data memory 11a (FIG. 3) and for transferring the data is received from the processor 11c, the direct memory access controller 11g utilizes the idle time of the bus line to access the data memory 11a directly and to read the stored contents out of the memory beginning at the prescribed address byte by byte in cyclic fashion and for applying the same to the interface circuit 11f. Further, when a write command for writing N-byte data successively into the data memory 11a from a prescribed address thereof is received from the processor, the direct memory access controller 11g uses the idle time of the bus line to read the data from the interface circuit 11f and to access the data memory 11a directly for successively writing in the data beginning at the prescribed address.
Thus, via the direct memory access operation the data stored in the data memory 11a is read successively and written into the shift register SFR1 in parallel fashion through the gate circuit GT.
Next, data is delivered to a data cable LNo while being shifted bit by bit in response to the clock pulses CLK. In other words, parallel data is converted into serial data, DATA. At this time, the clock pulses CLK also are delivered through a cable LN1 to indicate each bit position of the serial data DATA. Meanwhile, the local control circuit 101 samples the serial data DATA transmitted in response to the clock pulses CLK and performs a serial-parallel conversion (SP conversion) by writing the data into the shift register SFR2 in serial fashion while the data is shifted sequentially bit by bit. At the same time, the clock pulses CLK enter and are counted by the bit counter BTC. The bit counter BTC generates a carry pulse CP to increment the address counter when eight clock pulses are counted; this being equivalent to the length (eight bits) of the serial data transmitted. The SP conversion of the serial data is ended by the incrementing of the address counter ADC. The data is written in parallel fashion from the shift register SFR2, through the data bus DB2 and into the latches L1 through L8, which correspond to the first data address i.e., the contents of the address counter ADC being 1, and are then delivered to the various operator-manipulated devices through the corresponding drivers DV1 through DV8.
Thereafter, and in similar fashion, the contents of the address counter ADC is successively incremented so that the address counter generates a first address signal and a second address signal to select the corresponding latch circuits. In FIG. 4, the address signals are generated within the local control circuit 101. It is permissible, however, to transmit the address signals from the numerical control unit 11 via the cable LNo. In such case the cables LN1 and LN2 can be deleted.
In the foregoing, command data is successively transmitted from the numerical control unit 11 to each of the operator-manipulated devices, namely to the tape reader 13, tape puncher 14, MDI unit 16, operator's pendant 17 and manual pulse generator 18.
On the other hand, data is also received by the interface circuit 11f from each of the operator-manipulated devices, through the receivers RV1 through RVm, data selector DSL1, data bus DB2 and shift register SFR2. This data is subsequently stored in the data memory 11a via the direct memory access controller 11g.
In accordance with the present invention, the numbers of connecting cables can be markedly reduced in a mechanical-electronics system even when the numerical control unit is remote from each of the operator-manipulated devices. This simplifies the system and prevents the occurrence of misconnections. Further, since each of the operator-manipulated devices is controlled by the local control circuit, the numerical control unit need only exchange data with the power magnetics circuit or with the power magnetics circuit and local control circuit, thereby lightening the processing burden of the numerical control unit. Since the operator-manipulated devices are collected together at a single location in accordance with the present invention, the operator can perform his tasks with greater efficiency and remote control can be performed with facility.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3571802 *||May 31, 1968||Mar 23, 1971||Bunker Ramo||Query and reply system with alphanumeric readout|
|US3673576 *||Jul 13, 1970||Jun 27, 1972||Eg & G Inc||Programmable computer-peripheral interface|
|US3970997 *||Aug 29, 1974||Jul 20, 1976||Honeywell Information Systems, Inc.||High speed peripheral system interface|
|US4025906 *||Dec 22, 1975||May 24, 1977||Honeywell Information Systems, Inc.||Apparatus for identifying the type of devices coupled to a data processing system controller|
|US4034354 *||Nov 21, 1975||Jul 5, 1977||The Bendix Corporation||Programmable interface controller for numerical machine systems|
|US4038533 *||Sep 29, 1976||Jul 26, 1977||Allen-Bradley Company||Industrial control processor system|
|US4047159 *||Jul 8, 1975||Sep 6, 1977||U.S. Philips Corporation||Data transmission systems|
|US4052702 *||May 10, 1976||Oct 4, 1977||Kenway Incorporated||Circuit for interfacing microcomputer to peripheral devices|
|US4075691 *||Nov 6, 1975||Feb 21, 1978||Bunker Ramo Corporation||Communication control unit|
|US4079452 *||Jun 15, 1976||Mar 14, 1978||Bunker Ramo Corporation||Programmable controller with modular firmware for communication control|
|US4092714 *||Dec 1, 1976||May 30, 1978||Xerox Corporation||Parallel command-status interface through multiplexed serial link|
|US4200936 *||Aug 17, 1976||Apr 29, 1980||Cincinnati Milacron Inc.||Asynchronous bidirectional direct serial interface linking a programmable machine function controller and a numerical control|
|US4298958 *||Sep 7, 1979||Nov 3, 1981||Hitachi, Ltd.||Sequence control system|
|US4314329 *||Feb 4, 1980||Feb 2, 1982||Cincinnati Milacron Inc.||Method and apparatus for using a computer numerical control to control a machine cycle of operation|
|US4368511 *||Sep 2, 1980||Jan 11, 1983||Fujitsu Fanuc Limited||Numerical controlling method and system|
|US4396973 *||Jan 16, 1981||Aug 2, 1983||Fujitsu Fanuc Ltd.||Programmable sequence controller|
|DE2839736A1 *||Sep 13, 1978||Apr 5, 1979||John Martin Weber||Programmierungsgeraet fuer numerische steuerungssysteme|
|FR2375646A1 *||Title not available|
|GB1359073A *||Title not available|
|JPS5539931A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4794541 *||Apr 16, 1985||Dec 27, 1988||Fanuc Ltd.||Numerical control method|
|US4943905 *||Feb 19, 1988||Jul 24, 1990||Fanuc Ltd.||Interfacing method in a numerical control apparatus|
|US5065306 *||May 24, 1988||Nov 12, 1991||Fanuc, Ltd.||Serial interchange machine interface circuit|
|US5172311 *||Apr 8, 1992||Dec 15, 1992||Mannesmann Rexroth Gmbh||Electrical amplifier for controlling valves|
|US5239628 *||Aug 18, 1989||Aug 24, 1993||Sony Corporation||System for asynchronously generating data block processing start signal upon the occurrence of processing end signal block start signal|
|US5247295 *||Nov 9, 1990||Sep 21, 1993||Fanuc Ltd.||Pulse transfer system for manual pulse generator|
|US6219583 *||Mar 31, 1995||Apr 17, 2001||Fanuc Limited||Control system|
|US6457088||Jul 20, 1999||Sep 24, 2002||Vickers, Inc.||Method and apparatus for programming an amplifier|
|US8651111||Apr 28, 2005||Feb 18, 2014||David H. McDaniel||Photomodulation methods and devices for regulating cell proliferation and gene expression|
|U.S. Classification||700/84, 700/180|
|International Classification||B25J9/18, G05B19/4093, G05B19/408|
|Cooperative Classification||G05B2219/36161, G05B19/4093, G05B2219/33182, Y02P90/265|
|Jun 1, 1990||FPAY||Fee payment|
Year of fee payment: 4
|Jul 19, 1994||REMI||Maintenance fee reminder mailed|
|Dec 11, 1994||LAPS||Lapse for failure to pay maintenance fees|
|Feb 21, 1995||FP||Expired due to failure to pay maintenance fee|
Effective date: 19951214