US 4644564 A Abstract A maximum-likelihood sequence decoder is used with a partial-response signaling system for processing sequences of sampled values from a communication channel or recording device. The partial-response signals can be duobinary, dicode, or partial-response class-IV. The maximum-likelihood decoding for each sequence can be based upon a two-state trellis. Instead of two survivor metrics for two states, only a difference metric is necessary.
Claims(3) 1. An apparatus for maximum-likelihood sequence decoding of sample sequences with intersymbol interference of the partial-response class-IV type, said apparatus forming a decoder processing path responsive to received signals x
_{t}, said path typically including ad seriatim a whitened-matched filter (13), sampling means (15), metric value determining circuitry (19), and storage updating means (21) for survivor sequences, characterized in that:the metric value determining circuitry (FIG. 6) comprises: a subtractor (85) having as a first input thereto a sample value y _{n} ;a unit (81) for limiting the output of the subtractor to a range between +1 and -1; means (91) for combining the output of the limiting unit and the sample value and for providing binary sign magnitude indication of said combined output b _{n-1} ; anda path (87) applying the combining means output DJ _{n-1} as a second input DJ_{n-2} to the subtractor;said metric determining circuitry being further characterized in that: said combining means output DJ _{n-1} representing a recursive difference survivor metric formed from the range limited difference between the sample value y_{n-1} ; andsaid subtractor output representing the difference between combining means output DJ _{n-1} and the sample value y_{n}.2. A method of maximum-likelihood sequence decoding of the output signal of a communication or recording device channel, said channel synchronously transmitting or recording a sequence of binary symbols a
_{n} =+1 or -1, n being an integer symbol time index, said output signal being filtered and sampled to obtain samples y_{n} with intersymbol interference of the partial-response classes described by the polynomials 1+d, 1-d, or 1-d^{2} ^{2}, the method determining from the samples y_{n} the most likely transmitted or recorded sequence of binary symbols, said method being executable on a decoder of the type having a memory for storing binary valued indicia of state transitions underlying said decoding method, comprising the steps of:recursively computing a difference metric at each sampling instant, which metric represents the difference between implicit survivor metrics, each implicit survivor metric indicating the probability of occurrence of the binary survivor sequence obtained and stored in the decoder memory, the recursive computing step further including the steps of: generating two binary symbol decisions and using said decision to extend the binary survivor sequences stored in the path memory, the sign of the difference metric determining at each sampling instant which one of the survivor sequences currently stored in the path memory is the more probable sequence from which the output of the decoder is to be selected. 3. A method according to claim 2, wherein the maximum-likelihood sequence decoding of sample signals with intersymbol interference of the partial-response class-IV type being described by polynomial 1-d
^{2}, and further wherein the sequences of even and odd indexed samples y_{n} are independently decoded based upon independent state transition diagrams with two states at each sampling instant.Description This application is a continuation-in-part of copending application Ser. No. 06/520,666, filed on Aug. 5, 1983, now U.S. Pat. No. 4,571,734 in the name of F. B. Dolivo, G. Ungerboeck, and T. D. Howell. This invention relates to the decoding of a binary symbol sequence (a Partial-response signaling allows a better handling of intersymbol interference and allows a more efficient utilization of the bandwidth of a given channel. In partial-response (PR) systems, a controlled amount of intersymbol interference can be allowed. As the intersymbol interference then is known, the receiver can take it into account. PR signaling in communications allows transmissions at the Nyquist rate, and provides an attractive trade-off between error probability and the available spectrum. The partial-response systems described by the polynomials 1+d, 1-d, and 1-d Maximum-likelihood sequence estimation, in particular the Viterbi algorithm, is an effective tool in receivers for improving the detection of symbol sequences in the presence of intersymbol interference. It as described in the articles by G. D. Forney, "The Viterbi Algorithm", Proceedings of the IEEE, Vol. 61, No. 3, March 1973, pp. 268-278, and by G. Ungerboeck, "Adaptive Maximum-likelihood Receiver for Carrier-modulated Data Transmission Systems", IEEE Transactions on Communications, Vol. COM-22, No. 5, May 1974, pp. 624-636. These articles also show some basic form of MLSE receivers or portions thereof. The utilization of MLSE or Viterbi algorithm in connection with partial-response signaling systems was already suggested for both above-mentioned application areas by a publication of H. Kobayashi, "Application of Probabilistic Decoding to Digital Magnetic Recording Systems", IBM Journal of Research and Development, Vol. 15, No. 1, January 1971, pp. 64-74. The problem of maximum-likelihood sequence estimation can be stated as follows. Given a received sequence (z It is an object of the present invention to devise a method and apparatus for reliably decoding a signal representing a sequence of time-discrete binary symbols received from a transmission channel or read in a recording device, which allow to reduce the necessary circuitry to a minimum and enable operation at high speed. It is a further object to generate tentative decisions with a minimum delay with respect to the time at which the signal representing the symbol is presented to the receiver. It is assumed that the channel synchronously transmits or records a sequence of binary symbols a
1-d: y where r The foregoing objects are satisfied in that the invention uses only two survivor sequences, and only the difference between the two metrics associated with these survivor sequences is computed and stored. Simplicity and efficiency result because less computing and storage resources are required to process the one difference metric that would have been required to process the two path metrics, and the difference metric cannot grow without bound as the path metrics can. Reliability results from the fact that the detected sequence is chosen by maximum-likelihood sequence estimation. It is the one most likely to cause the observed sequence of sampled values at the receiver. In the case of 1-d The method steps include (a) partitioning the sample values y FIG. 1 depicts schematic survey of a transmission/recording system which is the environment for the present invention. FIG. 2 sets out impulse responses and transmission spectra of channels and filters in the system of FIG. 1. FIG. 3 shows a schematic representation of the separate handling of interleaved sequences in the decoder. FIG. 4 constitutes trellis diagrams for consecutive states of the survivor sequences in the decoder. FIG. 5 shows a block diagram of a first embodiment comprising circuitry for determining pairs of survivor metrics for two interleaved dicode sequences. FIG. 6 shows a block diagram of a second embodiment comprising circuitry for determining survivor metric differences in a whitened-matched filter receiver. FIG. 7 shows a block diagram of a third embodiment comprising circuitry for determining survivor metric differences in a matched filter receiver. FIG. 8 shows a block diagram of a limiter-decision unit for the circuitry of FIGS. 6 and 7. FIG. 9 shows a block diagram of the shift register and selection circuitry for storage and updating of survivor sequences. Partial-response signaling is a technique which enforces spectral properties by allowing a controlled amount of intersymbol interference. A survey of partial-response signaling is given in the article by P. Kabal et al, "Partial Response Signaling", IEEE Transactions on Communications, Vol. COM-23, No. 9, September 1975, pp. 921-934. With maximum-likelihood sequence estimation (MLSE), most partial-response schemes perform practically as well as a system without intersymbol interference. Reference is made in the article by H. Kobayashi, "Application of Probabilistic Decoding to Digital Magnetic Recording Systems", stated above. Hence, no penalty has to be paid for the benefit of spectrum shaping, except for the higher complexity of the MLSE decoding hardware which performs the Viterbi decoding process. Partial-response "class-IV" (PR-IV) signaling leads to spectral nulls at DC and at half of the signaling rate. PR-IV is therefore well suited for channels with baseband-like characteristics, which do not transmit DC. Magnetic recording channels are of this type and PR-IV is therefore regarded as a promising technique to achieve higher storage density in digital magnetic recording systems. In the following, first the theory of MLSE for PR-IV signaling is reviewed. In the next section, two types of MLSE receivers with identical performance are discussed, called the whitened-matched filter (WMF) version and the matched filter (MF) version. They differ in the receiver filters used before sampling the received signal at signaling rate, and in the computation of survivor metrics in the Viterbi decoding process. In another section explaining basic invention features, it is shown that PR-IV sequences can be viewed as two "dicode" sequences which are interleaved, and that each dicode sequence can be decoded independently. For binary systems, as in saturation recording, the state-transition diagram of each dicode scheme exhibits then only two states. Instead of two survivor metrics, it is possible to compute only one difference survivor metric. In a further section, embodiments are disclosed which are digital implementations of Viterbi decoders utilizing pipelined handling of interleaved PR-IV sequences, some of them using difference survivor metrics. Simplicity and capability for operation at high speed are achieved by decoding the two dicode sequences in an interleaved and pipelined fashion. A dicode decoder is the same as the partial-response class-IV decoder with the interleaving and pipelining removed. A duobinary decoder is similar to a dicode decoder with the signs of certain quantities changed. The discussion focuses on the partial-response class-IV decoder. The changes necessary for the dicode and duobinary cases are given at the end of each section. FIG. 1 is a schematic representation of a transmission system in which the present invention finds application. A sequence of binary values a It should be noted that channel 11 can also be a magnetic recording device, that the white noise w(t) is added during recording and reading, and that x(t) is the output signal of a magnetic reading transducer. Signal x(t) is applied to a receiver filter 13. For the present case, this may be either a whitened-matched filter (WMF), or a matched filter (MF), as will be explained later. The filter output is a continuous signal y(t) or z(t), depending on the type of filter. The filter output signal is sampled at regular intervals T by sampling means 15. The result is a sequence of time-discrete samples y These samples are furnished to a Viterbi decoder 17 in which they are used in a maximum-likelihood sequence estimation (MLSE) process to obtain binary output values b The present invention is concerned with the means for MLSE decoding contained in Viterbi decoder 17. In the sequel, some theoretical explanations will be given prior to the detailed description of the invention and the selected embodiments. As shown in FIG. 1, PR-IV signaling results from sending a data sequence (a In the frequency domain, this corresponds to the channel transfer characteristics ##EQU2## At the output of the channel the received signal becomes ##EQU3## where w(t) is assumed to be additive wide-band white noise. The above description of a PR-IV transmission system applies as well to a magnetic recording system where in the case of saturation recording the data amplitudes are binary: a The function h(t) is shown in FIG. 2(a). The transmission characteristic of the channel is depicted in FIG. 2(c). Two receiver versions for PR-IV signals are described. They are equivalent in that both perform true maximum-likelihood sequence estimation (MLSE). As mentioned above, they differ in the receiver filters used. The whitened-matched filter (WMF) version is more commonly known. In the particular case of the signal being given by (3), the WMF to be used as a receiver filter is just an ideal low-pass filter with cutoff frequency 1/2T. Its transmission characteristic is shown in FIG. 2(d). The output of this filter is given by ##EQU4## where h(t) was defined by (1) and has a shape as shown in FIG. 2(a), and r(t) denotes white noise band-limited to 1/2T. For the matched filter (MF) version, the receiver filter is matched to the channel characteristic given by (2), i.e. it has a characteristic as shown in FIG. 2(c). Thus, if causality is ignored, the receiver filter exhibits the transfer function ##EQU5## The overall response of the channel and MF to an isolated input a The noise p(t) is band-limited to 1/2T and correlated. The function s(t) is shown in FIG. 2(b). Sampling the outputs of the WMF and the MF at times nT, leads, respectively, to the sampled signals
y
z The last equality in (9) expresses the fact that the MF output samples could also be obtained by digital filtering of the WMF output signals. In the WMF case, the noise samples (r The squared terms of the right-hand side of (10) are identical for all sequences (a For the MF case, an equivalent cost function is obtained by replacing in the term y In the sequel, the following notation is used for the cost function: ##EQU11## where the auxiliary function v The sequence which maximizes J is determined by the Viterbi decoding algorithm. The cost function J can be rewritten as ##EQU13## Hence, its maximization can be carried out separately for JE with respect to (a As illustrated in FIG. 3, this point of view corresponds to treating PR-IV sequences characterized by the polynomial 1-D The Viterbi algorithm is now developed as it applies to one of the two interleaved dicode systems. Hence, in the following derivation indices are either even or odd. A general description of the Viterbi algorithm is given in the above-mentioned article by G. Forney, "The Viterbi Algorithm", and in a publication by J. F. Hayes, "The Viterbi Algorithm Applied to Digital Data Transmission", Communication Society Magazine, Vol. 13, March 1975, pp. 15-20. The Viterbi algorithm for one dicode system is illustrated in FIG. 4. It determines in a two-state trellis diagram the sequence . . . , a
q The survivor metrics and associated survivor sequences are extended by the recursion ##EQU15## where a WMF Version:
J
J MF Version:
J
J The Viterbi decoding process for binary dicode sequences can be significantly simplified by considering not the pairs of explicit survivor metrics but only the difference between the survivor metrics, i.e.
DJ From FIG. 4, it can be seen that four possible extensions of the survivor sequences are to be considered: ##STR1## The corresponding path selections are indicated on the right. Considering the above four cases, and observing (21)-(25), allows the determination of the following recursions for the difference survivor metrics: WMF Version: ##EQU16## MF Version: ##EQU17## The conditions in the above recursions reveal that extension (d) can never occur. The non-occurrence of this extension can be seen in FIG. 4. The theoretical background for the dicode (1-d) and the duobinary (1+d) systems is similar to that given in equations (1)-(28). The following summarizes the differences and gives the final results. The equations corresponding to (27) and (28) are directed to the dicode and duobinary cases. The processing of samples from a dicode channel is the same as the processing of the even (or odd) subsequence described for partial-response class-IV. The dicode versions of equations (8)-(28) are obtained by changing all occurrences of time indices n+2, k+2, n-2, and k-2, n+1, k+1, n-1, and k-1, respectively. Splitting into even and odd subsequences as described by equation (16) is omitted. The recursions for the survivor metrics corresponding to equations (27) and (28) are: WMF Dicode Version: ##EQU18## MF Dicode Version: ##EQU19## The duobinary versions of equations (8)-(28) can be obtained from the dicode versions by changing the signs of certain terms. For example, (8) and (9) become:
y
z The recursions for the difference survivor metrics for duobinary are: WMF Duobinary Version: ##EQU20## MF Duobinary Version: ##EQU21## In the following section, embodiments of the Viterbi decoder or MLSE decoder 17 which incorporate the invention are described. As shown generally in FIG. 1, the Viterbi decoder consists of a first section 19 for determining survivor metrics and for obtaining intermediate and tentative values for the receiver output signal, and a second section 21 for storing and updating the survivor sequences furnished by section 19, and for making the final selection of output values. Three embodiments are disclosed for section 19, in connection with FIGS. 5, 6, and 7. A suitable implementation of a limiter-decision circuit used in the second and third embodiments will be disclosed with reference to FIG. 8. Finally, one implementation of section 21 is explained and shown in FIG. 9. Each of these embodiments is described first for the partial-response class-IV channel. The modifications necessary to convert them to dicode and duobinary are described at the end. It should be noted that the digital circuitry discussed in the following generates binary output quantities which assume either value 0 or 1, and are therefore designated as "b The transition from one form to the other is formally given below in equations (29) and (30). In FIG. 5, an embodiment of section 19 of the Viterbi decoder is shown which determines two survivor metrics for the two states of the decoder, and which furnishes intermediate values b It comprises V unit 25 which computes for an applied input value y Four adders 35, 37, 39, and 51 are provided for adding the contents of registers 27 . . . 33, i.e. the four previously stored values of v The formal relationship between decoded values a With the aid of multiplexers or gating circuits 63 and 65, the sign bits available at the outputs of subtractors 51 and 53 select the maximum of each pair of values stored in registers 43/45 and 47/49, respectively, and furnish the resulting two values as metric values J The formal relationship between survivor metrics J It should be noted that the survivor metrics are not normalized but are allowed to wrap around the maximum values in their two's complement representation. With a sufficient word length, the add and subtract operations will still produce correct results. At the bottom of FIG. 5, boxes with indices are shown which illustrate the fact that the circuitry has separate stages. Each of the double vertical lines indicates where the circuitry comprises storage units that separate stages. At any time, each section contains only values either with even indices or with odd indices. At each clock time, the whole contents are shifted from one stage to the next for further processing, but no mixing between odd and even indexed values occurs. This shows that in the whole circuity, two subsequences with odd and even indices, respectively, are handled completely separately as indicated in FIG. 3, but in an interleaved and pipelined manner. Nevertheless, the sequence of input values and the sequence of output values are continuous, i.e. they need not be expressly separated into two subsequences because this splitting occurs automatically within the circuit of FIG. 4 due to the separation of stages by clocked storage units, and due to suitable feedback between stages. FIG. 6 shows an embodiment of section 19 of the Viterbi decoder which does not explicitly determine the two survivor metrics but only their difference. This second embodiment is suited for the WMF (whitened-matched filter) version of the receiver, i.e. the version producing receiver samples y The quantity shown next to each line in FIG. 6 indicates the number of bits transferred on that line in parallel. In the absence of noise, the samples y For soft decoding, the value for L should be chosen between 2 and 4. An important portion of the circuitry of FIG. 6 is the limiter-decision unit 81. With the aid of this unit, intermediate values b Limiter-decision unit 81 can be implemented either as a read-only store (ROS), as a programmable logic array (PLA), or by discrete logic. An example is shown in FIG. 8 and will be explained later. Referring again to FIG. 6, an input value y Limiter-decision unit 81 also furnishes the two binary intermediate values b One output line of adder 91, i.e. the one carrying the sign bit, is connected to an inverter 97 which complements the sign of DJ Similar as for FIG. 5, also at the bottom of FIG. 6 boxes with indices are shown. These boxes indicating separate stages and intermediate clocked storage units also illustrate the interleaved and pipelined handling of two sequences of alternating samples. A comparison between FIG. 5 and FIG. 6 reveals that fewer stages are required for the circuitry of FIG. 6, thus it has less delay and needs less hardware. A third embodiment of section 19 of the Viterbi decoder is illustrated in FIG. 7. It also directly determines the survivor metric difference value DJ In the MF case, sample values z The circuitry of FIG. 7 comprises the same limiter-decision unit as the circuitry of FIG. 6. Here, this unit has reference number 81a (detailed embodiment shown in FIG. 8). The output same Q Two outputs of limiter-decision unit 81 furnish the binary intermediate values b Contents of these flipflops are furnished as intermediate values b The blocks at the bottom of FIG. 7 with indices inserted illustrate also for this case the different stages of the circuitry separated by clocked storage units, which enable the pipelined and interleaved processing of the two dicode subseqeunces. A comparison of FIGS. 5, 6, and 7 immediately reveals that among the three metric-computation schemes presented, the MF version with difference metric calculation (FIG. 7) offers the lowest circuit complexity, capability of operation at highest signaling rate (from a circuit delay consideration), and shortest delay in producing binary decision values. Another advantage of the second and third embodiments over the first is that the difference metric is automatically normalized. Equations (27) and (28) show that it does not accumulate as the individual survivor metrics do. There is no need to provide extra word length to allow for wrap around. FIG. 8 shows an embodiment of limiter-decision unit 81/81a for the case L=4 comprising discrete logic circuits. As mentioned previously, this unit implements equation (31). It has eight inputs for the eight bits of a sample P The five input lines for the most significant bits of P The two output lines for the most significant digits of Q The output line for the first binary intermediate value b Details of section 21 of the Viterbi decoder 17, for the storage and updating of survivor sequences, are shown in FIG. 9. In consists essentially of two shift registers 137 and 139 each comprising 2m-1 flipflop stages arranged in sequence. Every second flipflop is connected to its successor through a multiplexer or gating circuit that allows to selectively transfer to the successor flipflop either the bit from the preceding flipflop stage of the same shift register or the bit from the corresponding flipflop stage of the other shift register. The control inputs of all multiplexers/gating circuits of one shift register are commonly connected to the input of the respective shift register, i.e. the binary value of the bit just inserted into the first stage of a shift register also determines the selections made by all multiplexers/gating circuits of the respective shift register. The output flipflop stages of both shift registers are connected to an additional multiplexer/gating circuit 141 which is controlled by a binary signal on selection control line 143. The output value of multiplexer/gating circuit 141 is stored in a final flipflop stage 145 having output line 147 for finally selected output bits b As shown in FIG. 9, inputs of the two shift registers 137 and 139 are connected to the two intermediate value outputs (b Operation is as follows. The two shift registers store the two binary sequences which have the highest probability of being similar to the transmitted sequence (a The finally selected bits are furnished sequentially on line 147 which is the output line of the whole Viterbi decoder 17. Section 21 shown in FIG. 9 has an additional portion 149 for providing a sequence of tentative output values which is required for timing recovery and gain control in the receiver. This section comprises an additional group of 2m-1 flipflops, each corresponding to one flipflop stage in the two shift registers 137 and 139 (except the last stage). The flipflops are arranged in pairs as shown, and the input of each pair (except the first one) is connected to a multiplexer/gating circuit whose two inputs are connected to the output of an associated flipflop stage in the first (137) and second (139) shift register, respectively. The control inputs of all multiplexers in portion 149 as well as the input to the first pair of flipflops are connected to control line 149, i.e. to output line 79 (or 79a, 79b) of survivor metric section 19. Thus, the outputs of all flipflops in portion 149 together with the output of flipflop 145 deliver, at each sampling time, a sequence of tentative output values b As was mentioned earlier, indices j and j-1 at the inputs of FIG. 9 correspond to indices n-4 and n-5 at the outputs of FIG. 5, to indices n-2 and n-3 at the outputs of FIG. 6, and to indices n-1 and n-2 at the outputs of FIG. 7, respectively. Thus, in FIG. 9, the index j can be replaced by n-4, n-2, or n-1, depending on whether the binary decision values b If circuit delay permits, the single-bit registers (flipflops) 55/57/75, 93/95/99, and 107, 109, 113, which in FIGS. 5, 6, and 7 buffer the output values, can be omitted, thus reducing processing delay by one signaling period. Similar simplifications are also posible in connection with deriving tentative decisions from portion 149 and the final decision, if circuit delay is not critical in the further operations performed with these signals. The partial-response class-IV embodiments described above can be converted to dicode embodiments by removing the registers and flipflops used for interleaving and pipelining. Removing a register or flipflop means deleting it from the circuit and connecting its inputs directly to their corresponding outputs. The elements to be removed are 43, 45, 47, and 49 in FIG. 5 with elements 83, 89 in FIG. 6, 101 in FIG. 7, and 151, 153, 155, 157, 159, 161, 163, and 165 in FIG. 9. The dicode embodiments can be converted to duobinary embodiments by the following modifications. The "V unit" 25 in FIG. 5 should generate an output according to the duobinary versions of equations (14) and (15): ##EQU25## Subtractor 85 in FIG. 6 should be changed to an adder, and adder 91 should be changed to a subtractor. The designations of 61a and 59a should be interchanged. Further, the adder in FIG. 7 should be changed to a subtractor. The designation 61b and 59b should also be interchanged.
______________________________________TABLE OF SYMBOLS USED______________________________________a = discrete amplitudeb = binaryc = continuouss = sampled Value Range Time Relation______________________________________a Patent Citations
Referenced by
Classifications
Legal Events
Rotate |