|Publication number||US4646126 A|
|Application number||US 06/638,782|
|Publication date||Feb 24, 1987|
|Filing date||Aug 8, 1984|
|Priority date||Oct 7, 1983|
|Publication number||06638782, 638782, US 4646126 A, US 4646126A, US-A-4646126, US4646126 A, US4646126A|
|Original Assignee||Kabushiki Kaisha Toshiba|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (3), Referenced by (14), Classifications (43), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a semiconductor device of the type in which IC (integrated circuit) chips are mounted on a semiconductor substrate.
In one of the known printed circuit boards used for forming a logic system, gold interconnection wiring layers are printed on a ceramic substrate. This known printed circuit board involves many problems. For example, the manufacturing cost is high. The pitch of the interconnection wiring layers is several hundred microns, resulting in a considerably low density of the interconnection wiring layers. With such a large pitch of the interconnection wiring layers, the length of the interconnection wiring layers is correspondingly longer. This results in a large stray capacitance associated therewith and a limitation in the operation speed of the associated device.
To solve such problems, there has been an approach in which many IC chips with different functions are mounted on the substrate, while being interconnected by a wiring layer. Prior to this approach, many IC chips with the same functions were mounted on the substrate. The approach improves the density of the interconnection wiring layers and the operation speed of the device. However, with only one defective IC chip, the entire device must be treated as a bad one. This reduces the production yield. To cope with this problem, there has been proposed another appoach in which a sub-IC chip is used in addition to the regular IC chips, giving a redundancy in use to the device. When a defective IC chip is found, the sub-IC chip is used for replacement with the defective regular IC chip. Therefore, the production yield is improved. The additional use of the redundancy circuit, however, deteriorates the operating speed performance.
Accordingly, an object of the present invention is to provide a semiconductor device which is low in cost and high in operation speed and integration density.
According to the invention, there is provided a semiconductor device comprising:
a semiconductor substrate;
an IC chip mounted on said substrate;
interconnection wiring layers formed on said substrate with an insulation film;
pads for said IC chip; and
means for connecting said IC chip to said pads.
FIG. 1 shows a plan view of a semiconductor device which is an embodiment of the present invention;
FIG. 2 shows a cross sectional view taken on line II in FIG. 1;
FIG. 3 shows a cross sectional view of another embodiment of a semiconductor device according to the present invention; and
FIG. 4 shows a partial cross sectional view of a yet another embodiment of a semiconductor device according to the present invention.
Referring to FIGS. 1 and 2, there is shown a first embodiment of a semiconductor device according to the present invention.
In FIG. 2, a semiconductor substrate 1 is a silicon substrate of high impurity concentration, or low resistance. The silicon substrate 1 is grounded or may be connected to a power source of 5 V, for example. First to third SiO2 films 21, 22 and 23 are layered on the semiconductor substrate 1 in a successive manner. An opening 4 for receiving an IC chip 3 is formed in a predetermined region of the SiO2 films 21, 22 and 23. In order to improve the production yield, the IC chip 3 used is preferably one of the chips tested and evaluated as good. If necessary, an IC chip 3 not tested and evaluated may be used. The IC chip 3 is mounted on the semiconductor substrate 1 by interposing a conductive adhesive layer 5 therebetween. The adhesive layer 5 fixes the IC chip 3 to the semiconductor substrate 1 while allowing electrical and thermal conduction between them. Alternatively, for fixing the IC chip 3 to the semiconductor substrate 1, an alloy layer may be formed therebetween using AuSi, for example. Use of the alloy provides a path allowing heat generated in the IC chip 3 to go to the semiconductor substrate 1. Formed on the first SiO2 film 21 are a plurality of interconnection wiring layers 6 extending vertically and horizontally as viewed in a plan. The SiO2 film 21 is formed relatively thick, and therefore has a small stray capacitance associated therewith. The small stray capacitance provides a small delay of signal transmission on the interconnection ring wiring layers 6. A region 21 A near the opening 4 for IC chip reception is thinner than the other region 21 B. An interconnection wiring layer 7 made of polysilicon or metal, for example, is formed on the thin film region 21 A. The formation of the thin film region 21 A is made in the same manufacturing step as that of the interconnection wiring layer 6. If necessary, another step may be used for forming the thin film region 21 A. The interconnection wiring layer 7 and the thin film region 21 A cooperate to form a grounded capacitance C. The capacitor C serves as a filter for reducing noise coming from a power line when the interconnection wiring layer 7 is used as the power line.
Contact holes 8 are selectively formed in the second SiO2 film 22. Further formed on the SiO2 film 22 are pads 11 made of aluminum and an interconnection wiring layer 12 extended from the pads 11. Connected to the pad 11 is the IC chip 3 through a bonding wire 10. The interconnection wiring layers 12 are respectively in contact with the interconnection layers 6 through the contact holes 8. An opening 13 for guiding the bonding wire 10 to the pad 11 is formed in the region of the third SiO2 film 23 where the pad 11 is provided.
The semiconductor device thus structured has the following effects:
(1) The manufacturing cost is low, since a silicon, not ceramic, substrate is used.
(2) The technique for fabricating an IC is used for the formation of the interconnection wiring layers 6 or 12. Therefore, flatness of the interconnection layers is excellent. Further, the width of the interconnection wiring layer and the pitch of the interconnection layers are very small, 1-2 μm. Therefore, the circuit density is improved, and the length of the interconnection layer is shortened.
(3) The small width and pitch of the interconnection layers brings about the small stray capacitance associated with the interconnection layers. Therefore, the buffer for driving the interconnection layers and their associated circuits may be small in size, leading to an improvement of the operation speed performance.
It is known that if charge and discharge time of the signal line is indefinitely small, the signal transmission speed indefinitely approaches the propagating speed of light on the signal line. In light of this, the short length of the interconnection wiring layer in this embodiment is used for the signal line, the signal transmission distance is short and this provides a lessened transmission delay signal.
(4) The capacitor C formed by the interconnection wiring layer 7 and the thin film region 21 A is closer to the opening 4 in which the IC chip 3 is set. Therefore, an inductance formed associated therewith is small, so that highly effective filtering by the capacitor C is possible. As a result, when the interconnection layer is used as a power line, noise interference is minimized.
(5) The components formed on the semiconductor substrate 1 are mainly the interconnection layers 6 and 7, the pads 11, and the interconnection wiring layers 12. Therefore, the production yield of the semiconductor devices is high. This is further enhanced when the tested and selected IC chip 3 is used.
FIG. 3 shows another embodiment of a semiconductor device according to the present invention. Only different portions and components from those in the first embodiment will be given for simplicity of explanation. As shown, the IC chip 3 is placed on the semiconductor substrate 1 through an insulating film 22A as a thin portion of an insulating film 22. Therefore, the IC chip 3 is electrically isolated from the semiconductor substrate 1. This feature allows individual potentials to respectively be applied to the IC chip 3 and the semiconductor substrate 1. Reference numerals 31 and 32 designate first interconnection wiring layers, and reference numerals 41 and 42 designate second interconnection layers. This embodiment can attain the effects comparable with those of the first embodiment.
FIG. 4 shows yet another embodiment of a semiconductor device according to the present invention. In this embodiment, the semiconductor substrate 1 has a low impurity concentration, not a high impurity concentration. High impurity concentration is found in the region 1A of the semiconductor substrate 1 corresponding to the region where the interconnection wiring layer 7 is formed. The remaining portions of this embodiment are the same as those of the FIG. 2 embodiment. No futher explanation will be given.
Since the region 1A of the semiconductor substrate 1 is the high impurity concentration region, the interconnection layer 7 and the thin film region 21 A and the high impurity concentration region 1A cooperatively form the capacitor C. If the interconnection wiring layer 7 is used as the power line, the capacitor C effectively reduces noise from the power line as in the previous embodiments.
While in the above-mentioned embodiment, the interconnection layers are double layered, it may be formed by a single layer or three or more layers. Silicon of the interconnection layers may be replaced by other suitable material, for example, aluminum. Further, the silicon substrate may be replaced by a substrate in which a semiconductor layer is formed on the insulating substrate made of sapphire, for example.
It should be understood that the present invention may variously be changed and modified within the scope of the present invention.
As seen from the foregoing description, the present invention provides a semiconductor device with high speed, high integration density and good reliability.
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|U.S. Classification||257/296, 257/E23.029, 257/E23.008, 257/532|
|International Classification||H01L25/07, H01L25/065, H01L25/04, H01L23/492, H01L23/64, H01L25/18, H01L23/14|
|Cooperative Classification||H01L2924/15787, H01L2224/02166, H01L2224/48624, H01L23/147, H01L2224/4823, H01L2924/01013, H01L2224/48463, H01L24/05, H01L2924/30105, H01L2224/04042, H01L23/4926, H01L2924/01005, H01L2224/85424, H01L2224/05624, H01L2924/01014, H01L2924/30107, H01L24/48, H01L2924/00014, H01L2224/45144, H01L2924/19041, H01L23/642, H01L2224/48137, H01L2924/14, H01L2924/01006, H01L2924/01079, H01L2224/48091, H01L2924/01023|
|European Classification||H01L24/48, H01L24/05, H01L23/64C, H01L23/492M2, H01L23/14S|
|Aug 8, 1984||AS||Assignment|
Owner name: KABUSHIKI KAISHA TOSHIBA 72 HORIKAWA-CHO SAIWAI-KU
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:IIZUKA, TETSUYA;REEL/FRAME:004296/0938
Effective date: 19840725
|Aug 1, 1990||FPAY||Fee payment|
Year of fee payment: 4
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|Aug 10, 1998||FPAY||Fee payment|
Year of fee payment: 12