|Publication number||US4649478 A|
|Application number||US 06/750,626|
|Publication date||Mar 10, 1987|
|Filing date||Jun 28, 1985|
|Priority date||Jun 28, 1985|
|Also published as||CA1247744A, CA1247744A1, DE3680959D1, EP0206346A1, EP0206346B1|
|Publication number||06750626, 750626, US 4649478 A, US 4649478A, US-A-4649478, US4649478 A, US4649478A|
|Inventors||William S. Worley, Jr.|
|Original Assignee||Hewlett-Packard Company|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Referenced by (3), Classifications (7), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention concerns interrupt signals to interrupt execution of an instruction in a computing system when performing calculations on one or more operands.
The term interruption is utilized to discuss the basic mechanism which handles traps, checks, faults and interrupts. Traps include two sorts of possibilities: either the functions or operations requested by a current instruction cannot or should not be carried out, or system intervention is desired by the user before or after the instruction is executed. Examples of the first possibility include arithmetic operations which result in overflow and instructions executed with insufficient privilege for their intended function.
Typically, when an arithmetic operation results in an overflow, the overflow is either ignored or is "trapped" out utilizing a data trap. When the overflow is ignored, meaningless data may result and be used in the execution of the remainder of the instruction. Typically, the processor status word (PSW) contains a bit which directs overflow control. This results in a global instruction for overflow trapping which complicates the operating system design and user application programs. Further, selective trapping of a data overflow is not possible without changing the PSW bit which provides overflow control.
In accordance with the principles of the present invention, selective data or overflow trapping is provided. Overflow control for a particular arithmetic operation is determined by a seven-bit field within the operation instruction thereby eliminating a global overflow control mode.
FIG. 1 illustrates a block diagram of the preferred embodiment in accordance with the principles of the present invention.
FIG. 2 illustrates a block diagram representing a 32-bit instruction word.
Referring to FIG. 1, the preferred embodiment of the present invention comprises arithmetic logic unit (ALU) 3, AND gate 5 and instruction storage register 1. The ALU 3 receives a first operand and a second operand on lines 12 and 14, respectively, and, in response to a control signal on line 4, performs a desired operation. The control signal on line 4 is derived from an instruction or opcode word stored in register 1. The desired operation may be, for example, an addition or a shift and add (multiply) operation. If an overflow occurs as a result of the execution of the opcode stored in register 1, the ALU 3 will provide a logic signal on line 8 to AND gate 5. A logic signal on line 6 which determines whether or not to trap if an overflow occurs is input to the AND gate 5. If both of the signals input to the AND gate 5 are a logic 1, a logic 1 is output on line 10. The logic signal on line 6 is derived from the bit or bits of the opcode word stored in cell 7 of the register 1.
Referring now to FIG. 2, the format of a major opcode instruction word is illustrated. Field 29 is six bits long and is the major opcode field determining the class of operation to be done by the machine. For example, the "02" entered in major opcode field 29 defines a three-register arithmetic and logical instruction; i.e., one major opcode defines arithmetic and logic operations between two operands stored in two general registers (not shown) and (conditionally) puts the result, zero, one, the generated condition or the first operand into a third general register (not shown). Fields 27, 25 and 21 contain the addresses of the general registers holding the operands and the general register where the resultant is stored. Fields 31 and 33 determine the conditions that the resultant is to be tested for and may be any of eight arithmetic conditions or their negations. The opcode extension field 23 is seven bits long and defines the arithmetic or logic operations to be performed; add, subtract or shift, for example. The opcode extension field 23 also contains the bit or bits which determine whether or not to trap if an overflow occurs.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4312034 *||May 21, 1979||Jan 19, 1982||Motorola, Inc.||ALU and Condition code control unit for data processor|
|US4346437 *||Aug 31, 1979||Aug 24, 1982||Bell Telephone Laboratories, Incorporated||Microcomputer using a double opcode instruction|
|US4409654 *||Mar 6, 1981||Oct 11, 1983||Hitachi, Ltd.||Data processor adapted for interruption to an instruction stream|
|US4498136 *||Dec 15, 1982||Feb 5, 1985||Ibm Corporation||Interrupt processor|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5327567 *||Mar 19, 1992||Jul 5, 1994||Texas Instruments Incorporated||Method and system for returning emulated results from a trap handler|
|US6816962||Feb 25, 2002||Nov 9, 2004||International Business Machines Corporation||Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions|
|US20030163670 *||Feb 25, 2002||Aug 28, 2003||International Business Machines Corporation||Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions|
|U.S. Classification||710/260, 712/244|
|International Classification||G06F7/48, G06F9/48|
|Cooperative Classification||G06F7/4991, G06F7/48|
|Aug 26, 1985||AS||Assignment|
Owner name: HEWLETT-PACKARD COMPANY, PALO ALTO, CALIFORNIA, A
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WORLEY, WILLIAM S. JR.;REEL/FRAME:004456/0555
Effective date: 19850814
|Aug 27, 1990||FPAY||Fee payment|
Year of fee payment: 4
|Sep 1, 1994||FPAY||Fee payment|
Year of fee payment: 8
|Sep 9, 1998||FPAY||Fee payment|
Year of fee payment: 12
|Jan 16, 2001||AS||Assignment|
Owner name: HEWLETT-PACKARD COMPANY, COLORADO
Free format text: MERGER;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:011523/0469
Effective date: 19980520