|Publication number||US4654120 A|
|Application number||US 06/793,400|
|Publication date||Mar 31, 1987|
|Filing date||Oct 31, 1985|
|Priority date||Oct 31, 1985|
|Also published as||CA1267349A, CA1267349A1, DE3672570D1, EP0224039A2, EP0224039A3, EP0224039B1|
|Publication number||06793400, 793400, US 4654120 A, US 4654120A, US-A-4654120, US4654120 A, US4654120A|
|Inventors||James J. Dougherty|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Non-Patent Citations (8), Referenced by (16), Classifications (15), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Technical Field
This invention relates to a method of making integrated semiconductor circuit structures and more particularly to a method of making planar semiconductor structures having filled grooves or trenches.
2. Background Art
Grooves or trenches filled with insulating material, such as silicon dioxide or polyimide, for isolating devices, e.g., transistors, from one another, in integrated semiconductor circuits have been known to provide significant device or transistor density improvements over other known isolation techniques such as those employing P-N junctions.
In IBM Technical Disclosure Bulletins, Vol. 17, No. 10, March, 1975, pp. 2893-2894, there is disclosed a V-groove trench filled with polyimide, Vol. 24, No. 11A, April, 1982, pp. 5458-5459, there is disclosed a transistor butted against the sidewall of a trench filled with insulating material, Vol. 23, No. 11, April, 1981, pp. 4917-4919, there is disclosed a trench filled with silicon dioxide and silicon nitride with portions of the silicon nitride being removed by a reactive ion etching (RIE) technique and Vol. 25, No. 11B, April, 1983, pp. 6129-6130, there is disclosed a method for filling a trench with silicon dioxide and planarizing the silicon dioxide with respect to the surface of the substrate in which the trench was formed.
U.S. Pat. No. 4,396,460, filed May 21, 1982, and issued Aug. 2, 1983, discloses a method for obtaining surface flatness at a groove in a semiconductor substrate by employing chemical etching and a double layer film which is made of two different substances.
In commonly assigned U.S. Pat. No 4,519,128, filed on Oct. 5, 1983, by D. G. Chesebro and F. J. Soychak and issued on May 28, 1985, there is disclosed a trench formed in a semiconductor substrate having thin layers of silicon dioxide and silicon nitride formed on the sidewalls and bottom of the trench, with the remainder of the trench filled with polyimide. Any excess polyimide is removed after being thermally cured by known etch back techniques.
It has been found that when the filling material in a trench is etched back an undesired step is formed between the surface of the substrate and the top of the filling material due to either over etching or under etching the filling material and due to the contour of the filling material at the trench. Such a step causes discontinuities in conductive lines or wiring subsequently formed over the substrate which reduces the reliability of these integrated circuits.
It is an object of this invention to provide an improved simple planarization method for semiconductor substrates having narrow grooves or trenches, e.g., less than 2 microns wide, formed therein and filled with, particularly organic material, such as polyimide.
In accordance with the teachings of this invention a method is provided for making a planar surface on a semiconductor substrate having a groove or trench formed therein and filled with a material such as an organic material which may be used to electrically isolate one region of the substrate from an adjacent region. The method includes the steps of forming a groove or trench in a semiconductor substrate through a surface thereof, depositing a filling material, such as an organic material, within the trench and on the surface of the substrate, forming a block of material over the trench on the organic material so as to extend a given distance over the surface of the substrate, etching the organic material and the block with a given etchant so as to remove the block and the organic material disposed over the surface of the substrate, forming a layer of material over the surface of the semiconductor substrate so as to cover the remaining portion of the organic material, with the layer of material and the organic material having similar etch rates with a given etchant and etching the layer of material and the organic material until all of the layer of material is removed.
In a preferred embodiment of this invention, the organic material is polyimide, each of the etching steps is carried out with a dry etching process, the etchant being 100% oxygen gas, the block of material is photoresist and the layer of material is also photoresist.
The foregoing and other objects, features and advantages of the invention will be apparent from the following and more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.
FIGS. 1, 2, 3 and 4 are sectional views of a structure having a trench formed in a semiconductor substrate taken at succeeding stages during the fabrication of the structure made in accordance with the teachings of the present invention.
Referring to the drawings in more detail there is illustrated in sectional view in FIG. 1 a structure which includes a semiconductor substrate 10, preferably made of silicon, having a P type conductivity and an epitaxial layer 12 having a surface 14 and of N type conductivity grown on the substrate 10 by known techniques with an N+ subcollector diffusion region 16 formed at the junction of the substrate 10 and the epitaxial layer 12.
By using an appropriately patterned photoresist mask, with, for example, nitrogen triflouride, not shown, and known reactive ion etching (RIE) techniques, a trench 18, e.g., 2 microns wide, is formed through the epitaxial layer 12 and the N+ subcollector region 16 into the substrate 10 to a depth of approximately 5.0 microns below the surface 14 of the epitaxial layer 12 to form isolated sections 12A and 12B in the epitaxial layer 12. The trench 18 is then filled with polyimide, preferably by depositing a first layer of about 3.5 microns of DuPont 2560 polyimide on the surface of the epitaxial layer 12 and allowing the polyimide to flow into the trench 18 during a spinning operation, curing the first polyimide layer at 80° C. for 13 minutes and then depositing a second layer of about 3.5 microns of DuPont 2560 polyimide over the first polyimide layer and curing the second polyimide layer at 400° C. for 25 minutes. Using reactive ion etching (RIE) techniques with oxygen as the etchant, the cured polyimide, not shown, on the surface 14 of the epitaxial layer 12, is removed with polyimide 20 remaining in the trench 18 to a level somewhat below the surface 14 of the epitaxial layer 12. The trench 18 is then completely filled with DuPont 2560 polyimide until a layer 22 of cured polyimide, about 1.3 microns thick, is formed on the surface 14 of the epitaxial layer 12, as indicated in FIG. 1 of the drawings. After curing the polyimide layer 22, which may have been performed at 400° C. for 25 minutes, a depression or groove 24 is known to form in the cured polyimide layer 22 over the trench 18. It has also been noted that after curing the polyimide, there are variations in the thickness of the polyimide layer 22 over the surface 14 of the epitaxial layer 12. By setting a target thickness of 1.3 microns for the cured polyimide layer 20, it has been found that the lowest point in the depression or groove 24 is located above the surface 14 of the epitaxial layer 12.
A layer of photoresist, about 2.4 microns thick, is now deposited on the polyimide layer 22 and, with an appropriately patterned mask, a photoresist segment or block 26 is formed over the trench 18 with extensions of the block 26 overlapping the surface 14 of the epitaxial layer 12 adjacent to the trench 18. The photoresist block 26 is made preferably with substantially vertical sidewalls. By again using reactive ion etching (RIE) techniques with oxygen as the etchant, the polyimide layer 22 is removed from the surface 14 of the epitaxial layer 12 except for the polyimide in the vicinity of the trench 18 under the photoresist block 26 where a polyimide segment 28, about 1.3 microns thick, is formed over the trench 18 and on the surface 14 of the epitaxial layer 12 adjacent to the trench 18, as indicated in FIG. 2 of the drawings.
The polyimide segment 28 is then covered with a layer of photoresist 30, as shown in FIG. 3, which may be of the same type as photoresist block 26, having a thickness of about 1.4 microns and having an etch rate similar to that of the polyimide block 28. The layer of photoresist 30 and the polyimide segment 28 are now removed by reactive ion etching (RIE) techniques with oxygen as the etchant to provide a planarized surface wherein it has been found that the upper surface 32 of the polyimide 20, as shown in FIG. 4, in the trench 18 is always less than 0.5 microns above the surface 14 of the epitaxial layer 12 or less than 0.3 microns below the surface 14 of the epitaxial layer 12. Thus, when a conductive line or electrical wiring is extended over the trench 18 between isolated sections 12A and 12B of the epitaxial layer 12, there is little or no likelihood that discontinuities will occur in the line or wire at the surface of the trench 18.
It should be understood that preferred polyimides for filling the groove or trench 18 are those that have a molecular weight greater than approximately 8000 grams/gram-mole. This type of polyimide is desired because the mechanical properties of lower molecular weight polyimides tend to be brittle and result in material defects such as delamination and in-situ fracturing after a trench filling operation. Although these higher molecular weight polyimides tend to produce non-planar surfaces due to the low relative solids content and viscous nature, by the use of the teachings of this invention a process is provided wherein very planar surfaces are repeatedly produced even with the use of polyimides having a molecular weight greater than approximately 8000.
In the preferred embodiment of this invention, polyimide is used as a trench filling material, however, this invention may be practiced by using materials other than polyimide, e.g., glass, given that appropriate reactive ion etching conditions and etchants are used to provide similar etch rates between the photoresist and the glass when reactively ion etching as indicated in FIG. 3 of the drawings.
It should also be noted that the process of this invention may be used advantageously to isolate one semiconductor region from another semiconductor region when making either bipolar transistors in regions 12A and 12B or when making field effect transistors.
Accordingly, it can be seen that this invention provides a very simple process for producing a highly planarized semiconductor structure when one or more trenches are formed in the structure resulting in improved reliability and higher yields for highly dense semiconductor circuits.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4396460 *||May 21, 1982||Aug 2, 1983||Hitachi, Ltd.||Method of forming groove isolation in a semiconductor device|
|US4519128 *||Oct 5, 1983||May 28, 1985||International Business Machines Corporation||Method of making a trench isolated device|
|US4545852 *||Jun 20, 1984||Oct 8, 1985||Hewlett-Packard Company||Planarization of dielectric films on integrated circuits|
|1||IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mar. 1975, "Forming Sidewall Dielectric Isolation of Integrated Circuit Devices", by P. M. Schaible et al, pp. 2893-2894.|
|2||*||IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mar. 1975, Forming Sidewall Dielectric Isolation of Integrated Circuit Devices , by P. M. Schaible et al, pp. 2893 2894.|
|3||IBM Technical Disclosure Bulletin, vol. 23, No. 11, Apr. 1981, "Prevention of Birdsbeak Formation", by I. Antipov, pp. 4917-4919.|
|4||*||IBM Technical Disclosure Bulletin, vol. 23, No. 11, Apr. 1981, Prevention of Birdsbeak Formation , by I. Antipov, pp. 4917 4919.|
|5||IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982, "Dielectric Isolation Process", by M. D. Hulvey et al, pp. 5458-5459.|
|6||*||IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982, Dielectric Isolation Process , by M. D. Hulvey et al, pp. 5458 5459.|
|7||IBM Technical Disclosure Bulletin, vol. 25, No. 11B, Apr. 1983, "Forming Wide Trench Dielectric Isolation", by P. J. Tsang, pp. 6129-6130.|
|8||*||IBM Technical Disclosure Bulletin, vol. 25, No. 11B, Apr. 1983, Forming Wide Trench Dielectric Isolation , by P. J. Tsang, pp. 6129 6130.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4836885 *||May 3, 1988||Jun 6, 1989||International Business Machines Corporation||Planarization process for wide trench isolation|
|US5009738 *||Dec 1, 1989||Apr 23, 1991||Leybold Aktiengesellschaft||Apparatus for plasma etching|
|US5456797 *||Jan 14, 1994||Oct 10, 1995||Robert Bosch Gmbh||Method of planarizing trench structures|
|US5705428 *||Aug 3, 1995||Jan 6, 1998||Chartered Semiconductor Manufacturing Pte, Ltd.||Method for preventing titanium lifting during and after metal etching|
|US5741738 *||Feb 21, 1996||Apr 21, 1998||International Business Machines Corporation||Method of making corner protected shallow trench field effect transistor|
|US5863828 *||Sep 25, 1996||Jan 26, 1999||National Semiconductor Corporation||Trench planarization technique|
|US5880005 *||Oct 23, 1997||Mar 9, 1999||Taiwan Semiconductor Manufacturing Company, Ltd.||Method for forming a tapered profile insulator shape|
|US5961794 *||Oct 4, 1996||Oct 5, 1999||Nec Corporation||Method of manufacturing semiconductor devices|
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|US6365968||Aug 7, 1998||Apr 2, 2002||Corning Lasertron, Inc.||Polyimide/silicon oxide bi-layer for bond pad parasitic capacitance control in semiconductor electro-optical device|
|US6593210 *||Nov 6, 2000||Jul 15, 2003||Advanced Micro Devices, Inc.||Self-aligned/maskless reverse etch process using an inorganic film|
|US8017493 *||Sep 13, 2011||Texas Instruments Incorporated||Method of planarizing a semiconductor device|
|US8816346||Oct 31, 2012||Aug 26, 2014||Beijing Boe Optoelectronics Technology Co., Ltd.||TFT array substrate and manufacturing method thereof|
|US20090280618 *||May 7, 2009||Nov 12, 2009||Texas Instruments Incorporated||Method of Planarizing a Semiconductor Device|
|WO2001026193A1 *||Sep 29, 2000||Apr 12, 2001||Corning Lasertron, Inc.||Method for making a ridge waveguide semiconductor device|
|U.S. Classification||438/424, 438/725, 438/703, 257/E21.546, 257/E21.256, 438/699|
|International Classification||H01L21/311, H01L21/762, H01L21/302, H01L21/3065, H01L21/76|
|Cooperative Classification||H01L21/31138, H01L21/76224|
|European Classification||H01L21/311C2B, H01L21/762C|
|Oct 31, 1985||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:DOUGHERTY, JAMES J.;REEL/FRAME:004478/0114
Effective date: 19851030
|May 18, 1990||FPAY||Fee payment|
Year of fee payment: 4
|Aug 25, 1994||FPAY||Fee payment|
Year of fee payment: 8
|Oct 20, 1998||REMI||Maintenance fee reminder mailed|
|Mar 28, 1999||LAPS||Lapse for failure to pay maintenance fees|
|Jun 8, 1999||FP||Expired due to failure to pay maintenance fee|
Effective date: 19990331