|Publication number||US4694313 A|
|Application number||US 06/702,601|
|Publication date||Sep 15, 1987|
|Filing date||Feb 19, 1985|
|Priority date||Feb 19, 1985|
|Publication number||06702601, 702601, US 4694313 A, US 4694313A, US-A-4694313, US4694313 A, US4694313A|
|Inventors||James D. Beasom|
|Original Assignee||Harris Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Referenced by (34), Classifications (35), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to semiconductor structures and more specifically to an improved semiconductor structure which is capable of conductivity modulation.
High voltage sustaining capability in a semiconductor device is usually achieved by use of a high resistivity region in the device in which most of the high sustaining voltage is handled. A disadvantage of this approach is that when current is flowing through the device a large voltage drop occurs in the high resistivity region since its bulk resistance is inversely proportional to its resistivity. In the prior art, the on resistance has been reduced by conductivity modulation of the high resistivity drain region. The minority carriers which modulate the drain resistivity are introduced by an integral PN diode which is in series with the drain. A top contact version of an NMOS embodying these principles is shown in FIG. 1. The P+ region labeled anode injects holes into the N drain region whose conductivity they increase. This structure is shown in FIG. 10 of U.S. Pat. No. 4,199,774 to Plummer.
There are several problems with this structure. One results from the presence of the anode (for N channel) or cathode (for P channel) which introduces a diode offset and non-linear small signal resistance to the zero offset linear resistance of the basic MOS device. The other arises from the parasitic SCR embedded in the structure. In FIG. 1, the SCR has P+ anode as anode, N bulk as N base, P body as NPN base and N source as cathode. At high current, the lateral voltage drops in the P body developed by the flow of collected holes to the body contact (injected by the anode) forward biases a portion of the N+ source to P body junction, thereby turning on the parasitic SCR. Once on, the SCR cannot be turned off by the MOS gate, thus defeating a major feature of the structure.
Thus, it is an object of the present invention to provide an insulated gate field effect transistor capable of sustaining high voltages with reduced latch sensitivity.
Another object of the present invention is to provide an insulated gate field effect transistor having modulated drain on resistance.
Yet another object of the present invention is to provide an insulated gate field effect transistor capable of withstanding high reverse blocking voltages.
Still another object of the present invention is to provide a conductivity modulated MOS structure with reduced latch up sensitivity which may be formed in an integrated circuit or as discreet devices.
An even further object of the present invention is to provide an SCR structure having an increased, controllable turn-off gain.
A still even further object of the present invention is to provide a diode structure having a lower turn-on voltage than a junction diode and a lower series resistance than a Schottky diode.
These and other objects of the invention are attained by providing a minority carrier diode and a majority carrier diode in the drain region with the minority carrier diode modulating the current path of the majority carrier diode. The diodes may be formed in a common surface of the drain region with the body and source region or may be formed on an opposed surface of the drain region. The minority carrier diode and the majority carrier diode may receive a common signal in which case the majority carrying diode should have a lower turn-on voltage than the minority carrying diode. The signal applied to the minority carrying diode should be less than the value which will produce latch up of the insulated gate field effect transistor structure. The minority carrier diode is positioned between the majority carrier diode and the body region. The majority diode may be formed as a Schottky diode or as a semiconductor junction diode.
Another embodiment is capable of current modulation using a minority carrier injecting diode and a separate drain contact. In this example, a drain contact is formed in the drain adjacent to the channel portion of the body. The anode of the minority carrier diode is formed in the drain region and is separated from the source region, formed in the body region, by the body contact. Here the insulated gate field effect transistor structure operates as a conventional transistor until a drain-to-source voltage greater than the voltage drop of the minority diode is reached. The diode begins to conduct and further increase of current flow will be through the diode. Since the source region is remote from the anode and separated by the body contact, very high anode current density can be handled without latch up.
An SCR structure having an increased, controllable turn-on gain is formed by providing a minority carrier diode and a majority carrier diode in the third layer of a four-layer device. The minority carrier diode is positioned between the second layer and the majority carrier diode and modulates the current path of the majority carrier diode.
A low turn-on voltage, low resistance diode is formed by providing a minority carrier junction in a substrate between the surface substrate contact and the majority carrier junction in the substrate. The majority carrier diode has a lower turn-on voltage and, thus, operates as a low turn-on diode until the voltage in the substrate reaches a point to which the minority carrier diode turns on. The minority carrier diode reduces the resistance by conductivity modulation.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.
FIG. 1 is a cross-sectional view of an insulated gate field effect transistor triac structure of the prior art.
FIG. 2 is a cross-sectional view of an insulated gate field effect transistor incorporating the principles of the present invention.
FIG. 3 is a cross-sectional view of an insulated gate field effect transistor with a punch-through shield incorporating the principles of the present invention.
FIG. 4 is a cross-sectional view of an insulated gate field effect transistor structure incorporating the principles of the present invention using a single diode.
FIG. 5 is a cross-sectional view of an insulated gate field effect transistor structure which is a modification of FIG. 4.
FIG. 6 is a cross-sectional view of an insulated gate field effect transistor incorporating the principles of the present invention using two semiconductor diodes.
FIG. 7 is a cross-sectional view of a vertical insulated gate field effect transistor incorporating the principles of the present invention.
FIG. 8 is a cross-sectional view of another vertical insulated gate field effect transistor incorporating the principles of the present invention.
FIG. 9 is a cross-sectional view of an SCR incorporating the principles of the present invention.
FIG. 10 is a cross-sectional view of a diode incorporating the principles of the present invention.
The basic insulated gate field effect transistor of the prior art including a diode connected in series with the drain to inject minority carriers is illustrated in FIG. 1. It includes an N-type drain region 10 in which a P body 12 is formed. An N+ source 14 is formed in the P body 12 and a gate 16 is formed over the portion of the body 12 between the source region 14 and the drain region 10 and is separated therefrom by a gate insulative layer 18. A P+ body contact 20 is formed in the body 12. A P+ anode 22 forms a junction diode with drain region 10. Although the anode region 22 of the diode introduces minority carriers and therefore increases the conductivity and reduces the on resistance, it also introduces a voltage drop. If a high enough signal is applied, the device latches on forming a parasitic SCR.
As an effort to maintain the reduced on resistance and voltage drop of the drain while reducing the latch sensitivity, the present invention provides, as illustrated in FIG. 2, an insulated gate field effect transistor including a minority and a majority carrier diode. In addition to the drain region 10, body region 12, source region 14, gate 16, body contact 20, and a semiconductor anode 22, a Schottky diode is formed. This diode is formed by a Schottky anode metal 24 on the surface of the drain region 10. For the example shown in FIG. 2, the Schottky diode injects only majority carriers, which are electrons in this example while the P+ anode injects holes. It should be noted that in P channel devices the majority injecting carriers would be holes although the minority injecting carriers would be electrons.
There are several ways in which the structure may be operated. The input signal may be connected to the Schottky anode 24 while a current is supplied to the semiconductor anode 22 sufficient to produce the desired modulation of the drain resistance but too small to cause latch up. In this way, large anode currents can be handled without latch up because the large currents are electron current flow injected into the drain by the Schottky. By positioning the minority carrier diode 22 between the majority carrier diode 24 and the body 12, better control of the modulation is achieved.
Although the anode 22 is shown as just between the majority carrier diode 24 and the body 12, the anode 22 may be a ring surrounding the Schottky diode 24. This would increase the Schottky diode breakdown voltage.
Another mode of operation depends upon the lateral disposition of the semiconductor anode between the Schottky anode 24 and the body 12. The two anodes are connected and current injected into the common node. The Schottky is made to have a lower built-in potential, and therefore lower turn-on voltage, than the P+-N diode. In this case, current will initially flow only through the Schottky then laterally through the N- drain to the gate induced channel on the body surface. A lateral voltage drop is developed between the two anodes in the N- by this flow. When the voltage drop equals the difference between the built-in voltages of the two diodes, the semiconductor anode will begin to conduct by injecting holes into the N-. The injected holes will reduce drain resistance by conductivity modulation.
As current is further increased, a balance will be maintained between the current flows through the two anodes. Enough current will flow through the P+ anode to reduce the N- resistance enough to hold the voltage difference between the two anodes at the value which balances their difference forward voltages. All other current will flow through the Schottky anode 24. If the source 14 and body 12 are tied together, the structure would be a three terminal device.
A higher current at onset of latch up is achieved because much of the total current flows by majority carriers injected by the Schottky anode 24. A lower offset is obtained because the Schottky has a lower turn-on voltage than the semiconductor diode. The ratio of current flow between the two anodes can be adjusted by changing the spacing between anodes or by changing their area ratio among other methods.
FIG. 3 illustrates a modification to the structure of FIG. 2 in which an N punch-through shield 26 has been added. The Schottky may be formed on the shield 24 as shown or on N drain material 10. A non-selective surface N region with field plates may also be used for the punch-through shield.
The structure of FIGS. 2 and 3 have the capability of blocking high reverse voltages, namely large negative anode-to-source voltage for an N channel or large positive cathode-to-source voltage for P channel devices. This is accomplished by using the step oxide field plate on the anode region 22 and the Schottky anode 24.
An improved structure which eliminates offset while retaining conductivity modulation is illustrated in FIG. 4. The device has a minority carrier diode on one side of the body and a conventional drain contact 30 on the other. Signal current is injected into both. When drain source voltage is less than a diode drop, current flows through the conventional MOS part of the device. When drain source voltage is greater than a diode drop, the anode begins to conduct and most further increase in device current flows through it. A feature of the structure of FIG. 4 is that the source region 14 is remote from the anode and separated from it by the body contact. This allows very high anode current density without latch up, but increases the voltage drop for the electron flow to the anode junction which is supplied by the source to the N drain by the gate induced channel.
A modification of the device of FIG. 4 is illustrated in FIG. 5. The source region is formed as a pair of source regions 14a and 14b in the body to region 12 with the body contact 20 therebetween. In addition to the original gate 16 over the channel region between the drain contact 30 and the source contact 14a, a second or anode gate 32 is formed over the body region 12 between the source contact 14b and the drain region 10 adjacent to the anode 22. The gate 32 is separated from the surface of the body 12 by a gate oxide 34.
Although the majority carrier diode has been illustrated in FIGS. 2 and 3 as including a Schottky diode, other majority diodes may be formed. As illustrated in FIG. 6, the majority diode is formed by a majority anode 36 being formed by P-- region in the N- drain 10. The notation of P-- relative to the N- drain region 10 indicates that the majority anode 36 has a lower impurity concentration than the drain region 10. It should be noted that while the P+ minority anode 22 and the P-- majority anode 36 or Schottky contact 24 are minority and majority carriers injectors in the N- drain regions, if the drain region is P type, minority and majority cathode regions would be minority and majority receptors although the diodes would still be minority and majority diodes operating as a primary signal source and a modulation signal.
In addition to the lateral insulated gate field effect transistor devices, the present invention is also applicable to vertical insulated gate field effect transistor devices as illustrated in FIGS. 7 and 8. The vertical device of FIG. 7 includes an annulus body 12' in which is formed an annulus source 14'. Semiconductor diode 22 and the Schottky diode 24 are formed on a surface of the drain region 10 opposite that in which the body region 12' and source region 14' are formed. In FIG. 8, the vertical insulated gate field effect transistor includes a vertical gate 16' on vertical insulative gate layer 18' extending from the surface through the source region 14 and the body region 12 substantially to the drain region 10. The minority diode having anode 22 and the majority diode having anode 36 are shown as semiconductor devices. An area of increased N+ impurities 10a, as illustrated by the dotted line in FIG. 8, is provided at the surface in which the minority anode 22 and majority anode 36 are formed.
If the two diodes of FIGS. 7 and 8 are tied together, the turn-on can be set by adjusting the areas of the two diode types so that the desired current ratio is achieved taking into account the higher current density of a low barrier height Schottky diode or P-- to an N majority carrier injecting diode to a minority injecting diode.
Although the description of the preferred embodiments so far have been directed to insulated gate field effect transistors, the principle is also applicable to silicon controlled rectifiers (SCR) as well as diodes. As illustrated in FIG. 9, the four-layer SCR device includes a first layer or cathode N+ region 14 formed in a second layer or P gate region 12 which is formed in a third layer or N- gate region 10. The fourth layer of the SCR structure includes the anode SCR contact 24 which forms the majority carrier diode. A minority carrier anode includes P+ region 22 formed in the third layer 10. Although the four regions are not layers, they are referred to as layers since an SCR is known generically as a four-layer device. A P+ gate contact region 20 is formed in the P gate 12. In the structure of FIG. 9, the gate turn-off gain is increased by the control of the amount of injected minority carriers. Since some of the device current is majority carriers provided by the majority carrier diode rather than all the current being from the minority carrier diode as in the conventional SCR turn-off gain control is provided. The various means for biasing the two diodes are described above for the insulated gate field effect transistor.
Another application of the two diode concept of the present invention is illustrated in FIG. 10 to provide a lower turn-on voltage than a PN junction diode and a lower series resistance than a Schottky diode. The diode structure includes an N- cathode region 10 having an N+ cathode contact 30, a majority carrier diode having Schottky contact 24 and a minority carrier diode having P+ anode region 22. The minority carrier injecting region 22 is placed between the substrate contact 30 and the majority injecting junction 24. The majority carrier diode 24 has a lower turn-on voltage than the minority carrier injection junction 22. In operation, when the two junctions are connected together, current flows initially through the majority carrier junction. When the voltage drop developed in the substrate between the two junctions by the lateral flow of majority carriers to the substrate contact 30 reaches the difference in turn-on voltage of the two junctions, the minority carrier junction 22 begins to conduct. The minority carriers injected into the substrate 10 reduces its resistance by conductivity modulation. In this way the low turn-on voltage of the majority carrier diode is combined with the low series resistance, and thus low diode voltage at high currents of the minority carrier diode in a single substrate.
From the preceding description of the preferred embodiments, it is evident that the objects of the invention are attained, and although the invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation. The spirit and scope of the invention are to be limited only by the terms of the appended claimed is.
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|U.S. Classification||257/138, 257/168, 257/E29.197, 257/141, 257/E29.047, 257/E29.115, 257/E29.338, 257/E29.066, 257/E29.195, 257/E29.037, 257/E29.201, 257/E29.198|
|International Classification||H01L29/872, H01L29/08, H01L29/739, H01L29/10, H01L29/417|
|Cooperative Classification||H01L29/7393, H01L29/7395, H01L29/7397, H01L29/0834, H01L29/1095, H01L29/872, H01L29/41716, H01L29/1016, H01L29/7391|
|European Classification||H01L29/08D2, H01L29/10C2, H01L29/739C, H01L29/10G, H01L29/739C2B2, H01L29/739B, H01L29/872, H01L29/739C2, H01L29/417C|
|Feb 19, 1985||AS||Assignment|
Owner name: HARRIS CORPORATION, MELBOURNE, FL 32919, A CORP OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:BEASOM, JAMES D.;REEL/FRAME:004371/0610
Effective date: 19850212
|Mar 4, 1991||FPAY||Fee payment|
Year of fee payment: 4
|Mar 3, 1995||FPAY||Fee payment|
Year of fee payment: 8
|Mar 12, 1999||FPAY||Fee payment|
Year of fee payment: 12
|Sep 27, 1999||AS||Assignment|
Owner name: INTERSIL CORPORATION, FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HARRIS CORPORATION;REEL/FRAME:010247/0043
Effective date: 19990813
|Nov 8, 1999||AS||Assignment|
Owner name: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT, N
Free format text: SECURITY INTEREST;ASSIGNOR:INTERSIL CORPORATION;REEL/FRAME:010351/0410
Effective date: 19990813