|Publication number||US4716313 A|
|Application number||US 07/058,617|
|Publication date||Dec 29, 1987|
|Filing date||Jun 3, 1987|
|Priority date||Jun 15, 1983|
|Also published as||DE3485234D1, EP0129217A2, EP0129217A3, EP0129217B1|
|Publication number||058617, 07058617, US 4716313 A, US 4716313A, US-A-4716313, US4716313 A, US4716313A|
|Inventors||Ryoichi Hori, Kiyoo Itoh, Jun Etoh|
|Original Assignee||Hitachi, Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (2), Referenced by (47), Classifications (14), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of application Ser. No. 620,894, filed on June 15, 1984, now abandoned.
The present invention relates to a pulse control circuit which is suitable for driving a capacitance load at high speed.
Reductions in the sustain voltage of elements which have resulted from the recent miniaturization of bipolar or MOS transistors have tended to reduce the operating voltages of integrated circuits. From the user's point of view, conventional supply voltages, such as supply voltages in units of 5 V, are desirable for ease of use. It is considered that means by which it will be possible to satisfy both the needs of the manufacturers of integrated circuits and the users is a reduction of the external supply voltage Vcc within the chips and the operation of miniaturized elements by a voltage VL which has been lowered thereby.
FIG. 1A is taken from U.S. patent application No. 368,162 applied for by the present Applicant. A miniaturized element 12a of FIG. 1B is used in an internal circuit a which determines the effective integration density of chips 10, and the remedy for the reduction in the voltage resistance resulting from miniaturization is to operate the element by a voltage VDP which is the external supply voltage Vcc reduced by a voltage limiter 30. However, it is usually easier to design a drive circuit b which uses a higher supply voltage and which includes, for example, an input-output interface, which does not contribute much to the integration density. Thus, a comparatively large element 12b, as shown in FIG. 1B, is used for the driving circuit b which is operated by applying Vcc thereto.
A chip is a single substrate on which memory, logic or other LSI devices are fabricated. In a memory LSI device, a from FIG. 1A is a memory array and its related circuits. On the other hand, in a logic LSI device, a is an area constructed of repeated cells making up the ROM or RAM area of a microcomputer. Details of embodiments of voltage limiters using this voltage limiter system are given in U.S. patent application Nos. 368,162 and 562,969.
When this kind of voltage limiter system is utilized for charging a capacitance load which has only a low voltage resistance in the circuit a, the output VDP of the voltage limiter 30 is supplied to the drain of a charging transistor as a supply voltage and, pulses of the same level as that of the external supply voltage Vcc are applied to the gate of the transistor, turning the transistor on.
In FIG. 2, a precharge circuit for a data line of a semiconductor memory is shown as an example of this type of circuit. In FIG. 2, charging transistors Q6, Q7 controlled by precharge pulse φP2 of a maximum level of Vcc charge data lines Do and Do to a voltage as large as the output voltage VDP of the voltage limiter 30. Numeral 1 denotes a memory cell array.
However, in this circuit, the equivalent internal resistance of the voltage limiter 30 is connected in series to the equivalent resistances of the charging transistors Q6 or Q7 when they are on, and thus it is necessary to make these resistances much smaller to enable charging at a higher speed when there is a larger capacitance load. For that purpose, the size of the transistors in the voltage limiter 30 and the transistors Q6, Q7 must be larger, and thus it can be understood that it is difficult to drive a large capacitance load faster when there must be a high degree of integration.
An object of the present invention is to provide a pulse drive circuit which is suitable for driving a large capacitance load at high speed.
In order to drive a capacitance load at a high speed without an undesirably large increase in the circuit size, a driving arrangement is provided to charge the capacitance load in accordance with a limited voltage. A voltage limiter is coupled to a supply voltage providing a predetermined limited voltage. A pulse generator is coupled to receive the limited voltage and to provide output pulses which are, in turn, limited in accordance with the output voltage of the voltage limiter. A driver is coupled between the supply voltage and the capacitance load, and is controlled by the output pulses of the pulse generator. In this way, the capacitance load is charged through the driver in accordance with the limited voltage. Since the voltage limiter is not arranged along a series connection between the driver and the capacitance load, the internal equivalent resistance of the voltage limiter does not detrimentally influence the resistance along the series connection.
FIG. 1A is a diagram of the chip structure of a conventional semiconductor circuit.
FIG. 1B is a diagram of an example of the structure of two transistors used in the chip of FIG. 1A.
FIG. 2 is a diagram of a precharge circuit for data lines of a semiconductor memory.
FIG. 3 is a circuit diagram of a first embodiment of the present invention.
FIG. 4 is a circuit diagram of a second embodiment of the present invention.
FIG. 5 is a graph of the output characteristic of the voltage limiter 30 used in the circuit of FIG. 4.
FIGS. 6A and 6B illustrate the high-voltage generation circuit (31c) used in the embodiment of FIG. 4.
FIG. 7 is a circuit diagram of a third embodiment of the present invention.
FIG. 8 is a graph of the output characteristic of the voltage limiter (30D) used in the circuit of FIG. 9.
FIG. 9 is a circuit diagram of a fourth embodiment of the present invention.
FIGS. 10A and 10B illustrate the voltage generation circuit (31C) used in the circuit of FIG. 8.
FIGS. 11A and 11B are circuit diagrams of two parts of a semiconductor memory of the present invention which are different from each other.
FIG. 12 is a circuit diagram of the voltage limiter (30E) used in the circuit of FIG. 11B.
FIG. 13 is a circuit diagram of the pulse-limiting circuit (G) of FIG. 11B.
FIG. 14 is a circuit diagram of the voltage converter circuit (H) of FIG. 11B.
FIG. 15 is a circuit diagram of a fifth embodiment of the present invention which discharges a charge from a capacitance load.
FIG. 16 is a circuit diagram of a sixth embodiment of a discharge circuit.
FIG. 17 is a graph illustrating conventional problems encountered when driving a capacitance load.
FIG. 3 shows a fundamental embodiment of the present invention. A signal φil whose amplitude is controlled by the operation of a pulse-generating circuit PG is input to a gate of a MOS transistor QL ', and a capacitance load CL connected to the source of the transistor is driven thereby.
The pulse-generating circuit PG inputs pulse φi of a maximum voltage equivalent to the supply voltage Vcc.
Details of this pulse-generating circuit PG and its operation are given in "Electronics" Mar. 24th, 1982, pp. 132-136. An outline thereof is provided below.
An inverted output of a driver 12 to which the input pulse φi is applied makes a MOS transistor QD discharge its gate voltage so that its electric potential changes from high to low. Simultaneously, a bootstrap capacitance (not shown) acts so that the gate voltage of a transistor QL is charged by a non-inverted output of the driver 12 so that its low potential becomes a high potential of at least the level of Vcc, turning the transistor QL on.
An internal supply voltage VDP which is different from the external supply voltage Vcc and is applied to the gate of a transistor QLL so that a voltage of VDP -VT is applied to the drain of transistor QL. Thus, the output φil rises from a low voltage of zero to the drain voltage VDP -VT of the transistor QL. VT denotes the threshold voltage of each transistor in this embodiment.
The external supply voltage Vcc is applied to the drain of transistor QL ', but the capacitance load CL is charged by a voltage of up to VDP -2VT which is equal to the high voltage VDP -VT of the pulse φil reduced by the threshold voltage VT of the transistor QL '. By suitably increasing the size of transistor QL ' alone, that is, by increasing the magnitude of W/L (channel width/channel length), it is possible to drive the capacitance load CL at high speed, however large CL is. Concrete details of circuits embodying the voltage limiter 30 are disclosed in U.S. patent application Nos. 368,162 and 562,969. One example of these will now be described with reference to FIG. 4. This embodiment removes the problem often encountered in the prior art that, when charging the capacitance load CL the voltage limiter and the charge-control transistors must all be large-sized transistors. When the voltage with which the capacitance load CL is charged is Vout (hereinafter, "signal voltage" denotes any voltage on the high electric potential side, without particular limitations), the voltage of the pulse φil is Vin and the threshold voltage of the transistor QL is VT, Vout is generally given by:
Vout =Vin -VT (1)
Accordingly, a control of the output voltage on the high electric potential side can be accomplished by controlling Vin which can be defined in response to the essential voltage Vout.
Thus for Vin it is necessary to generate a voltage which is higher than the required charge voltage by the voltage VT. For this purpose, the output voltage VDP of the voltage limiter 30 of FIG. 3 could be modified.
FIG. 4 discloses an embodiment in which the voltage of VDP -VT is applied to the capacitance load CL. FIG. 4 differs from FIG. 3 only in that a voltage limiter 30A is designed so that it outputs a voltage VDP +VT which is only VT higher than the output VDP of the voltage limiter 30 of FIG. 3. FIG. 4 shows a concrete example of the voltage limiter 30 which outputs VDP from a contact point between a resistor RLM and a series of n diodes D1 to Dn. The voltage limiter 30 outputs the voltage VDP of which has a characteristic as shown in FIG. 5 with respect to the external supply voltage Vcc. This characteristic shows that if the external supply voltage Vcc is less than V0, the output of the voltage limiter is equal to Vcc; and if it is greater than V0, the output thereof varies with a gradient of m which is less than 1. When the standard voltage is 5 V, V0 is selectively defined by a value which is less than 5 V; and when Vcc is 5 V, VDP can be determined to be, for example, 3.5 V by this characteristic.
V0 is equal to the external supply voltage when the n series-connected diodes D1 to Dn of FIG. 4 start to be turned on. The gradient m is defined by the ratio of the resistance RLM in series with the resistance of the group of diodes D1 . . . Dn when on.
Returning to FIG. 4, a high-voltage generation circuit 31 generates a voltage Vpp which is higher than the external supply voltage Vcc. This circuit will be described later with reference to FIGS. 6A and 6B.
In FIG. 4, two transistors Q103, Q101, which are arragned so that the drain of one is connected to the gate of other, and a resistance Rp are connected in series between an output terminal of the high-voltage generation circuit 31 and an output terminal of the limiter 30. Thus, the drain voltage of transistor Q103 is equal to VDP +2VT. Since this voltage VDP +2VT is applied to the gate of a transistor Q102 whose drain receives the external supply voltage Vcc, VDP +VT is applied to the gate of the transistor QLL in the pulse-generating circuit PG. Accordingly, the high electric potential of the pulse φil is equal to VDP and so a charging voltage of up to VDP -VT is applied to the capacitance load CL. The output voltage Vpp of the high-voltage generation circuit 31 is set by the formula:
Vpp ≧VDP +2VT
The high-voltage generation circuit 31 will now be described with reference to the circuit diagram thereof of FIG. 6A. A circuit Cp1 has a construction and operation such that pulse φB is applied through a charge-pump capacitor CB to a node between two transistors Qc1 and Qc2 arranged so that the source of Qc1 is connected to the gate of Qc2, and pulses higher than Vcc are generated. A circuit Cp2 also comprises of two transistors Qc '1 and Qc '2 connected in the same state as in circuit Cp1 and a charge-pump capacitor CB '. However, it differs from Cp1 in that pulse φB is generated. The sources of transistors Qc2 and Qc '2 for a wired OR. φB and φB, respectively are pulses of a certain period and inverses thereof, in a chip. The circuits for producing these pulses are not shown in the drawings for simplicity. Cp denotes a parasitic capacitance generated in the output wiring. Nodes N1 and N1 ' respectively of transistors Qc1 and Qc '1 of FIG. 6B are precharged to the voltage Vcc-VT. Each of the pulses φB and φB then reach Vcc during each of time bands T1, T2, respectively, when the corresponding nodes N1 and N1 ' are raised to 2Vcc-VT during T1 and T2 by the capacitive coupling of charge-pump capacitors CB and CB ', respectively. This voltage appears as an output voltage Vpp through transistors Qc2, Qc2 ' but the voltage is reduced by the threshold voltage VT of the transistors Qc2, Qc2 ' and thus Vpp is given by the formula Vpp =2(Vcc-VT). As a result, the output Vpp becomes a d.c. voltage which is greater than Vcc.
Since the high-voltage generation circuit 31 receives the charges of the capacitors CB, CB ' output during both time bands T1, T2, the ability of the circuit to supply charge is great, and a ripple noise in its output Vpp is low.
FIG. 7 shows an embodiment which can charge the capacitance load CL to the voltage VDP. The circuit shown in FIG. 7 differs from that of FIG. 4 in that a voltage limiter 30B is constructed so that the output voltage VDP of the voltage limiter 30 is raised to VDP +2VT. Namely, the circuit in FIG. 7 differs from that of FIG. 4 in that the drain and gate of a transistor Q104 are connected in series to transistors Q101 and Q103 and high voltages VppA and VppB generated by voltage generation circuits 31A and 31B are applied to the drain of a transistor Q102 and a resistor Rp, respectively.
The gate voltage of the transistor Q103 is made to be VDP +3VT by activating the transistor Q104. Thus, a voltage which is higher by VT than that in the circuit of FIG. 4 is applied to the gates of transistors QLL, QL ', and the capacitance load CL is charged to the voltage VDP.
In addition, the high-voltage generation circuit 31B supplies the transistor QLL with a voltage VppB which value is VDP +2VT, in order to raise the gate voltage of the transistor QL, to VDP +VT which is higher than that in FIG. 4.
The output VppA from the high-voltage generation circuit 31A must be greater that the drain voltage VDP +3VT of the transistor Q103.
Ordinary integrated circuits are subjected to aging tests after the final production step in order to ensure their reliability. These aging tests are designed to detect any transistor in which basic problems are likely to occur because of a failure of its gate oxide film, and are performed by deliberately applying to each transistor in the circuit a voltage which is higher than those encountered during normal usage. It is necessary to apply to each element a voltage which is slightly lower than the destructive voltage of a normal element in order to improve the chances of finding failures with these aging tests. For an integrated circuit chip which is so constructed that a supply voltage is supplied through a voltage limiter within the chip, examples which can accomplish these aging tests, even for the circuit part a of FIG. 1 which has a low voltage resistance, are disclosed in U.S. Patent Application Nos. 368,162 and 562,969.
It is desirable that the present invention can accomplish these aging test. In the embodiments thereof shown in FIGS. 3, 4 and 7, the voltage limiter 30 varies the output voltage VDP in accordance with the characteristic of FIG. 5. Thus, if the gradient m is selected to have a certain magnitude, the output VDP can be charged to the voltage required for the aging tests by varying the magnitude of Vcc. This change means that the voltage applied to the load capacitance CL can be varied, and thus the aging tests can be accomplished for the load capacitance CL.
However, when Vcc is near the normal operating voltage 5 V, it is better not to change VDP much if Vcc is varied. For this purpose, it is desirable to minimize the gradient m of the characteristic of FIG. 5 as far as possible. Therefore, in the voltage limiter 30 of FIGS. 3, 4 and 7, when the external voltage Vcc is greater than Vo', which is greater than the normal operating voltage 5 V, it is desirable, as shown in FIG. 8, to generate VDP so that its characteristic varies with respect to the voltage Vcc above the voltage Vo with a gradient m' that is greater than the gradient m when Vcc is between the voltages Vo and Vo'.
FIG. 9 shows an embodiment in which the capacitance load CL is supplied with a voltage which varies in accordance with the characteristic of FIG. 8.
FIG. 9 differs from FIG. 7 in that a voltage limiter 30D is used instead of the voltage limiter 30 of FIG. 7. The circuit of the voltage limiter 30D is disclosed in U.S. Patent Application Nos. 368,162 and 562, 969. This voltage limiter 30D ouputs a voltage VDP which has the characteristic shown in FIG. 8. Namely, in FIG. 9, VG (for example, Vcc+2VT) is applied to the gate of a transistor Qo of the voltage limiter 30D. The magnitude of the voltage VG is selected so that it can turn Qo on. When the magnitude of the external supply voltage Vcc is between 0 and V0, a transistor Ql is turned off, and thus the output VDP is equal to Vcc. When the external supply voltage Vcc is between V0 and V0 ', the transistor Ql is turned on because transisors Q1, Qm are on. Accordingly, the output VDP varies according to a gradient m (m<1 ) determined by the conductance ratio of transistors Qo and Ql.
When the external supply voltage Vcc is above V0 ', a transistor Ql ' is turned on because transistors Q1 ' and Qn ' are on. consequently, the output is defined by a gradient m' (m'>m) which is also determined by the ratio of conductance of transistors Qo and Ql, and also by the sum of the conductances of the transistors Qo and Ql '.
The circuit shown in FIG. 9 differs from that of FIG. 7 in that a high voltage Vppc generated by a high-voltage generation circuit 31C (which will be described later with reference to FIGS. 11A and 11B), is applied to the drain of the transistor QLL.
The voltage Vppc is selected to have a magnitude greater than that of the gate voltage VDP +VT of the transistor QLL even if that gate voltage varies. Thus, in the same way as in the circuit of FIG. 7, the voltage Vppc is applied to the capacitor CL even if the magnitude of VDP varies. As a result, the aging tests of the capacitance load CL can be accomplished by varying Vcc. It is obvious that the voltage limiter 30C of FIG. 9 can be used instead of the voltage limiter 30 of FIGS. 3, 4 and 7, and it also goes without saying that the high-voltage generation circuits 31A and 31B of FIG. 9 must generate output voltages VppA and VppB that are higher than VDP +3VT and VDP +2VT respectively, even if Vcc varies.
The high-voltage generation circuit 31C will now be described. A pulse-generating circuit PG', shown in FIG. 10A, differs from the pulse-generating circuit PG of FIG. 3 only in that it does not have the transistor QLL. Pulse φBB output from the pulse-generating circuit PG' are connected to the source of a transistor QBB by a bootstrap capacitor CBB. The drain and gate of the transistor QBB are connected to the external supply voltage Vcc.
The operation of this voltage generation circuit 31C will now be described with reference to FIG. 10B. An output Vppc is precharged to the voltage VCC -VT by the transistor QBB. When an input pulse φi of the pulse generation circuit PG' rises, an output pulse φBB starts to rise simultaneously with an output pulse φil of the pulse generation circuit PG (FIG. 9). The pulse φBB rises as far as Vcc, and φil rises to VDP +VT. In response to the rise of the pulse φBB, Vppc rises because of the capacitive coupling of CBB. The magnitude of CBB is such that the maximum value of Vppc becomes the voltage necessary for obtaining the source voltage VDP +VT of a transistor QLL (FIG. 9), that is, a voltage higher than VDP +VT. It is better to employ the voltage generation circuit 31C than a circuit which outputs Vppc continuously, because Vppc is generated only when a pulse φil is generated, and so the power consumption is reduced.
This means that the high-voltage generation circuits 31A and 31B can be constructed of the same circuit.
FIGS. 11A and 11B show an embodiment in which the present invention is applied to MOS dynamic memory with a single -transistor type memory cell. In these drawings, a group of circuits 1 enclosed within a dot-dash line comprise a memory array circuit. A group of circuits 2 enclosed within a dot-dot-dash line comprise circuits (direct peripheral circuits) which control the memory array circuit and amplify signals from memory cells. A group of circuits 3 enclosed within a triple-dot dash line denotes circuits (indirect peripheral circuits) which supply signals to the direct peripheral circuits, amplify memory signals from the memory array circuit, and write memory signals into the memory array circuit.
In the memory array 1, capacitors C1 and C2, transistors Q8, Q9 and Q11, Q12 represent dummy cells. Capacitors CM1, CM2 . . . CMn-1, CMn and transistors QM1, QM2 . . . QMn-1, QMn each form memory cells. Pulse φp3 applied to the gates of transistors Q9 and Q10 are used to discharge the capacitors C1, C2 before reading, and is generated in a pulse-generating circuit 33.
A denotes a word driver circuit which generates word-selecting signals from address signals.
When a transistor QD1 or QD2 on a word line W1 or W2, respectively, is selected, the word driver circuit A raises the gate voltage of a transistor Q16 on a dummy word line WD1 to a higher level, and outputs a signal φxl to a dummy word line WD1 and the appropriate word line W1 or W2.
On the other hand, when a transistor QDn-1 or QDn on a word line Wn-1 or Wn, respectively, is selected, a transistor Q17 on a dummy word line WD2 is selected.
Transistors Q21, Q22 connect I/O and I/O lines to data lines D and D by pulses φ4.
Transistors Q1, Q2 form part of a sense amplifier and transistors Q3, Q4 act as switches to connect data lines to the sense amplifier.
Transistors Q6, Q7 are used for precharging and will be described later. A transistor Q5 is used for switching between the short-circuiting of data lines Do, Do '.
A transistor Q18 is used for precharging a line l, and transistors Q19, Q20 are used for driving the sense amplifier.
A voltage limiter 30E outputs two voltages VL1 and VL2 through a circuit shown in FIG. 12. This circuit is formed by connecting the gate of the transistor Q104 of the voltage limiter 30C of FIG. 9 to the transistor Q102 of FIG. 4.
Each transistor is constructed to as to have a threshold voltage VT of 0.5 V, and a voltage limiter 30D is constructed so that VDP is 3.5 V when the external supply voltage Vcc is 5 V. Thus, the outputs VL1 and VL2 are 4.0 V and 4.5 V, respectively, when Vcc is 5 V.
The voltage limiter 30E can generate these two voltage magnitudes within a single circuit. Thus, the area of the semiconductor chip can be reduced, and fluctuations between VL1 and VL2 can be made smaller because the voltage limiter 30E operates on the basis of the same output VDP of the voltage limiter 30D.
In FIG. 11B, F denotes a circuit which receives a precharge signal φP2 (5 V) and also VL2 (4.5), and which outputs a precharge signal φP2l whose voltage is VT less than VL2. F is composed of a circuit which is identical to the pulse-generating circuit PG of FIG. 9.
The data lines D, D and a common source terminal of the sense amplifier composed of the transistors Q1, Q2 is precharged to a voltage equal to VL2 reduced by only the threshold voltage VT, by transistors Q6, Q7 and Q18 to the gates of which pulses are applied.
For example when the external supply voltage Vcc is 5 V and the threshold voltage is 0.5 V, the precharge voltage is 3.5 V.
Since there are numerous data lines within a memory, the total capacitance thereof is fairly large. However, according to the present invention, these lines can be precharged to a voltage which is lower than Vcc at high speed.
In order to prevent any differences in data line voltages caused by the difference between the threshold voltages of transistors Q6 and Q7, the gate voltage φP1 of Q5 can be made higher than φP2 l, transistor Q5 is can be turned on to short-circuit lines D and D.
I/O, IO lines are common data input and output lines connected to a plurality of data lines.
In FIG. 11B, B denotes a pulse-generating circuit and C denotes another pulse-generating circuit which inputs write data Din and generate pulses din, din which are complementary to each other.
Numeral 33 denotes a circuit which inputs external control pulse signals at the voltage Vcc and generates pulses such as φP1, φP2, etc.
In FIG. 11B, G denotes a circuit which receives a signal φx of a voltage amplitude of 5 V and also VL2 (4.5 V), and which outputs a signal φX l of the same voltage amplitude as VL2. This circuit, shown in FIG. 13, is well-known and is disclosed in U.S. patent application No. 368162 wherein it is described as a circuit for converting a signal amplidute, employing a self-bootstrapping effect. This signal φx l becomes a word line signal of a memory cell.
In this embodiment, the present invention is not applied to the driving circuit G for word lines W1 . . . Wn. That is the reason why, since only one word line should be selected and the capacitance thereof is small, the driving speed is made much faster by the circuit G. However, a component in which the present invention is applied must charge all the data lines at once so that the load on it is heavy, and its speed is must therefore be made slower by such means as the driving circuit G. If a data line is charged according to the present invention, it is clearly impossible to make the speed faster than the speed obtained when only one word line is charged by the driving circuit G. However the present invention is suitable for precharging a large capacitance load such as several data lines, etc., since high-speed charging is not needed.
In FIG. 11B, H denotes a voltage converter circuit which receives VL1 (4.0 V) and Vcc(5 V), and which generates a set up d.c. voltage of Vcp (3.5 V). As shown in FIG. 14, it is composed of a so-called source-follower transistor Qss which inputs Vcc through its drain and VL1 through its gate, and outputs Vcp from its source. It is possible to stabilize the operation of the circuit by inserting a large resistance Rss between an output terminal and ground, and by passing a small current therethrough, as shown in FIG. 14. In the Figure, Vcp is a precharge voltage supplied to the I/O and I/O lines, or it is a writing voltage in the writing circuit composed of transistors Q23 to Q26, and is set to 3.5 V, equal to the data line voltage.
In order to precharge the I/O, I/O lines, a conventional method of inputting the controlled voltage Vcp to the drains of transistors Q28, Q29 is employed. However, in the same way as in the precharging means for data lines, it is possible to employ the method of controlling the voltages of the I/O, I/O lines at a predetermined magnitude by applying voltage-controlled pulse signals within the chip to the gates of the transistors Q28, Q29. The I/O, I/O lines can be precharged as fast as the data lines, so the present invention should be applied thereto. A circuit such as that shown in FIG. 12 is suitable for this purpose because it has a small capacitance and a convenient layout.
Circuits for discharging the capacitance load are shown in FIGS. 15 and 16.
FIG. 15 shows an embodiment in which a signal φil, an inversion of the signal φil of FIG. 3, is input to the gate of a transistor Q'D, and an output can be extracted from the drain thereof. In this embodiment, the inverted signal φil is output and the capacitance load C'L is driven on the basis of the driving ability of a transistor QD " defined by its W/L ratio. Thus, in the same way as in the embodiment of FIG. 3, any size of driving ability can be obtained by selecting a suitable value of W/L.
FIG. 16 shows an embodiment in which a push-pull type of buffer circuit is constructed from two of the pulse-generating circuits PG of FIG. 3 which form an inverted signal and apply it and the original signal to the gates of transistors QL ", QD ". φi l is input to QL " and the inverted signal φil of φil is input to QD ". An output φo " therefrom is a signal of the same phase as φil at a voltage controlled by the voltage of φil. In the present embodiment, the rise term of φil of φo " and is output on the basis of the driving ability of transistor QL " determined by the ratio W/L, and the fall term thereof is output according to that of transistor QD ". The driving ability required for each section can be easily obtained so that the capacitance load CL can be driven at high speed.
Each of these embodiments have been described using n-channel MOS transistors as examples, but p-channel MOS transistors can be employed if all the potential relationships are reversed. For example, if p-channel MOS transistors are used for the pulse-generating circuit and the supply voltage is -5 V (the circuit operates within the range of -5 V to 0 V), the circuit can be operate under conditions in which -5 V is applied to the drain of transistor QL " and 0 V (ground) is applied to the source of transistor QD ". In this case, the output voltage is given by the formula Vout =Vin -VT, in the same way as in formula (1), when the voltage of the input φil is Vin ; so that if, for example, Vin is -4 V and VT is -0.5 V (p-channel transistors have negative threshold voltages), Vo =-4-(-0.5)=-3.5 V. This means that the magnitude of Vin can control Vout. If an operating range of from 0 V (corresponding to the previous -5 V) to 5 V (corresponding to the previous OV) is wanted, the whole range can be shifted intact in the positive direction by 5 V. The drain of transistor QL " can be set to OV and that of transistor QD " to 5 V so that Vin =1 V. The output voltage Vout in this case is 1.5 V (a signal inverted by 1.5 V on the basis of +5 V). Both n-channel and p-channel MOS transistors are used for in a CMOS type of LSI device, and any of the above embodiments can be used therein, according to the purpose of the device. Bipolar transistors can be used instead of MOS transistor, the same operations as those of a MOS transistor can be accomplished by a circuit in which the collector, emitter and base of a bipolar transistor replace the drain, source and gate of a MOS transistor, respectively.
When this discharge circuit is used together with the voltage limiter 30 with the characteristics of FIGS. 4 and 9, the following effect is obtained, in the same way as in the charging circuit of FIG. 3. The amplitude of the voltage of the pulse signal applied to the gates of the transistors QD " (in FIGS. 15 and 16) and QL " (in FIG. 16) follows the curve of FIG. 5 when the external supply voltage Vcc is higher or lower than Vo, to control the operating speeds of the transistors QD ", QL ".
For example, in the transistor type of dynamic memory shown in FIGS. 11A and 11B, even when the external supply voltage Vcc is varied in order to stabilize the memory operations between the memory array 1 and the direct peripheral circuits 2 and the indirect peripheral circuits 3, it is necessary to maintain the matching between the operating speeds of each of the circuits.
However, when not using a voltage limiter such as that of FIGS. 5 and 8, in which the gradient m is controlled so that it is less than the variation in the external supply voltage Vcc, the operating speed depends on the operating and manufacturing conditions because each circuit has a different operating mode, so that it is difficult to maintain this matching. In particular in recent years, the wiring resistances within the memory array circuit 1, the direct peripheral circuits 2, etc., have increased because of the increased integration of memories, and also the characteristics of MOS transistors make it more difficult to match them to the circuits which determine the operating speed.
This problem is very important, particularly when the external supply voltage Vcc varies. FIG. 17 illustrates this state, with reference to an example in which a signal 101a must be generated when the waveform of a signal 100a has fallen below the voltage VcrT. This is equivalent to the relationship between the discharge speed (100a) for the data lines Do, Do during read-out and the signal φ4 (101a) for extracting those signals onto the I/O line. 100b denotes the discharge speed for the data lines Do, Do when the external supply voltage Vcc drops. Since the discharge speed for a data line is mainly controlled by its wiring resistance, the time taken for discharge as far as the voltage VcrT hardly varies in comparison with the signal waveform of 100a in a memory array in which the integration density and wiring resistance have been increased. However, since φ4 (100a) generated by the peripheral circuits is usually determined by the characteristics of several MOS transistors, the time taken for its generation is greatly delayed, as shown by the signal waveform 101b, when the external supply voltage Vcc drops.
In contrast, if an attempt is made to reduce the delay in the generation of the signal waveform 101b when the external supply voltage Vcc is low, the signal waveform 101b is generated earlier than that when the signal waveform 100b reaches VcrT when the external supply voltage is high.
Thus, if one of the circuits shown in FIGS. 9, 15 and 16 is employed as a circuit controlling the delay in the signal waveform 101, the delay in the generation of the signal waveform due to variations in the external supply voltage Vcc can be eliminated.
This means that, since variations in the voltage output by the voltage limiter 30 are smaller than those in the external supply voltage Vcc, and the operating speeds of the transistors QL ', QD ", QL " (FIGS. 9, 15 and 16) hardly vary, the signal waveform 101b can be generated earlier, as shown by the wave form 101b'.
Accordingly, it is possible to realize a memory which can operate stably with no delaying in its access time.
The memories of FIGS. 11A and 11B have been described by way of example, but this method can be applied to any other type of memory with the same objectives, without any modification.
As stated above, details of the present invention have been given in accordance with various embodiments thereof, but the potential application of the present invention should not be limited to these embodiments. For example, the present invention can be employed in LSI devices other than memory circuits. It can also be employed in LSI devices which use transistor other than n-type MOS transistors.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3932773 *||Jul 20, 1973||Jan 13, 1976||Jakob Luscher||Control system for periodically energizing a capacitive load|
|US4090096 *||Mar 29, 1977||May 16, 1978||Nippon Electric Co., Ltd.||Timing signal generator circuit|
|US4441035 *||Oct 5, 1981||Apr 3, 1984||Mitel Corporation||CMOS Turn-on circuit|
|US4451745 *||Dec 8, 1980||May 29, 1984||Fujitsu Limited||Address buffer circuit with low power consumption|
|US4469959 *||Mar 15, 1982||Sep 4, 1984||Motorola, Inc.||Input buffer|
|US4475050 *||May 5, 1983||Oct 2, 1984||Motorola, Inc.||TTL To CMOS input buffer|
|US4482824 *||Jul 12, 1982||Nov 13, 1984||Rockwell International Corporation||Tracking ROM drive and sense circuit|
|US4494015 *||Feb 8, 1982||Jan 15, 1985||Siemens Aktiengesellschaft||Pulse enhancement circuit for digital integrated circuit|
|US4499387 *||Dec 3, 1982||Feb 12, 1985||Tokyo Shibaura Denki Kabushiki Kaisha||Integrated circuit formed on a semiconductor substrate with a variable capacitor circuit|
|US4555642 *||Sep 22, 1983||Nov 26, 1985||Standard Microsystems Corporation||Low power CMOS input buffer circuit|
|US4584491 *||Jan 12, 1984||Apr 22, 1986||Motorola, Inc.||TTL to CMOS input buffer circuit for minimizing power consumption|
|US4585955 *||Nov 30, 1983||Apr 29, 1986||Tokyo Shibaura Denki Kabushiki Kaisha||Internally regulated power voltage circuit for MIS semiconductor integrated circuit|
|US4626704 *||Apr 19, 1985||Dec 2, 1986||Ricoh Company, Ltd.||Voltage level converting circuit|
|US4631426 *||Jun 27, 1984||Dec 23, 1986||Honeywell Inc.||Digital circuit using MESFETS|
|JPS57130294A *||Title not available|
|1||Dingwall, "TTL to CMOS Buffer Circuit", RCA Technical Notes, No. 1114, pp. 1-3, Jun. 11, 1975.|
|2||*||Dingwall, TTL to CMOS Buffer Circuit , RCA Technical Notes, No. 1114, pp. 1 3, Jun. 11, 1975.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4843253 *||Dec 15, 1987||Jun 27, 1989||Sgs Microelettronica Spa||Monolithically integratable circuit for the generation of extremely short duration current pulses|
|US4853560 *||Jan 27, 1988||Aug 1, 1989||Hitachi, Ltd.||Logic circuit and semiconductor integrated circuit device capable of operating by different power supplies|
|US4943952 *||Dec 27, 1988||Jul 24, 1990||Nec Corporation||Semiconductor memory circuit with improved bit lane precharge circuit|
|US4952825 *||Mar 13, 1989||Aug 28, 1990||Nec Corporation||Semiconductor integrated circuit having signal level conversion circuit|
|US5121007 *||Apr 29, 1991||Jun 9, 1992||Nec Corporation||Step-down unit incorporated in large scale integrated circuit|
|US5150188 *||Nov 30, 1990||Sep 22, 1992||Kabushiki Kaisha Toshiba||Reference voltage generating circuit device|
|US5157280 *||Feb 13, 1991||Oct 20, 1992||Texas Instruments Incorporated||Switch for selectively coupling a power supply to a power bus|
|US5194762 *||Mar 26, 1990||Mar 16, 1993||Kabushiki Kaisha Toshiba||Mos-type charging circuit|
|US5214602 *||Apr 5, 1991||May 25, 1993||Mosaid Inc.||Dynamic memory word line driver scheme|
|US5227673 *||Nov 13, 1990||Jul 13, 1993||Vlsi Technology, Inc.||Differential output buffer with feedback|
|US5276356 *||May 21, 1992||Jan 4, 1994||Kabushiki Kaisha Toshiba||High speed output circuit having current driving capability which is independent of temperature and power supply voltage|
|US5537067 *||Mar 11, 1994||Jul 16, 1996||Texas Instruments Incorporated||Signal driver circuit operable to control signal rise and fall times|
|US5751643 *||Mar 6, 1996||May 12, 1998||Mosaid Technologies Incorporated||Dynamic memory word line driver|
|US5907251 *||Nov 22, 1996||May 25, 1999||International Business Machines Corp.||Low voltage swing capacitive bus driver device|
|US5933029 *||Apr 28, 1997||Aug 3, 1999||Kabushiki Kaisha Toshiba||Semiconductor integrated circuit device comprising a bias circuit, a driver circuit, and a receiver circuit|
|US6013958 *||Jul 23, 1998||Jan 11, 2000||Lucent Technologies Inc.||Integrated circuit with variable capacitor|
|US6037805 *||Mar 29, 1999||Mar 14, 2000||Kabushiki Kaisha Toshiba||Integrated circuit device having small amplitude signal transmission|
|US6061277 *||Jul 27, 1998||May 9, 2000||Mosaid Technologies Incorporated||Dynamic memory word line driver scheme|
|US6125075 *||Oct 9, 1998||Sep 26, 2000||Hitachi, Ltd.||Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions|
|US6198339 *||Sep 17, 1996||Mar 6, 2001||International Business Machines Corporation||CVF current reference with standby mode|
|US6212591||Apr 2, 1999||Apr 3, 2001||Cradle Technologies||Configurable I/O circuitry defining virtual ports|
|US6278640 *||Apr 13, 2000||Aug 21, 2001||Mosaid Technologies Incorporated||Dynamic memory word line driver scheme|
|US6363029||Feb 18, 2000||Mar 26, 2002||Hitachi, Ltd.||Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions|
|US6456152 *||May 4, 2000||Sep 24, 2002||Hitachi, Ltd.||Charge pump with improved reliability|
|US6580654||Jan 24, 2002||Jun 17, 2003||Mosaid Technologies, Inc.||Boosted voltage supply|
|US6603703||Jul 31, 2001||Aug 5, 2003||Mosaid Technologies, Inc.||Dynamic memory word line driver scheme|
|US6614705||Mar 28, 2001||Sep 2, 2003||Mosaid Technologies, Inc.||Dynamic random access memory boosted voltage supply|
|US6703891||Jun 26, 2002||Mar 9, 2004||Hitachi, Ltd.||Charge pump with improved reliability|
|US6906575||Aug 21, 2003||Jun 14, 2005||Renesas Technology Corp.||Semiconductor integrated circuit device|
|US6970391||May 20, 2003||Nov 29, 2005||Renesas Technology Corporation||Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions|
|US6980448||Jun 17, 2003||Dec 27, 2005||Mosaid Technologies, Inc.||DRAM boosted voltage supply|
|US7002856||May 20, 2005||Feb 21, 2006||Renesas Technology Corporation|
|US7038937||Mar 2, 2004||May 2, 2006||Mosaid Technologies, Inc.||Dynamic memory word line driver scheme|
|US7042276||Jun 13, 2005||May 9, 2006||Renesas Technology Corp.||Charge pump with improved regulation|
|US7227373 *||Dec 3, 2004||Jun 5, 2007||Micron Technology, Inc.||On-chip substrate regulator test mode|
|US7525332||Feb 21, 2007||Apr 28, 2009||Micron Technology, Inc.||On-chip substrate regulator test mode|
|US7535749||Mar 30, 2006||May 19, 2009||Mosaid Technologies, Inc.||Dynamic memory word line driver scheme|
|US8023314||Mar 16, 2009||Sep 20, 2011||Mosaid Technologies Incorporated||Dynamic memory word line driver scheme|
|US20030201817 *||May 20, 2003||Oct 30, 2003||Hitachi, Ltd|
|US20040004512 *||Aug 21, 2003||Jan 8, 2004||Hitoshi Tanaka||Semiconductor integrated circuit device|
|US20040037155 *||Jun 17, 2003||Feb 26, 2004||Mosaid Technologies, Incorporated||Dynamic memory word line driver scheme|
|US20050093612 *||Dec 3, 2004||May 5, 2005||Micron Technology, Inc.||On-chip substrate regulator test mode|
|US20050237102 *||Jun 13, 2005||Oct 27, 2005||Hiloshi Tanaka||Semiconductor integrated circuit device|
|US20060028899 *||Apr 25, 2005||Feb 9, 2006||Mosaid Technologies Incorporated||DRAM boosted voltage supply|
|US20070146001 *||Feb 21, 2007||Jun 28, 2007||Micron Technology, Inc.||On-chip substrate regulator test mode|
|EP0805557A2 *||Apr 30, 1997||Nov 5, 1997||Kabushiki Kaisha Toshiba||Semiconductor integrated circuit device|
|EP0805557A3 *||Apr 30, 1997||Apr 7, 1999||Kabushiki Kaisha Toshiba||Semiconductor integrated circuit device|
|U.S. Classification||326/80, 365/189.16, 327/541, 365/203, 365/230.06|
|International Classification||G11C11/419, G11C11/401, H03K19/017, H03K19/0185, G11C11/409|
|Cooperative Classification||H03K19/018507, H03K19/01707|
|European Classification||H03K19/017B, H03K19/0185B|
|Apr 23, 1991||FPAY||Fee payment|
Year of fee payment: 4
|Apr 3, 1995||FPAY||Fee payment|
Year of fee payment: 8
|Jun 1, 1999||FPAY||Fee payment|
Year of fee payment: 12