|Publication number||US4724433 A|
|Application number||US 06/796,755|
|Publication date||Feb 9, 1988|
|Filing date||Nov 12, 1985|
|Priority date||Nov 13, 1984|
|Publication number||06796755, 796755, US 4724433 A, US 4724433A, US-A-4724433, US4724433 A, US4724433A|
|Inventors||Hiroshi Inoue, Shinichi Yamashita|
|Original Assignee||Canon Kabushiki Kaisha|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (67), Classifications (9), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a matrix-type image display panel, particularly a high density display panel using an active matrix, and a method for driving the same using specific type of switching pulses applied to a sample-and-hold circuit.
FIGS. 1 and 2 show a conventional sample-and-hold (S/H) circuit, and the switching and clock pulses therefor, respectively. In FIG. 1, reference numeral 1 denotes a shift register for driving an analog switching element 2 such as a thin film transistor (TFT) and reference numeral 3 denotes a capacitor for holding an image signal.
Clock pulses shown in FIG. 2 are inputted to the shift register 1 and switching pulses ○1 - ○4 also shown in FIG. 2 are supplied to respective analog switching elements 2. The analog switching elements 2 are turned ON by these switching pulses, whereby information signals (image signals) are sampled-and-held in capacitors 3. As shown in FIG. 2, the conventionally used switching pulses serially applied to different analog switching elements are composed of such time-serially applied pulses or pulse trains that they are different only in phase and do not overlap each other in a same pulse duration T.
The switching pulses used in this type of driving method are required to have a frequency of f×n×m wherein f denotes a frame frequency, n denotes the number of vertically arranged picture elements and m denotes the number of horizontally arranged picture elements, and the frequency of the clock pulses amount to twice as many as that of the switching pulses.
As a result, even when relatively few picture elements are used, e.g., n=240 and m=160, a clock pulse frequency amounts to above 4.6 MHz. Further, when the number of picture elements is increased, e.g., to n=480 and m=480, in response to the requirement for a high element density in recent years, the required frequency of clock pulses is above 27.6 MHz, so that driving with a C-MOS (complementary MOS) -type shift register as a high-speed shift register becomes impossible. As a result, there is posed a serious restraint to minimization of power consumption and cost reduction of the display apparatus.
A principal object of the present invention is, in view of the problems as mentioned above, to provide a matrix-type display panel and a driving method therefor adapted to suppress the increase in clock pulse frequency in response to an increase in the density of picture elements and allow the use of a C-MOS type shift register, so that low power consumption and cost reduction of the display apparatus are realized.
According to an aspect of the present invention, there is provided a driving method for a matrix-type display panel of the type comprising a display panel having a plurality of scanning lines, a plurality of data lines and a plurality of picture elements disposed at each intersection of the scanning lines and data lines, and analog switching elements for sampling-and-holding information signals which are applied to the data lines in synchronism with scanning signals applied to the scanning lines; the driving method comprising: applying such switching pulses to the analog switching elements that time-serial pulses among them are shifted in phase from each other and overlap each other in the same duration.
These and other objects, features and advantages of the present invention will become more apparent upon a consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings.
FIG. 1 is a diagram of a conventional sample-and-hold circuit;
FIG. 2 shows timing clock pulses and switching pulses applied to the shift register shown in FIG. 1;
FIGS. 3A and 3B show waveforms of switching pulses applied according to the invention;
FIG. 4 is a circuit diagram according to a first embodiment of the invention;
FIG. 5 shows waveforms of switching pulses applied in the first embodiment;
FIG. 6 is a circuit diagram according to a second embodiment of the invention;
FIG. 7A shows waveforms of timing clock pulses applied to respective shift registers and FIG. 7B shows waveforms of switching pulses supplied from respective shift registers, respectively used in the second embodiment; and
FIG. 8 is a circuit diagram illustrating an active matrix-type display panel according to the invention.
A sample-and-hold circuit is operated for storing and transferring image-signals supplied to horizontally arranged picture elements of an active matrix-type image display apparatus based on controlling signals from a shift register. According to the present invention, switching pulses supplied time-serially from a shift register to analog switching elements of a sample-and-hold circuit are caused to shift by an arbitrary amount of difference (e.g., 45°, 90°, etc.) with each other and overlap each other in a same period or duration, whereby an available periods for changing the sample-and-hold circuit are increased.
FIGS. 3A and 3B show states where the above mentioned pulses are supplied to analog switching elements of a sample-and-hold circuit. FIGS. 3A and 3B show cases where time-serially supplied pulses shift in phase by 90° with each other and overlap each other in a same cycle or duration. Similar image data are applied to respective analog switching elements concerned during the overlapped period. However, when the pulses are of high speed as shown in FIG. 3A, an effective data period is attained in the latter period of the pulse because of its large rise time, so that the image data during a former overlapping half period of the pulse does not have a substantial effect. Furthermore, even when the pulses are of a relatively low speed and the rise time is a small percentage of a whole pulse duration (i.e., when the time constant for charging the a switching element is sufficiently smaller than the pulse duration) as shown in FIG. 3B, image data held in sample-and-hold capacitors are mainly determined by the time of the falling points of the waveforms so that the image data applied during the overlapping period do not substantially exert any ill effects.
A first embodiment of the driving method according to the present invention is explained with reference to FIG. 4 showing a circuit diagram used in the first embodiment and FIG. 5 showing switching pulses supplied from a shift register. Referring to FIG. 4, a shift register generates switching pulses corresponding to input clock pulses. The switching pulses are applied to analog switching elements 2, e.g., comprising thin film transistors, and the information signals 5 are sampled-and-held in capacitors 3. An inverter 4 is used to reverse the clock pulses applied to a lower shift register 1.
In this circuit, two shift registers 1 are disposed at an upper position and a lower position, and the controlling signal lines leading to the analog switching elements are alternately connected to these upper and lower shift registers. Thus, signal lines are distributed into halves and respectively connected to the two shift registers.
When the upper and lower shift registers 1 are driven by two sets of clock pulses with mutually inverted phases by using the above mentioned circuit arrangement, switching pulses supplied to the analog switching elements 2 are shown at ○1 - ○4 in FIG. 5. Thus, FIG. 5 shows that time-serially supplied pulses are shifted from each other by a phase difference of 90° and overlap each other in a same pulse period or duration 2T.
In the above embodiment, the frequency of the clock pulses becomes one half of clock pulses conventionally used and is reduced to 13.8 MHz for 480×480 picture elements, while the switching pulse frequency is reduced to 6.9 MHz.
A second embodiment of the present invention is shown with reference to FIG. 6 showing a circuit diagram used in the second embodiment. FIG. 7A shows timing clock pulses applied to respective shift registers 1 and FIG. 7B shows switching pulses supplied from the shift registers 1.
In this embodiment, two shift registers each are disposed at upper positions and lower positions, respectively, and the controlling signal lines leading to the analog switching elements 2 are distributed row by row upwardly and downwardly. Further, the upwardly distributed or directed controlling signal lines are further connected alternately to a pair of upper shift registers SR1 and SR3, while the downwardly distributed controlling signal lines are connected alternately to a pair of lower shift registers SR2 and SR4.
According to the circuit arrangement shown in FIG. 6, image signals 5 are sampled-and-held by a sample-and-hold circuit 7 to be distributed in accordance with timing clock pulses to the shift registers, which correspond to the phase differences of the switching pulses.
In the above embodiment, timing clock pulses as shown at φ1 -φ4 in FIG. 7A, which are 25% duty clock pulses with phases differing by 90° each, are applied to respective shift registers. When such clock pulses are applied, switching pulses as shown at ○1 - ○4 in FIG. 7B are applied to analog switching elements 2. FIG. 7B shows that time-serially supplied pulses are shifted from each other by 45° and overlap each other in a same pulse duration 4T. When the pulses shown at ○1 - ○4 in FIG. 7B are considered, a pulse having a duration of 4T is applied to a switching element, and adjacent or time serially supplied pulses overlap each other for a period of 3T (3/4 of a pulse duration). However, the overlapping has no substantial effect on image data supplied to sample-and-hold capacitors 3 as explained hereinbefore.
In the above embodiment, the frequency of the clock pulses becomes one fourth of that conventionally used and is reduced to 6.9 MHz for 480×480 picture elements.
In the above circuit structure, as 25% duty clock pulses with phases differing by 90° each are required, a means for generating and distributing the clock pulses, e.g., constituted by a high-speed IC such as a high-speed clock-operated 4 bit-shift register) is additionally required. However, such an additional means constitutes only a minor part of the whole system, e.g., such a clock pulse distributing means requires 4 bits whereas each shift register is one with 120 bits (=480/4 bits). therefore, it has a minor effect on power consumption and a system cost, when compared to the great advantages accompanying the use of low-speed C-MOS shift registers and switching elements.
FIG. 8 shows a circuit diagram of an active matrix-type display panel, wherein reference numeral 81 inclusively denotes analog switching elements as described above connected to sample-holding condensers 3; 82 denotes a shift register for generating scanning signals; 83 denotes capacitive components provided by, e.g., a nematic liquid crystal; and 84 denotes an n×m matrix display panel.
As described above, according to the invention switching pulses, time-serially or successively supplied to analog switching elements constituting a sample-and-hold circuit, are shifted in phase from each other and overlap each other in a same period or duration. As a result of this structure, even though an increase in the frequency of clock pulses accompanies an the increase in element density, the high-speed shift registers can be constituted by C-MOS, and therefore, a display apparatus can be driven at a low power consumption and produced at a low cost.
Further, according to a second embodiment, the charging time (sampling time) for a switching element is increased to 4 times as long as that conventionally used, so that charge efficiency is improved thereby resulting in the advantage that a high-speed analog switching element conventionally used is unnecessary.
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|U.S. Classification||345/208, 345/87|
|International Classification||G09G3/36, H04N5/66, G02F1/133|
|Cooperative Classification||G09G3/3688, G09G2310/0248, G09G2310/0297|
|Nov 12, 1985||AS||Assignment|
Owner name: CANON KABUSHIKI KAISHA, 3-30-2 SHIMOMARUKO, OHTA-K
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:INOUE, HIROSHI;YAMASHITA, SHINICHI;REEL/FRAME:004482/0299
Effective date: 19851101
|Jul 5, 1988||CC||Certificate of correction|
|Jul 1, 1991||FPAY||Fee payment|
Year of fee payment: 4
|Jun 27, 1995||FPAY||Fee payment|
Year of fee payment: 8
|Jun 29, 1999||FPAY||Fee payment|
Year of fee payment: 12