|Publication number||US4725558 A|
|Application number||US 06/927,501|
|Publication date||Feb 16, 1988|
|Filing date||Nov 6, 1986|
|Priority date||Nov 6, 1985|
|Also published as||CN1003481B, CN86106409A, CN87102718A, CN87102718B|
|Publication number||06927501, 927501, US 4725558 A, US 4725558A, US-A-4725558, US4725558 A, US4725558A|
|Inventors||Shunpei Yamazaki, Kunio Suzuki, Mikio Kinka, Takeshi Fukada, Masayoshi Abe, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Susumu Nagayama, Kaoru Koyanagi|
|Original Assignee||Semiconductor Energy Laboratory Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Referenced by (50), Classifications (22), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to a semiconductor defects curing method and apparatus in which the performance of the semiconductor device is improved. More particularly, this invention relates to measures for eliminating disadvantages caused by the effect of electrical shorts and shunts due to pinholes or other gaps created during the fabrication process of the device.
Recently, considerable efforts have been made to develop systems for depositing amorphous semiconductor alloys, each of which can encompass relatively large areas, and which can be doped to form p-type and n-type materials for the production of p-i-n and other type devices which are, in photovoltaic and other applications, substantially equivalent to their crystalline counterparts. As such a device, there are disclosed improved photoelectric cells in Japanese patent published application Nos. Sho 55-4994, 55-124274, 56-13777, 56-13778, and 56-13779.
One example of a prior art photovoltaic device is shown in FIG. 1. In the figure, a transparent conductive film 2 is formed on a glass substrate 1 with a mask aligned above the substrate 1. Semiconductor layers 3 are deposited on the substrate 1 with the conductive film 2 therebetween with a mask aligned above the substrate 1. Further, on the substrate 1 with the conductive film 2 and the semiconductor layers 3, aluminum layers 4 are formed as second electrodes with a mask. Reference numerals 31 and 11 designate respective photoelectric cells in the figure.
The two cells 31 and 11 are connected in series by means of a connection 12. In the connection 12 the second electrode 38 is made to be in contact with the first electrode 37. Although the figure appears only with two such connections, a number of the cells are connected with each other in series. The integrated photovoltaic device tends to be degraded after thermal treatment at 150° C. for tens of hours. The reason for the degradation is attributed to a reaction between the aluminum layer 4 and the semiconductor layer 3. Such a device is not suitable for outdoor use where the device is likely to be subjected to a high temperature ambient.
To eliminate the adverse reaction, use is made of a double-layered electrode as the second electrode, composed of a conductive transparent layer such as an ITO film below the aluminum electrode, the ITO film being free from reaction with the aluminum layer or the semiconductor layer. The conductive transparent electrode, however, tends to be finely deposited throughout the semiconductor including pinholes, gaps, or the like type defects introduced during fabrication processing. The transparent electrode material in the defects constitutes short current paths either as deposited or after fabrication. Because of this, only photovoltaic devices having narrow converting areas such as of 1 cm ×4 cm are currently available.
One attempt to eliminate short current circuit paths within amorphous semiconductor photovoltaic devices involves the application of a reverse bias voltage to the device. This applied reverse bias causes large currents to flow through the short circuit current paths causing localized heating of the current paths. The localized heating crystallizes the amorphous semiconductor in the region of the short circuit current paths, thereby resulting in an increase in the resistivity of the paths. Unfortunately, this process has many limitations. The resistivity of the path remains less than the resistivity of the unheated amorphous semiconductor device area, even after having been increased by the concentrated current. As a result, the short circuit current paths are not eliminated, but merely have their resistivity changed to a limited extent. Also this method is not effective for eliminating short circuit current paths resulting from substrate surface irregularities which can be a most prevalent cause of short circuit current paths, especially in large area devices having a roughened substrate surface forming a diffuse back reflector.
It is therefore an object of the invention to provide an improved semiconductor defects curing method in which adverse short circuits are effectively eliminated.
It is another object of the invention to provide an improved semiconductor defects curing method and apparatus in which undesirable shunts are eliminated with only a simple procedure.
It is a further object of the invention to provide an improved semiconductor defects curing method and apparatus which can be used with an effective roughened large area and without causing short circuit current paths.
FIG. 1 is a fragmentary, cross sectional view of a prior art solar cell.
FIGS. 2(A) through 2(D) are fragmentary, cross sectional views showing another embodiment of the invention.
FIG. 3 is an equivalent circuit of another embodiment of the invention.
FIG. 4 is a graphical diagram showing the trend of reverse bias current in response to increasing reverse bias voltage.
FIGS. 5(A) through 5(D) are fragmentary, cross sectional views showing a further embodiment of the invention.
Referring to FIGS. 2(A) to 2(D), an embodiment of the invention is illustrated. On a substrate 1 such as a glass pane 1.2 mm thick×10 cm long×10 cm wide is formed a conductive transparent film 2, e.g., a laminated film of an ITO layer 1500 angstroms thick on a SnO2 layer 200 to 400 angstroms thick or a transparent film mainly composed of tin oxide or tin nitride doped with a halogen. The film may be fabricated by a LPCVD method, a plasma CVD method, a spraying method, a sputtering method, and an ECR method.
The conductive film 2 is divided into a plurality of sections by patterned grooves 13 which are formed by a laser beam of 1.06 micrometers wavelength or 0.53 micrometers wavelength from a YAG laser 13 controlled by a microcomputer.
The patterned grooves 13 are 50 micrometers wide and 10 cm long by which each section is partitioned from others each with 10 to 20 mm width. On this film a nonmonocrystal layer 3 is formed with a p-n junction or p-i-n junction and with 0.2 to 1.0 micrometer thickness, more preferably 0.5 to 0.7 micrometer thickness. A preferred example is a laminated layer composed of a p-type semiconductor layer (Six Cl-x ; l>x>0) 50 to 150 angstroms thick, an intrinsic amorphous or intrinsic semiamorphous silicon semiconductor layer 0.4 to 0.9 micrometer thick, and an n type layer 200 to 500 micro meters thick.
The semiconductor layer 3 formed with holes 6 and 6' is coated by a spinner or a coater with photocurable organic resin such that all the holes are filled completely with the resin. The organic resin may be a photoresist of positive type such as OFPR-800 distributed by Tokyo Ohka Kogyo Co., Ltd. or other known photoresist. For instance, an amount of photoresist is applied on the layer 3 to a thickness of 0.1 through 5.0 micrometers by spinning at 500 rpm for 5 seconds and thereafter at 2000 rpm for an hour, followed by a prebaking at 85° C. for 40 minutes. The photoresist layer is irradiated from the glass substrate side with ultraviolet light 17 having 300 to 400 nanometers wavelength. The ultraviolet light cannot penetrate the semiconductor layer 3 because of the absorption in the layer whereas the resin 7, 7' filling the holes 6 and 6' is selectively cured. In other words, the intensity and the wavelength are chosen so that the semiconductor layer 3 can function as a mask. Curing of OFPR-800 is carried out by irradiation of ultraviolet light of 6 mW/cm2 for 5 seconds followed by aftertreatments. Then, the uncured resin is removed by rinsing with pure water for 10 minutes. The remaining cured resin in the holes is chemically stabilized by sinter and post-cure treatments. For instance, the layer is given post baking for an hour at 150° C. Thus, the stopping process is completed.
After stopping the holes, openings 18 are formed adjacent to the groove 13 as shown in FIG. 2(B) by means of laser scribing to provide an access to the first electrode 37 and 37'. Although the openings 18 reach the substrate 1 in the figure, they can be more shallow so as long as at least portions of the first electrodes 37 and 37' are exposed. A second electrode 4 consisting of a laminate of two conductive layers is deposited on the underlying laminated layers 2 and 3 and separated into portions by grooves 20 scribed by laser scribing.
The second electrode may also be a transparent conductive layer 300 to 500 angstroms thick, for example, made of ITO, In2 O3, SnO2, or ZnO through which incident light of long wavelength can pass out of the device.
Alternatively, the second electrode may be made reflective by deposition of aluminum, chromium, or silver as a single-layered reflective film, or aluminum and nickel on the transparent electrode film as a double-layered reflective film. In the latter embodiment, the second electrode is comprised of an ITO layer 1050 angstroms thick and an aluminum layer 1000 angstroms thick. The electrode can be formed by sputtering, electron beam deposition, or a plasma CVD method at less than 300° C. in order not to degrade the semiconductor.
Referring to FIG. 2(D) and FIG. 3, a reverse bias applying circuit 22 is illustrated. The circuit comprises a power supply 24 and a number of zener diodes 23. Between each adjacent pair of diodes 23 and between the power supply 24 and the first or last diodes electrical contact is made with the first and second electrodes, respectively so that the power supply 24 output voltage is divided into the reverse bias voltages which are applied to each cell constituting the device. The reverse bias voltage must be less than the breakdown voltage of the p-i-n junction of the semiconductor layer 3. Because of this the reverse bias voltage does not cause current passage through flawless portions of the semiconductor layer 3. To further preclude breakdown of the p-i-n junction, the zener diodes are selected such that the zener voltage is slightly below the breakdown voltage of the p-i-n junction.
In FIG. 3, the circuit diagram includes the number of the cells constituting the device, each of which is represented by a diode 25 corresponding to the semiconductor layer 2 and a resistance 26 corresponding to the defects (holes) as leakage source. The zener diode 23 is connected in parallel to the diode and the resistance so that the voltage applied to the diode 25 is kept below the breakdown voltage thereof.
With the bias voltage less than the breakdown voltage, the holes or flaws in the semiconductor layer 3 filled with the organic resin become current passages which are heated as electric current flows therethrough. The electric power is sometimes less than that required for burning out the holes or flaws completely. To make the burning out easy, the substrate 1 is heated in advance together with the semiconductor to a temperature less than the temperature at which the semiconductor may be degraded, normally less than 150° C.
An experiment was made with a device having 15 cells connected with each other and the bias voltage was chosen at 120 V. As a result, the variation in current in response to increasing reverse bias voltage was obtained as shown in FIG. 4.
In the experiment, the reverse bias voltage increased from 0 to V to 120 V. A first leakage current was observed at 30-1. However, the leakage current decreased because of defects burning out due to the concentrated current flow. As the reverse bias voltage increased, a number of current ripples were observed. The magnitude of the leakage current became larger at the higher reverse bias voltages. With the reverse bias voltage decreasing from a point 32 (through point 33), the reverse bias current smoothly dropped without leakage current.
For reference, the device thus treated was subjected to increasing reverse bias voltage. No leakage current, however, was observed until the reverse current increased at the breakdown voltage (point 34).
After removing the bias applying circuit, the device, integrated on a 10 cm×10 cm panel, was irradiated with light of 100 mW/cm2 (AMl). The characteristics obtained were:
open-circuit voltage: 12.934 V
fill factor: 0.6641
short-circuit current: 79.34 mA
current density: 17.290 mA/cm2
With the device fabricated according to the process identical to that of the preceding in FIG. 2 but without reverse bias curing, the following experimental data 1 were obtained, and without the hole filling process and reverse bias curing, the following experimental data 2 were obtained:
______________________________________ data 1 data 2______________________________________open circuit voltage: 12.315 V 11.49 Vfill factor: 0.597 0.471short-circuit current: 79.34 mA 53.7 mAefficiency: 8.33% 4.43%______________________________________
Compared with the figures obtained with the initial embodiment, it is understood that the device having undergone the reverse bias voltage demonstrates further improved characteristics. The reason why the reverse bias curing is effective is considered to be that a chemical reaction between the resin and the semiconductor may produce a stable insulator tightly joined to the pin-holes.
Another embodiment of the invention is shown in FIGS. 5(A) through 5(D). In this embodiment, the process is similar to that of the preceding embodiment. Therefore, only different configurations are described where redundant explanation does not appear.
A substrate 1 is composed of a conductive heat resisting stainless steel foil 40 of 10 to 100 micrometers thickness and a heat resisting organic resin film or an inorganic insulator film such as of enamel 41 on the stainless foil 40. On the substrate 1, a first electrode 2 is formed, for example, made of a 200 angstroms thick chromium layer, a 200 to 400 angstroms thick silicon oxide layer over a 1500 angstroms thick aluminum layer, a 500 angstroms thick Si3 N4 layer over a 1500 angstroms thick aluminum layer, or a 1500 to 2000 angstroms thick transparent conductive layer mainly composed of tin oxide or tin nitride doped with halogen.
After dividing the first electrode by means of grooves 13 as in the previous embodiment, a multilayered semiconductor layer 3 with a pn junction or pin junction composed, for example, of an n-type semiconductor layer of 200 to 500 thickness, an intrinsic amorphous or semiamorphous silicon semiconductor layer of 0.4 to 0.9 micrometers thickness, and a p-type semiconductor layer (SixCl-x : 0<x<l ) of 50 to 150 angstroms thickness is formed on the substrate.
Then, after the hole filling process is carried out, a second electrode 300 to 1400 angstroms thick is formed with use of a metallic mask. The second electrode is made of a conductive transparent material such as ITO, In2 O3, SnO2, or ITN (a mixture of indium nitride and tin nitride).
Grooves 8 which provide access to the first electrode reach only to the surface of the first electrode 2 so that the second electrode 4 can be in contact with the first electrode 2.
After removing the bias applying circuit, the device integrated on a 10 cm×10 cm panel was irradiated with light of 100 mW/cm2 (AMl). The characteristics obtained were:
open-circuit voltage: 12.618 V
fill factor: 0.672
short-circuit current: 79.710 mA
current density: 17.371 mA/cm2
The effective curing action of the application of the reverse bias is attributed also to the transparent electrodes made of conductive transparent oxide provided on both sides of the semiconductor. That is, when the semiconductor is burned by the reverse bias voltage, a chemical reaction takes place between the transparent electrode and the semiconductor or insulator resulting in an insulating oxide product, silicon oxide for example.
With a device fabricated according to a process identical to that of the preceding FIG. 5 but without reverse bias curing, the following experimental data 1 were obtained, and without the hole filling process and without reverse bias curing, the following experimental data 2 were obtained:
______________________________________ data 1 data 2______________________________________open-circuit voltage: 11.30 V 6.54 Vfill factor: 0.626 0.368short-circuit current: 79.4 mA 75.69 mAefficiency: 8.16% 3.48%______________________________________
As in the previous embodiment, only by filling defects of the semiconductor layer can the performance of the photovoltaic device be markedly improved.
The other important feature of the invention, which is not illustrated in the figure, is that a high yield can be obtained since the fluctuation of the characteristics is small among the finished products. For instance, 0.195 (X=9.63%) was obtained as the variance in efficiency from ten samples each 10 cm long×10 cm wide prepared according to the NEDO standard.
While the present invention has been described with reference to several preferred processes and embodiments thereof, many variations and modifications will now occur to those skilled in the art. It is our intent, therefore, to be limited solely by the scope of the appending claims and not by the specific embodiment disclosed herein. Examples of variations are as follows.
The semiconductor layer may be constituted with a multijunction structure in place of the single junction structure. Namely, the layer can be a laminate composed of a p-type semiconductor (SixCl-x), an intrinsic amorphous silicon semiconductor, an n-type silicon semiconductor, a p-type semiconductor (SixCl-x), an intrinsic semiconductor (SixGel-x), and n-type silicon semiconductor layer 300 to 1000 angstroms thick, wherein O<X<e.g., X=0.5.
To scribe the grooves, the grooves can be formed all at once by irradiating with a laser beam extending in the lateral direction which is produced from an eximer laser through a cylindrical lens, if necessary, after expansion of the original beam.
The above technique according to the invention is applicable also to a light emitting semiconductor devices with double heterojunctions and a super lattice structure. As such devices, the applicant has disclosed some semiconductor devices in U.S. Pat. No. 4,527,179 and U.S. application Ser. No. 645,773.
The invention is advantageous also when applied to a diode array of an image sensor or a nonlinear element of a thin film display. In some applications, the reverse bias voltage circuit can be dispensed with or very simplified. For example, an active device can be cured by applying a reverse voltage to the source, drain, and/or gate electrodes.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4166918 *||Jul 19, 1978||Sep 4, 1979||Rca Corporation||Method of removing the effects of electrical shorts and shunts created during the fabrication process of a solar cell|
|US4385971 *||Jun 26, 1981||May 31, 1983||Rca Corporation||Electrolytic etch for eliminating shorts and shunts in large area amorphous silicon solar cells|
|US4420497 *||Aug 24, 1981||Dec 13, 1983||Fairchild Camera And Instrument Corporation||Method of detecting and repairing latent defects in a semiconductor dielectric layer|
|US4451970 *||Oct 21, 1982||Jun 5, 1984||Energy Conversion Devices, Inc.||System and method for eliminating short circuit current paths in photovoltaic devices|
|US4464823 *||Aug 3, 1983||Aug 14, 1984||Energy Conversion Devices, Inc.||Method for eliminating short and latent short circuit current paths in photovoltaic devices|
|US4466992 *||May 28, 1982||Aug 21, 1984||Phillips Petroleum Company||Healing pinhole defects in amorphous silicon films|
|US4543171 *||Mar 22, 1984||Sep 24, 1985||Rca Corporation||Method for eliminating defects in a photodetector|
|US4544797 *||Mar 26, 1984||Oct 1, 1985||Nukem Gmbh||Method for preventing short-circuits or shunts in a large area thin film solar cell and cell obtained thereby|
|US4640002 *||Dec 5, 1985||Feb 3, 1987||The University Of Delaware||Method and apparatus for increasing the durability and yield of thin film photovoltaic devices|
|JPS5574544A *||Title not available|
|JPS5935490A *||Title not available|
|JPS6037165A *||Title not available|
|JPS6085578A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4774193 *||Mar 4, 1987||Sep 27, 1988||Siemens Aktiengesellschaft||Method for avoiding shorts in the manufacture of layered electrical components|
|US5089426 *||Jan 16, 1990||Feb 18, 1992||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing a semiconductor device free from electrical shortage due to pin-hole formation|
|US5112409 *||Jan 23, 1991||May 12, 1992||Solarex Corporation||Solar cells with reduced recombination under grid lines, and method of manufacturing same|
|US6348807 *||Nov 24, 1998||Feb 19, 2002||Advanced Micro Devices, Inc.||Method and system for utilizing multiple thermocouples to obtain a temperature contour map|
|US6777249||May 30, 2002||Aug 17, 2004||Semiconductor Energy Laboratory Co., Ltd.||Method of repairing a light-emitting device, and method of manufacturing a light-emitting device|
|US7045369||Oct 9, 2001||May 16, 2006||Semiconductor Energy Laboratory Co., Ltd.||Method of fabricating and/or repairing a light emitting device|
|US7195499||Jun 22, 2004||Mar 27, 2007||Semiconductor Energy Laboratory Co., Ltd.||Method of repairing a light-emitting device and method of manufacturing a light-emitting device|
|US7220603||Sep 15, 2004||May 22, 2007||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing display device and manufacturing apparatus|
|US7651896||Aug 23, 2007||Jan 26, 2010||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device|
|US7727779||Apr 13, 2006||Jun 1, 2010||Semiconductor Laboratory Co., Ltd.||Method of fabricating and/or repairing a light emitting device|
|US7727847||Aug 16, 2007||Jun 1, 2010||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing display device|
|US7759859||Apr 5, 2007||Jul 20, 2010||Semiconductor Energy Laboratory Co., Ltd.||Light emitting device and manufacturing method thereof|
|US7795154||Aug 21, 2007||Sep 14, 2010||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device that uses laser ablation, to selectively remove one or more material layers|
|US7943287||Jul 26, 2007||May 17, 2011||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing display device|
|US7960261||Mar 7, 2008||Jun 14, 2011||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing crystalline semiconductor film and method for manufacturing thin film transistor|
|US7977168||Jan 22, 2010||Jul 12, 2011||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device|
|US7994021||Jul 25, 2007||Aug 9, 2011||Semiconductor Energy Laboratory Co., Ltd.||Method of manufacturing semiconductor device|
|US8044895||Sep 8, 2005||Oct 25, 2011||Semiconductor Energy Laboratory Co., Ltd.||Display device and driving method of the same|
|US8202811||Sep 9, 2010||Jun 19, 2012||Semiconductor Energy Laboratory Co., Ltd.||Manufacturing apparatus for selectively removing one or more material layers by laser ablation|
|US8227353||Aug 14, 2007||Jul 24, 2012||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device|
|US8349623||Aug 1, 2008||Jan 8, 2013||Sharp Kabushiki Kaisha||Method and apparatus for manufacturing thin film photoelectric conversion module|
|US8557614||Dec 23, 2011||Oct 15, 2013||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing lighting device|
|US8563431||Aug 17, 2007||Oct 22, 2013||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device|
|US8574944 *||Mar 27, 2009||Nov 5, 2013||The University Of Toledo||System for selectively filling pin holes, weak shunts and/or scribe lines in photovoltaic devices and photovoltaic cells made thereby|
|US8614699||Oct 21, 2011||Dec 24, 2013||Semiconductor Energy Laboratory Co., Ltd.||Display device and driving method of the same|
|US8659014||Jul 1, 2011||Feb 25, 2014||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device|
|US8703579||Jul 20, 2011||Apr 22, 2014||Semiconductor Energy Laborator Co., Ltd.||Method of manufacturing semiconductor device|
|US9059347||Jun 14, 2011||Jun 16, 2015||Semiconductor Energy Laboratory Co., Ltd.||Photoelectric conversion device and manufacturing method thereof|
|US9214587||Aug 18, 2011||Dec 15, 2015||Semiconductor Energy Laboratory Co., Ltd.||Photoelectric conversion module and manufacturing method thereof|
|US9577008||Dec 20, 2013||Feb 21, 2017||Semiconductor Energy Laboratory Co., Ltd.||Display device and driving method of the same|
|US20020042152 *||Oct 9, 2001||Apr 11, 2002||Semiconductor Energy Laboratory Co., Ltd.||Method of fabricating and/or repairing a light emitting device|
|US20040229385 *||Jun 22, 2004||Nov 18, 2004||Semiconductor Energy Laboratory Co., Ltd.||Method of repairing a light-emitting device and method of manufacturing a light-emitting device|
|US20050095740 *||Sep 15, 2004||May 5, 2005||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing display device and manufacturing apparatus|
|US20050212000 *||Mar 15, 2005||Sep 29, 2005||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing light emitting device, and electronic device|
|US20060054894 *||Sep 8, 2005||Mar 16, 2006||Semiconductor Energy Laboratory Co., Ltd.||Display device and driving method of the same|
|US20060183254 *||Apr 13, 2006||Aug 17, 2006||Semiconductor Energy Laboratory Co., Ltd.||Method of fabricating and/or repairing a light emitting device|
|US20070166843 *||Mar 22, 2007||Jul 19, 2007||Semiconductor Energy Laboratory Co., Ltd.||Method of repairing a light-emitting device and method of manufacturing a light-emitting device|
|US20070257607 *||Apr 5, 2007||Nov 8, 2007||Semiconductor Energy Laboratory Co. Ltd.||Light emitting device and manufacturing method thereof|
|US20080026543 *||Jul 25, 2007||Jan 31, 2008||Semiconductor Energy Laboratory Co., Ltd.||Method of manufacturing semiconductor device|
|US20080050895 *||Aug 17, 2007||Feb 28, 2008||Semiconductor Energy Laboratory Co., Ltd.||Method for Manufacturing Semiconductor Device|
|US20080057718 *||Aug 14, 2007||Mar 6, 2008||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device|
|US20080176383 *||Aug 21, 2007||Jul 24, 2008||Semiconductor Energy Laboratory Co., Ltd.||Manufacturing Apparatus of Semiconductor Device and Method for Manufacturing Semiconductor Device|
|US20080182207 *||Jul 26, 2007||Jul 31, 2008||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing display device|
|US20080233719 *||Mar 7, 2008||Sep 25, 2008||Semiconductor Energy Laboratory Co., Ltd.||Method for Manufacturing Crystalline Semiconductor Film and Method for Manufacturing Thin Film Transistor|
|US20100184254 *||Jan 22, 2010||Jul 22, 2010||Semiconductor Energy Laboratory Co., Ltd.||Method for Manufacturing Semiconductor Device|
|US20100326970 *||Sep 9, 2010||Dec 30, 2010||Semiconductor Energy Laboratory Co., Ltd.||Manufacturing Apparatus of Semiconductor Device and Method for Manufacturing Semiconductor Device|
|US20110214729 *||Mar 27, 2009||Sep 8, 2011||University Of Toledo||System for Selectively Filling Pin Holes, Weak Shunts and/or Scribe Lines in Photovoltaic Devices and Photovoltaic Cells Made Thereby|
|EP2184789A1 *||Aug 1, 2008||May 12, 2010||Sharp Corporation||Method and apparatus for manufacturing thin film photoelectric conversion module|
|EP2184789A4 *||Aug 1, 2008||Jul 27, 2011||Sharp Kk||Method and apparatus for manufacturing thin film photoelectric conversion module|
|EP2256818A1 *||May 20, 2010||Dec 1, 2010||Yamaichi Electronics Deutschland GmbH||Connection socket, solar panel and method|
|U.S. Classification||438/80, 136/290, 438/88, 257/E27.125, 136/244, 136/258, 438/466, 438/4|
|International Classification||H01L31/0216, H01L31/02, H01L31/20, H01L27/142|
|Cooperative Classification||H01L31/208, Y02P70/521, H01L31/046, Y10S136/29, Y02E10/50, H01L31/02021|
|European Classification||H01L31/20D, H01L31/0216B3, H01L31/02H2B, H01L27/142R2|
|Nov 6, 1986||AS||Assignment|
Owner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., 398, HA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:YAMAZAKI, SHUNPEI;SUZUKI, KUNIO;KINKA, MIKIO;AND OTHERS;REEL/FRAME:004627/0583
Effective date: 19861017
|Aug 16, 1991||FPAY||Fee payment|
Year of fee payment: 4
|Aug 16, 1995||FPAY||Fee payment|
Year of fee payment: 8
|Aug 9, 1999||FPAY||Fee payment|
Year of fee payment: 12