Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS4735917 A
Publication typeGrant
Application numberUS 06/856,280
Publication dateApr 5, 1988
Filing dateApr 28, 1986
Priority dateApr 28, 1986
Fee statusPaid
Publication number06856280, 856280, US 4735917 A, US 4735917A, US-A-4735917, US4735917 A, US4735917A
InventorsDoris W. Flatley, Kenneth M. Schlesier
Original AssigneeGeneral Electric Company
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Silicon-on-sapphire integrated circuits
US 4735917 A
Abstract
A process for forming a silicon-on-sapphire integrated circuit comprises forming a layer of a conformal dielectric material, such as silicon dioxide, over a sapphire substrate having at least one island of silicon on a major surface thereof; forming a layer of a planarizing material over the dielectric layer, anisotropically etching the planarizing material for a time sufficient to expose the surface of the dielectric layer overlying the island; etching the dielectric layer for a time sufficient to expose at least the top surface of the island; removing the remaining planarizing material, growing a thin layer of gate oxide on the exposed surface of the island and providing a patterned layer of conductive polycrystalline silicon thereover. The etching of the dielectric layer can be continued to at least partially expose the sidewall surface of the islands. Preferably, etching is continued for a time sufficient to completely expose the sidewall surfaces of the isla
The government has rights to this invention pursant to Subcontract No. A5ZV-522881-E-507 under Contract No. F04704-84-C-0061 awarded by the Department of the Air Force.
Images(2)
Previous page
Next page
Claims(8)
We claim:
1. A process of forming an integrated circuit including the steps of:
providing an insulating substrate having at least one island of silicon on a major surface thereof;
depositing a layer of a conformal dielectric material over the island and the substrate, the thickness of said layer being less than the thickness of the island;
depositing a layer of a planarizing material over the layer of dielectric material;
etching the dielectric material with an etchant which does not substantially erode the remaining planarizing material for a time sufficient to expose the top surface and at least partially expose the sidewall surfaces of the islands;
removing the remaining planarizing material;
oxidizing the exposed surface of the silicon island to form a thin layer of silicon dioxide thereon; and
providing a patterned layer of conductive polycrystalline silicon over the thin layer of silicon dioxide.
2. A process in accordance with claim 1, wherein the insulating substrate is sapphire and the conformal dielectric material is silicon dioxide.
3. A process in accordance with claim 1, wherein the silicon island is monocrystalline silicon.
4. A process in accordance with claim 1, wherein the conformal dielectric layer is deposited on the substrate and island by plasma enhanced chemical vapor deposition.
5. A process in accordance with claim 1, wherein etching of the dielectric layer is continued for a time sufficient to completely expose the sidewall surfaces of the island and a portion of the surface of the substrate adjacent thereto.
6. A process in accordance with claim 5, wherein a sufficient portion of the substrate is exposed adjacent to the sidewalls of the islands so that, after the exposed surfaces of the island are oxidized, there is a separation between the resulting layer of silicon dioxide and the remaining layer of dielectric material.
7. A process in accordance with claim 1, wherein the planarizing material is an organic positive resist material.
8. A process in accordance with claim 7, wherein the planarizing material remaining after etching of the dielectric layer is completed is removed with an organic solvent.
Description

The government has rights to this invention pursant to Subcontract No. A5ZV-522881-E-507 under Contract No. F04704-84-C-0061 awarded by the Department of the Air Force.

The present invention relates to a process of forming a silicon-on-sapphire integrated circuit which includes metal oxide semiconductor field-effect transistors (MOSFETs) and more particularly, to such a circuit having improved radiation-hardened characteristics.

BACKGROUND OF THE INVENTION

A silicon-on-sapphire (SOS) integrated circuit typically includes a plurality of spaced, isolated islands of single-crystalline silicon on the surface of a sapphire substrate. Each island may include a MOSFET which has source and drain regions spaced by a channel region, a channel oxide layer over at least the channel region and a conductive gate on the oxide layer and over the channel region. The various MOSFETs are electrically connected to form a desired circuit, such as a complementary MOS (CMOS) integrated circuit. The MOSFETs are typically electrically connected, at least in part, by conductive interconnects of doped polycrystalline silicon.

When SOS devices are subjected to radiation, the passage of radiation through the sapphire substrate creates secondary electrons. These secondary electrons have a high kinetic energy, greater than 20 electron volts for sapphire, which is rapidly lost through scattering events until they are thermalized to the conduction band. These electrons then drift in an electric field, causing current flow, until they are trapped, recombined with ionized core atoms, or pass through device contacts. Thus, in an SOS integrated circuit in which polycrystalline silicon conductive interconnects are directly on the surface of the sapphire substrate, the radiation generated electrons in the sapphire will flow directly into the interconnects which will conduct the electrons directly into field-effect transistors in the silicon islands. This flow of electrons can adversely affect the operation of the SOS integrated circuit.

SUMMARY OF THE INVENTION

There is disclosed a process of forming an integrated circuit which includes an insulating substrate, e.g. sapphire, having at least one island of monocrystalline silicon on a major surface thereof. A thin conformal layer of a dielectric material, e.g. silicon dioxide, is formed over the substrate and the islands. A layer of a suitable planarizing material is deposited over the dielectric material to a thickness greater than the thickness of the islands. The planarizing layer is anisotropically etched until the dielectric layer on the top of the islands is exposed. The dielectric layer is then etched until at least the top surface of the islands is exposed. Etching may be continued to partially expose the sidewall surface of the islands. In a preferred embodiment, etching is continued to expose all of the sidewalls of the islands and a portion of the substrate adjacent thereto. The remaining planarizing layer is removed and a thin layer of silicon dioxide is formed on the exposed surfaces of the islands. Preferably, there is a separation between the silicon dioxide layer on the islands and the dielectric material on the substrate. A patterned layer of conductive silicon is provided thereover.

BRIEF DESCRIPTION OF THE DRAWING

FIGS. 1-6 are sectional views illustrating in sequence the various steps of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 1, silicon islands 14, suitably monocrystalline silicon, have been formed on a major surface 12 of an insulating substrate 10, such as sapphire. While the process of the present invention is particularly advantageous in the formation of a silicon-on-sapphire integrated circuit, it is equally applicable to other monocrystalline insulating substrates, such as beryllia or spinel, or amorphous substrates, such as glass. When the substrate 10 is amorphous the silicon islands 14 are typically polycrystalline. The silicon islands 14 are formed, e.g. by depositing a layer of silicon over the substrate 10 and lithographically defining it utilizing conventional techniques. The silicon islands are suitably from about 200 to 1000 nm thick.

A layer of conformal dielectric material 16 is formed over the substrate 10 and the islands 14. By a conformal layer is meant a layer having a substantially uniform thickness throughout. The conformal layer 16 is suitably silicon dioxide, although other conventional dielectric materials such as silicon nitride or silicon oxynitride could be utilized as well. The conformal dielectric layer 16 is deposited by conventional means such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) and the like. The conformal dielectric layer 16 is thinner than the silicon islands 14 and is suitably from about 50 to 500, preferably from about 80 to 100, nanometers thick.

A thick layer of a suitable planarizing material 18 is deposited over the conformal dielectric layer 16 as shown in FIG. 2. The planarizing material 18 is conventionally applied, preferably by spin-coating, and then baked to enhance planarization and remove residual solvent. The planarizing material 18 is typically a positive resist material such as HPR 206 of Philip A. Hunt Chemical Corp., AZ 1450J of the Shipley Company and the like. Other suitable organic materials which could be utilized to form the planarizing layer 18 include certain polyimides and poly(methylmethacrylate). Although the polyimides have a greater temperature processing latitude, the positive resist materials are generally preferred because of their superior planarizing capability and, particularly, their purity. It is necessary that the planarizing material have resistance to the etchant utilized to etch the dielectric layer 16 as will be discussed. The planarizing layer is substantially thicker than the silicon islands and, after baking, would be thicker where it overlies the substrate 10 than where it overlies the silicon islands 14. Generally, the thickness of the planarizing layer 18, measured over the substrate 10, is at least twice the thickness of the silicon islands.

The planarizing layer 18 is anisotropically etched by conventional dry etching, e.g. reactive ion etching utilizing a plasma such as oxygen or combinations thereof with other gases, for a time sufficient to expose the top surface of the dielectric layer 16 overlying the islands 14 as shown in FIG. 3. The exposed dielectric layer 16 is then etched, suitably by wet etching utilizing, e.g. dilute hydrofluoric acid, or dry etching utilizing a plasma such as carbon tetrafluoride, for a time sufficient to expose at least the top surface of the islands 14 as shown in FIG. 4. The etching of the dielectric layer 16 may be continued to etch the exposed portion thereof adjacent to the silicon islands 14, thus partially exposing the sidewalls of silicon islands 14. Preferably, etching is continued until the sidewalls of the islands 14 and a portion of the substrate adjacent thereto are exposed as shown in FIG. 5. When the dielectric layer 16 is initially dry etched to expose the top of the islands 14, the extended etch is suitably carried out by wet etching. The remaining portion of the planarizing layer 18 is then removed, e.g. with a suitable organic solvent.

MOSFETs can then be formed in the islands 14 using any conventional technique. For example, as shown in FIG. 6, a thin layer of silicon dioxide 20 is formed on the surface and exposed sidewall surfaces of the islands 14, suitably by thermal oxidation of the islands 14 for a time sufficient to form the necessary thickness of oxide. The silicon dioxide layer 20 is suitably from about 10 to 50 nm in thickness, measured on the top of the islands 14. The thin silicon dioxide layer 20 overlying the islands 14 will form the channel dielectric of the devices to be formed thereon. Preferably, the silicon dioxide layer 20 overlying the islands 14 does not contact the dielectric layer 16 on the substrate surface 12. Although a separation of several nanometers is preferred between layers 20 and 16, the extent thereof is not critical to the subject invention. It has been found that devices having a separation between layers 16 and 20 have improved radiation hardening characteristics in comparison to devices having a continuous dielectric layer.

An electrode, suitably comprising a layer of conductive polycrystalline silicon, is then formed on the dielectric layers 16 and 20. The polycrystalline silicon layer may be made conductive by doping with a suitable impurity, such as phosphorus, suitably by adding a source of the impurity, e.g. phosphine, to the silane utilized to form the polysilicon layer by, e.g. low pressure chemical vapor deposition. The conductive polycrystalline silicon electrode is then conventionally, e.g. lithographically, defined to form strips 22 extending across portions of the islands 14 which are to be the channel regions of the MOSFETs as shown in FIG. 6. The strips of doped, conductive polycrystalline silicon 22 provide the desired connection between devices. Using the strips of polycrystalline silicon 22 as a mask, ions of an appropriate conductivity type material are then implanted into the islands 14 to form the source and drain regions of the MOSFETs. Additional strips of conductive polycrystalline silicon may be formed on the device to make ohmic contact with the source and drain regions formed in the islands 14 and electrically connect the various MOSFETs in a desired circuit arrangement in known manner.

The process of this invention is advantageous in that the polycrystalline silicon interconnects are not directly on the surface of the sapphire substrate 10 but are on an intermediate layer of silicon dioxide or other suitable dielectric 16 which has a higher band gap than sapphire and thereby forms a potential barrier to electron flow. The dielectric layer 16 thus will prevent or at least minimize the flow of radiation induced electrons from the sapphire substrate 10 to the polycrystalline silicon conductive lines and thereby prevent any adverse effect to the integrated circuit as a result of the radiation. This advantage is enhanced by the separation of the silicon dioxide layer 20 and the dielectric layer 16 even though there is minimal contact between the interconnect and the substrate in the separation.

The subject process also provides a means for controlling the thickness of the gate oxide layer 20 formed on the top and the sidewalls of the isolated islands 14. This is advantageous to the performance of a device such as a MOSFET formed in the islands and the circuit formed therefrom.

The invention has been described with reference to preferred embodiments thereof. It will be appreciated by those skilled in the art that various modifications may be made from the specific details given without departing from the spirit and scope of the invention.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3511702 *Aug 20, 1965May 12, 1970Motorola IncEpitaxial growth process from an atmosphere composed of a hydrogen halide,semiconductor halide and hydrogen
US3740280 *May 14, 1971Jun 19, 1973Rca CorpMethod of making semiconductor device
US3890632 *Dec 3, 1973Jun 17, 1975Rca CorpStabilized semiconductor devices and method of making same
US3943542 *Nov 6, 1974Mar 9, 1976International Business Machines, CorporationHigh reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
US3974515 *Sep 12, 1974Aug 10, 1976Rca CorporationIGFET on an insulating substrate
US4002501 *Jun 16, 1975Jan 11, 1977Rockwell International CorporationSos processmetal-oxide-semiconductor, silicon on sapphire
US4016016 *May 22, 1975Apr 5, 1977Rca CorporationMethod of simultaneously forming a polycrystalline silicon gate and a single crystal extension of said gate in silicon on sapphire MOS devices
US4076573 *Dec 30, 1976Feb 28, 1978Rca CorporationDeposition of aluminum oxide
US4160260 *Nov 17, 1977Jul 3, 1979Rca Corp.Planar semiconductor devices and method of making the same
US4174217 *Aug 2, 1974Nov 13, 1979Rca CorporationMethod for making semiconductor structure
US4178191 *Aug 10, 1978Dec 11, 1979Rca Corp.Process of making a planar MOS silicon-on-insulating substrate device
US4183134 *Dec 11, 1978Jan 15, 1980Westinghouse Electric Corp.High yield processing for silicon-on-sapphire CMOS integrated circuits
US4199384 *Jan 29, 1979Apr 22, 1980Rca CorporationMethod of making a planar semiconductor on insulating substrate device utilizing the deposition of a dual dielectric layer between device islands
US4199773 *Aug 29, 1978Apr 22, 1980Rca CorporationInsulated gate field effect silicon-on-sapphire transistor and method of making same
US4242156 *Oct 15, 1979Dec 30, 1980Rockwell International CorporationMethod of fabricating an SOS island edge passivation structure
US4252582 *Jan 25, 1980Feb 24, 1981International Business Machines CorporationEvaporation, dopes
US4263709 *Dec 22, 1978Apr 28, 1981Rca CorporationPlanar semiconductor devices and method of making the same
US4277884 *Aug 4, 1980Jul 14, 1981Rca CorporationMethod for forming an improved gate member utilizing special masking and oxidation to eliminate projecting points on silicon islands
US4313809 *Oct 15, 1980Feb 2, 1982Rca CorporationAluminum overcoating
US4323910 *Nov 28, 1977Apr 6, 1982Rca CorporationMNOS Memory transistor
US4341569 *Jul 8, 1980Jul 27, 1982Hughes Aircraft CompanySemiconductor on insulator laser process
US4356623 *Sep 15, 1980Nov 2, 1982Texas Instruments IncorporatedFabrication of submicron semiconductor devices
US4368085 *Jul 8, 1980Jan 11, 1983Rockwell International CorporationSilicon-on-sapphire semiconductor
US4385937 *May 14, 1981May 31, 1983Tokyo Shibaura Denki Kabushiki KaishaSilicon on sapphire semiconductor
US4393572 *May 29, 1980Jul 19, 1983Rca CorporationSemiconductors
US4393578 *Mar 22, 1982Jul 19, 1983General Electric CompanyMethod of making silicon-on-sapphire FET
US4395726 *Mar 27, 1980Jul 26, 1983Tokyo Shibaura Denki Kabushiki KaishaSemiconductor device of silicon on sapphire structure having FETs with different thickness polycrystalline silicon films
US4447823 *Mar 5, 1981May 8, 1984Tokyo Shibaura Denki Kabushiki KaishaSOS p--n Junction device with a thick oxide wiring insulation layer
US4455738 *Dec 24, 1981Jun 26, 1984Texas Instruments IncorporatedSelf-aligned gate method for making MESFET semiconductor
US4472459 *Oct 24, 1983Sep 18, 1984Rca CorporationLocal oxidation of silicon substrate using LPCVD silicon nitride
US4491856 *Feb 27, 1984Jan 1, 1985Tokyo Shibaura Denki Kabushiki KaishaSemiconductor device having contacting but electrically isolated semiconductor region and interconnection layer of differing conductivity types
US4523963 *Feb 27, 1984Jun 18, 1985Tokyo Shibaura Denki Kabushiki KaishaMethod of fabricating MOS device on a SOS wafer by stabilizing interface region with silicon and oxygen implant
US4533934 *Oct 2, 1980Aug 6, 1985Westinghouse Electric Corp.Device structures for high density integrated circuits
US4547231 *Jun 26, 1984Oct 15, 1985Mitsubishi Denki Kabushiki KaishaSeparation of elements by dielectric film
US4557794 *May 7, 1984Dec 10, 1985Rca CorporationMethod for forming a void-free monocrystalline epitaxial layer on a mask
US4604304 *Jul 3, 1985Aug 5, 1986Rca CorporationControlled oxidation of several thin layers
US4658495 *Apr 28, 1986Apr 21, 1987Rca CorporationMethod of forming a semiconductor structure
EP0179719A1 *Oct 22, 1985Apr 30, 1986Sgs-Thomson Microelectronics S.A.Method of producing integrated circuits on an isolating substrate
JPS57133667A * Title not available
Non-Patent Citations
Reference
1Ansell et al., "CMOS in Radiation Environments," VLSI Systems, Sep. 1986, pp. 28-36.
2 *Ansell et al., CMOS in Radiation Environments, VLSI Systems, Sep. 1986, pp. 28 36.
3Hughes et al., "Oxide Thickness Dependence of High-Energy-Electron-, VUV-, and Corona-Induced Charge in MOS Capacitors," Applied Physics Letters, vol. 29, No. 6, Sep. 15, 1976, pp. 377-379.
4 *Hughes et al., Oxide Thickness Dependence of High Energy Electron , VUV , and Corona Induced Charge in MOS Capacitors, Applied Physics Letters, vol. 29, No. 6, Sep. 15, 1976, pp. 377 379.
5J. S. Chang, "Selective Reactive Ion Etching of Silicon Dioxide," Solid State Technology, Apr. 1984, pp. 214-219.
6 *J. S. Chang, Selective Reactive Ion Etching of Silicon Dioxide, Solid State Technology, Apr. 1984, pp. 214 219.
7K. Tanno et al., "Selective Silicon Epitaxy Using Reduced Pressure Technique," Japanese Journal of Applied Physics, vol. 21, No. 9, Sep. 1982, pp. L564-566.
8 *K. Tanno et al., Selective Silicon Epitaxy Using Reduced Pressure Technique, Japanese Journal of Applied Physics, vol. 21, No. 9, Sep. 1982, pp. L564 566.
9Naruke et al., "Radiation-Induced Interface States of Poly-Si Gate MOS Capacitors Using Low Temperature Gate Oxidation," IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dec. 1983, pp. 4054-4058.
10 *Naruke et al., Radiation Induced Interface States of Poly Si Gate MOS Capacitors Using Low Temperature Gate Oxidation, IEEE Transactions on Nuclear Science, vol. NS 30, No. 6, Dec. 1983, pp. 4054 4058.
11Saks et al., "Radation Effects in MOS Capacitors with Very Thin Oxides at 80 K.," IEEE Transactions on Nuclear Science, vol. NS-31, No. 6, Dec. 1984, pp. 1249-1255.
12 *Saks et al., Radation Effects in MOS Capacitors with Very Thin Oxides at 80 K., IEEE Transactions on Nuclear Science, vol. NS 31, No. 6, Dec. 1984, pp. 1249 1255.
13W. E. Ham, "The Study of Microcircuits by Transmission Electron Microscopy", RCA Review, vol. 38, Sep. 1977, pp. 351-389.
14 *W. E. Ham, The Study of Microcircuits by Transmission Electron Microscopy , RCA Review, vol. 38, Sep. 1977, pp. 351 389.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5404007 *May 29, 1992Apr 4, 1995The United States Of America As Represented By The Secretary Of The Air ForceRadiation resistant RLG detector systems
US5643836 *Jul 22, 1994Jul 1, 1997Siemens AktiengesellschaftMethod for producing a semiconductor layer structure having a planarized surface and the use thereof in the manufacture of bipolar transistors and DRAMS
US6612175Jul 20, 2000Sep 2, 2003Nt International, Inc.Sensor usable in ultra pure and highly corrosive environments
US7152478May 16, 2003Dec 26, 2006Entegris, Inc.Sensor usable in ultra pure and highly corrosive environments
US7285449 *Nov 19, 2002Oct 23, 2007Fujitsu LimitedSemiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method
US7446023 *Dec 15, 2004Nov 4, 2008Sharp Laboratories Of America, Inc.High-density plasma hydrogenation
US7514745 *Mar 31, 2006Apr 7, 2009Oki Semiconductor Co., Ltd.Semiconductor device
US8088666Sep 17, 2007Jan 3, 2012Fujitsu Semiconductor LimitedSemiconductor device manufacture method including process of implanting impurity into gate electrode independently from source/drain and semiconductor device manufactured by the method
Classifications
U.S. Classification438/164, 257/E21.704, 257/E21.243, 438/953, 438/703
International ClassificationH01L21/3105, H01L21/86
Cooperative ClassificationY10S438/953, H01L21/86, H01L21/31051
European ClassificationH01L21/3105B, H01L21/86
Legal Events
DateCodeEventDescription
Nov 8, 1999ASAssignment
Owner name: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT, N
Free format text: SECURITY INTEREST;ASSIGNOR:INTERSIL CORPORATION;REEL/FRAME:010351/0410
Effective date: 19990813
Owner name: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT 11
Oct 4, 1999FPAYFee payment
Year of fee payment: 12
Sep 11, 1999ASAssignment
Owner name: INTERSIL CORPORATION, FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HARRIS CORPORATION;REEL/FRAME:010255/0405
Effective date: 19990813
Sep 29, 1995FPAYFee payment
Year of fee payment: 8
Sep 18, 1991FPAYFee payment
Year of fee payment: 4
Mar 15, 1988ASAssignment
Owner name: GENERAL ELECTRIC COMPANY
Free format text: MERGER;ASSIGNOR:R C A CORPORATION, A CORP. OF DE.;REEL/FRAME:004837/0618
Effective date: 19880129
Owner name: GENERAL ELECTRIC COMPANY,STATELESS
Dec 18, 1987ASAssignment
Owner name: RCA CORPORATION, A CORP. OF DE.
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:RCA CORPORATION;REEL/FRAME:004808/0894
Effective date: 19871215
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RCA CORPORATION;REEL/FRAME:004808/0894
Owner name: RCA CORPORATION
Apr 28, 1986ASAssignment
Owner name: RCA CORPORATION, A CORP. OF DE.
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:FLATLEY, DORIS W.;SCHLESIER, KENNETH M.;REEL/FRAME:004556/0050
Effective date: 19860425