Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS4736290 A
Publication typeGrant
Application numberUS 06/873,904
Publication dateApr 5, 1988
Filing dateJun 13, 1986
Priority dateJun 18, 1985
Fee statusLapsed
Also published asCA1251284A1, DE3584446D1, EP0205692A1, EP0205692B1
Publication number06873904, 873904, US 4736290 A, US 4736290A, US-A-4736290, US4736290 A, US4736290A
InventorsIan M. McCallion
Original AssigneeInternational Business Machines Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Microprocessors
US 4736290 A
Abstract
A microprocessor that has two operating modes for generating memory location addresses includes a processor 20 connected to a read-only memory 21, a random access memory 22, and an I/O unit 23 through control 25, data 26 and address 27 buses. A remapper unit 24 is connected in the address bus between the processor 20 and the read only memory and the random access memory so that when it is enabled by a signal from the I/O unit it can selectively change addresses generated by the processor and thus redirect the control of the microprocessor.
Images(2)
Previous page
Next page
Claims(8)
What is claimed is:
1. A microprocessor comprising a processor unit, a read only memory, a random access memory and an input-output unit connected by a control bus, a data bus and an address bus and which has at least a first mode and a second mode of operation for the generation of memory location addresses, characterized in that the microprocessor also includes a remapper unit connected in the address bus between the processor unit and the read only memory and te random access memory, means when changing modes for providing an enable signal to said remapper unit, said remapper unit responsive to said enable signal to selectively change address words generated by the processor.
2. A microprocessor as claimed in claim 1 in which the remapper unit connected in the address bus receives one bit of each address word generated by the processor unit and when enabled replaces the value of said one bit with a different value.
3. A microprocessor as claimed in claim 1 in whicht he first mode provides an address that invokes a power-on start-up control program and the second mode provides an address that bypasses the power-on start-up program which differs by one bit from the address of the first mode and invokes a mode switching control program.
4. A microprocessor as claimed in claim 3 in which the mode switching control program controls the processor to perform the following functions:
(a) mask off interrupts,
(b) store in random access memory the relevant processor information,
(c) activate the remapper,
(d) activate the reset,
(e) release the remapper,
(f) load the information saved at (a) into the processor, and
(g) enable interrupts.
5. A microprocessor as claimed in claim 2 in which the first mode provides an address that invokes a power-on start-up control program and the second mode provides an address that bypasses the power-on start-up control program which differs by one bit from the address of the first mode and invokes a mode switching control program.
6. A microprocessor as claimed in claim 5 in which the mode switching control program controls the processor to perform the following instructions:
(a) mask off interrupts,
(b) store in random access memory the relevant processor information,
(c) activate the remapper,
(d) activate the reset,
(e) release the remapper,
(f) load the information saved at (a) into the processor, and
(g) enable interrupts.
7. In a microprocessor of the type comprising a processor unit, a read only memory, a random access memory and an input-output unit connected by a control bus, a data bus and an address bus and which has at least a first mode and a second mode of operation for the generation of memory location addresses, said processor in response to a mode change providing an address on the address bus that causes a power-on start-up program to be invoked, the improvement for bypassing the power-on start-up program comprising:
a remapping unit connected in the address bus between the processor unit and the read only memory and the random access memory and
means for providing an enable signal when changing modes to said remapper unit,
said remapper unit responsive to said enable signal to change the address generated by the processor to an address which bypasses the power start-up program.
8. In a microprocessor of the type comprising a processor unit, a read only memory, a random access memory and an input-output unit connected by a control bus, a data bus and an address bus and which has at leas a normal mode and protected mode of operation for the generation of memory location addresses, said processor normally in response to the normal mode providing an address on the address bus that causes a power-on start-up program to be invoked, the improvement for bypassing the power-on start-up program when after being in the protected mode, switching back to the normal mode comprising:
said read only memory providing at a given address operation in the normal mode with the power-on start-up program,
said random access memory providing at address one bit different from said given address a program that puts the operation in the normal mode without the power-on start-up program,
a remapper unit connected in one line of the address bus between the processor switching unit and the read only memory and the random access memory and
means for providing an enable signal to said remapper unit when changing from said protected mode back to said normal mode, said remapper unit responsive to said enable signal to change by one bit the address generated by the processor to provide the address which bypasses the power-on start-up program.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to improvements in microprocessors and in particular to apparatus and a method for switching the operating mode of a microprocessor to allow a more efficient use of the machine.

2. Description of the Prior Art

Microprocessors are defined as the physical realization of the central processing unit of a computr system on either a single chip of semiconductor or a small number of chips, (New Penguin Dictionary of Electronics, 1979). Microprocessors usually consist of an arithmetic and logic unit, a control unit and a memory unit. Microprocessors are characterized by speed, word length, architecture and instruction set, which may be either fixed or microprogrammed. The combination of these characteristics determines the performance of the processor.

Most microprocessors have a fixed instruction set. Microprogrammed processors have a control store containing the microcode or firmware that defines the processor's instruction set; such processors may either be implemented on a single chip or constructed from bit-slice elements.

The processor's architecture determines what register, stack and I/O facilities are available, as well as defining the processor's primitive data types and how addresses are derived from its registers. The data types, which are the fundamental entities that can be manipulated by the instruction set, typically include bit, nibble (4 bits), byte (8 bits), word (16 bits), and on the latest microprocessors, double words (32 bits). A word is usually defined as the number of bits in the processor's internal data bus rather than always being 16 bits. Instructions generally include arithmetic logical, flow-of-control, and data movement (between stacks, registers, memory, and I/O ports).

The first microprocessor, the four-chip set Intel 4004, appeared in 1971.

It was a calculator that could implement a simple set of instructions in hardware but permitted complex sequences of them to be stored in a read-only memory (ROM). It has a four-chip set consisting of a CPU, ROM, RAM, and a shift-register chip. The Intel 4004 had a 4-bit data bus, could address 4.5K bytes of memory, and had 45 instructions. Its 8-bit counterpart, the Intel 8008, was introduced in 1974 and its improved derivative, the Zilog Z-80, in 1976.

Current microprocessors include the Zilog Z8000, Motorola 68000, Intel 8086, National 16000, as well as the older Texas Instruments 9900 and Digital Equipment Corporation LSI-11. All of these chips use a 16-bit-wide external data bus. Still higher performance microprocessors using 32-bit external data busses are now beginning to appear.

An article in the IBM Journal of Research and Development, Vol. 29, No. 2, March 1985 entitled "Microprocessors in Brief", by Robert C. Stanley, gives an overview of the past, present, and future of microprocessors and describes the key elements of their structure and operation.

One of the problems that has arisen through the development of families of microprocessors is maintaining compatibility between succeeding generations so that programs developed to run on earlier machines are also able to run on later processors while, at the same time, new programs are able to make use of extended features, such as larger memory capacity.

An example of this problem is found in the IBM Personal Computer (IBM PC) and compatible machines. (IBM is a Registered Trademark). The original IBM PC used the Intel 8088 processor and had a random access memory (RAM) of 640K bytes. A recent version of the IBM PC, the PC/At, uses the more powerful Intel 80286 microprocessor and can have up to 14.6M bytes of RAM.

The 80286 has the same instruction set as the 8088 with some extensions, and has two modes of operation, `real` mode and `protected` mode. The modes define the method of deriving addresses from the contents of registers. In real mode addresses are derived in exactly the same way as is used in the 8088 with the result that programs written for the 8088 will work on the 80286 in real mode, but with no access to the additional memory.

In protected mode a different method of deriving addresses is used which allows access to all memory of the machine, but unfortunately prevents programs not specifically designed to operate on the processor in protected mode from working.

It may be noted here that other methods of increasing the addressing capability of a microprocessor have been devised. For example, as reported in PC WEEK, 30 Apr. 1985, Intel and Lotus are making available for the IBM PC a special memory card with up to 4 Meg of memory utilizing `bank switching`, and Lotus is providing special versions of its software that exploit the additional memory. This method has the advantage that it can be used on existing PCs but it too appears to require programs to be changed to exploit the additional memory.

It is of course possible to modify programs so that they will run in protected mode, and many programs will be so modified. However, while popular application programs have not been modified the computer system must be able to run these modified programs; in other words it must be possible to switch modes.

The 80286 provides an instruction to switch from real to protect mode, but does not provide an instruction to switch back.

Therefore to switch from protected to real mode requires circuitry external to the 80286 to cause a reset of the 80286.

Reset of a microprocessor is caused by applying a pulse to its RESET input. The microprocessor clears all its internal registers and begins to fetch instructions from a fixed address. This address will usually be a Read-only Memory of the computer system and will contain the first instruction of the power on routine which checks out the basic operation of the processor and other parts of the computer system. When the computer is first turned on, external circuitry generates a RESET pulse for the microprocessor after all power levels are stable.

The IBM Personal Computer AT uses reset for mode switching, and incorporates

a. circuits to trigger the RESET pulse from a program

b. circuits to register the fact that the RESET is for the purpose of mode switch, so that after some amount of testing has been performed, the processor can determine whether to proceed with checkout and then initialize the system or whether to complete a mode switch.

c. a routing in ROM which obtains control immediately after RESET and does the following:

1. performs the basic testing of the microprocessor

2. tests the modes switch register (b). If not set, continues with normal power-on sequence, Else . . .

3. determines the address of the modeswitch routine in RAM

4. branches to the modeswitch routine

(Step 1 here takes considerable time and is unnecessary when mode switching, so it might be suggested that this routine could be improved by reversing the order of steps 1 and 2. This would be considered poor practice in modern computer systems because an error that would cause a diagnostic check in step 1 may lead to an invalid outcome of step 2.)

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a solution to the problem of switching modes in microprocessors that is faster than the solution described above that is embodied in the IBM Personal Computer AT.

The additional speed is achieved by avoiding the need to execute the power on routine, and this is achieved by additional hardward circuitry referred to as a remapper. The mode switch registering circuits are dispensed with in this invention.

The remapper changes some addresses coming out of the microprocessor before they reach the memory. In particular the startup address is changed so that the first instruction executed after reset is in the mode switching routine instead of the power on routine.

According to the invention there is provided a microprocessor comprising a processor unit, a read only memory, a random access memory and an input-output unit connected by a control bus, a data bus and an address bus and which has at least a first mode and a second mode of operation for the generation of memory location addresses, characterized in that the microprocessor also includes a read only memory and the random access memory remapper unit connected in the address bus between the processor unit and the, said remapper unit responsive to an enable signal to selectively change address words generated by the processor.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the invention may be fully understood a preferred embodiment thereof will now be described with reference to the accompanying drawings, in which:

FIG. 1 is a block schematic of a microprocessor central processing (CPU) chip.

FIG. 2 is a simplified block schematic of a microprocessor system embodying the invention.

FIG. 3 illustrates the preferred embodiment of the remapper.

DETAILED DESCRIPTION

Referring now more particularly to the drawings, a typical microprocessor CPU chip consists of several separate logical sections as shown in FIG. 1. A control ROM (read-only memory) 1, decodes instructions one at a time and directs the operation of the rest of the CPU chip. A timing and sequence logic unit 2 steps each operation through in its proper order. An ALU (arithmetic logic unit) 3 performs basic arithmetic and logical operations on operands that are fed through it. There are normally a number of registers of various sizes located on the CPU chip itself. Address pointer registers 4, 5, 6 are provided the width of which is dependent on the size of memory the system is designed to handle and on whether the memory being addressed is in the CPU or external to it. There are data registers 7, 8, 9, 10, for storing and transferring data, and at least one of these registers is normally a special-purpose working register called an accumulator 10. The accumulator 10 is involved in most of the data-oriented activity on the CPU. (The results of most of the ALU operations are sent to the accumulator, and its contents are quite often used as one of the operands.) Connecting all of these elements is a data bus 11 whose width is determined by the microprocessor word size. The data bus, with bidirectional buffers 12 at the boundary of the CPU chip, becomes the local system data but and acts as the information path connecting all data-related elements in the system.

The contents of the active address pointer register generally, follow a separate path 14 to the boundary of the CPU chip, where it passes through address buffers 13 to become the local system address bus. A 16-bit address bus allows addressing of 65,536 (often referred to as "64K") separate memory locations, and a 20-bit address bus allows for over a million or 1M. A 24-bit address gives 16M possibilities. In an effort to reduce the number of pins on the CPU package, some microprocessors multiplex some portion of the address bus and data bus on the same group of pins as they leave the CPU chip. This saves pins on the CPU, but requires that extra hardware be added to create individual address and data busses to serve the rest of the system. This is of little consequence in larger systems, however, because the local address and data busses must be buffered again before being distributed to a large number of memory and peripheral chips, and the demultiplexing and buffering can both be done by the same devices. (The address bus is unidirectional only, out of the CPU, but the data bus is bidirectional and must be buffered in both directions.)

FIG. 2 shows the processor of FIG. 1 (20) connected to read only memory (ROM) 21, Random Access Memory (RAM) 22, and a set of input/output control units 23. The data buffers 12 of the processor are connected through the data bus 25, the control bus 26 connects the ROM, RAM and I/O units to the control and timing unit 2 and the address buffers 13 are connected through a bus 27 to an address remapper unit 24 (FIG. 3) and then through bus 28. A reset line 29 connects the I/O unit 23 to the processor and a set line 30 connects the I/O unit to the address remapper.

In the preferred embodiment of the invention, the ROM, 21 responds to addresses in the ranges 936K-1Meg and 15.936 Meg to 16 Meg. The RAM responds to addresses in the ranges 0-640K and 1Meg-15Meg. The ROM contains the power-on routine, and the RAM contains the mode switch routine.

The address remapper unit 24 is shown in detail in FIG. 3. The address bus 27 has 24 bit lines (A0-A23) of which A20 is connected to a two input multiplexor chip 32. The second input 30 to the chip 32 comes from the I/O slave processing chip 23. Microprocessor chip 20 also receives an input from chip 23 on the reset line 29.

When the microprocessor receives an input signal to indicate that it should start operation its first action is go to its power-on address where is found the Power-on self test routine (POST). The power-on address in hexadecimal is expressed as FFFFF0 (24 bits).

The remapper shown in FIG. 3 allows the processor to by-pass the POST routines for the purpose of mode switching as follows. A Mode Switching routine is stored in RAM 22 at the address EFFFF0 which is one bit, in the most significant four bits, different that FFFFF0 (the address of POST).

When the remapper is activated by a `1` value on its `select` input 30 from the I/O units, whatever value appears on line A20 is converted to a `0` bit before being passed on to the rest of the computer system.

If the I/O units now generate a reset online (29) the restart address is converted to EFFFF0 which is the mode switching routine address.

The mode switching routine performs the following actions:

(a) masks off interrupts,

(b) stores in RAM the relevant processor information such as one or more routine addresses to be branched to when the mode switch is complete, a task identifier that indicates the task to be dispatched in the new mode,

(c) activates the remapper 24(32),

(d) activates the reset (29),

(e) releases the remapper,

(f) loads the saved RAM information into the processor,

(g) enables interrupts.

The preferred embodiment of the remapper described above is as simple as possible, but remaps half the addresses of the machine. However, it should be clear that a more complex remapper could be devised which changes fewer addresses. In particular, a remapper which changed only the addresses of the first instruction of the start-up routine would be ideal, but would require more circuits.

The mode switching routine described above activates and releases the remapper on every switch. Alternatively, the preferred embodiment does not do this but leaves the remapper permanently active after initial start-up.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3737860 *Apr 13, 1972Jun 5, 1973Honeywell Inf SystemsMemory bank addressing
US4030073 *Nov 5, 1975Jun 14, 1977Digital Equipment CorporationInitialization circuit for establishing initial operation of a digital computer
US4045782 *Mar 29, 1976Aug 30, 1977The Warner & Swasey CompanyMicroprogrammed processor system having external memory
US4121286 *Oct 8, 1976Oct 17, 1978Plessey Handel Und Investments AgData processing memory space allocation and deallocation arrangements
US4153933 *Feb 13, 1978May 8, 1979Intel CorporationSingle chip MOS computer with expandable memory
US4179735 *Apr 4, 1977Dec 18, 1979Ing. C. Olivetti & C., S.P.A.Computer with an arrangement for changing its working environment
US4228502 *Jun 26, 1978Oct 14, 1980Hitachi, Ltd.Electronic computer system
US4302809 *Nov 16, 1979Nov 24, 1981Burroughs CorporationExternal data store memory device
US4340932 *May 17, 1978Jul 20, 1982Harris CorporationDual mapping memory expansion unit
US4368515 *May 7, 1981Jan 11, 1983Atari, Inc.Bank switchable memory system
US4374411 *Feb 14, 1980Feb 15, 1983Hayes Microcomputer Products, Inc.Relocatable read only memory
US4382279 *Nov 17, 1980May 3, 1983Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme)Single chip microprocessor with on-chip modifiable memory
US4403283 *Jul 28, 1980Sep 6, 1983Ncr CorporationExtended memory system and method
US4443847 *Feb 5, 1981Apr 17, 1984International Business Machines CorporationPage addressing mechanism
US4445170 *Mar 19, 1981Apr 24, 1984Zilog, Inc.Computer segmented memory management technique wherein two expandable memory portions are contained within a single segment
US4450524 *Sep 23, 1981May 22, 1984Rca CorporationSingle chip microcomputer with external decoder and memory and internal logic for disabling the ROM and relocating the RAM
US4527251 *Dec 17, 1982Jul 2, 1985Honeywell Information Systems Inc.Remap method and apparatus for a memory system which uses partially good memory devices
US4528648 *Jul 21, 1982Jul 9, 1985Sperry CorporationMemory management system
US4580212 *Mar 22, 1982Apr 1, 1986Nissan Motor Co., Ltd.Computer having correctable read only memory
US4608632 *Aug 12, 1983Aug 26, 1986International Business Machines CorporationMemory paging system in a microcomputer
EP0055553A2 *Dec 17, 1981Jul 7, 1982Fujitsu LimitedInformation processor with initial programme loading
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4888688 *Sep 18, 1987Dec 19, 1989Motorola, Inc.Dynamic disable mechanism for a memory management unit
US4928237 *Mar 27, 1987May 22, 1990International Business Machines Corp.Computer system having mode independent addressing
US5018062 *Oct 23, 1987May 21, 1991A.I. Architects, Inc.Method and apparatus for overriding a ROM routine in response to a reset
US5193161 *May 18, 1990Mar 9, 1993International Business Machines Corp.Computer system having mode independent addressing
US5226122 *Aug 21, 1987Jul 6, 1993Compaq Computer Corp.Programmable logic system for filtering commands to a microprocessor
US5274791 *Jul 5, 1991Dec 28, 1993Chips And Technologies, Inc.Microprocessor with OEM mode for power management with input/output intiated selection of special address space
US5381530 *Jun 30, 1993Jan 10, 1995Compaq Computer CorporationProgrammable logic system for filtering commands to a microprocessor
US5455909 *Apr 22, 1992Oct 3, 1995Chips And Technologies Inc.Microprocessor with operation capture facility
US5513332 *May 31, 1988Apr 30, 1996Extended Systems, Inc.Database management coprocessor for on-the-fly providing data from disk media to all without first storing data in memory therebetween
US5548746 *Nov 12, 1993Aug 20, 1996International Business Machines CorporationNon-contiguous mapping of I/O addresses to use page protection of a process
US5574926 *Mar 11, 1994Nov 12, 1996Olympus Optical Co., Ltd.One-chip microcomputer system having function for substantially correcting contents of program
US5809330 *Sep 26, 1996Sep 15, 1998Kabushiki Kaisha ToshibaConflict free PC in which only the I/O address of internal device is change when it is determined that the I/O address is overlap by expansion device
US6598111 *Sep 19, 2000Jul 22, 2003Texas Instruments IncorporatedBackplane physical layer controller
Classifications
U.S. Classification711/202
International ClassificationG06F12/06, G06F9/455, G06F9/445, G06F12/00, G06F12/02, G06F15/78, G06F9/06
Cooperative ClassificationG06F9/4403, G06F9/45537
European ClassificationG06F9/455H1, G06F9/44A1
Legal Events
DateCodeEventDescription
Jun 13, 2000FPExpired due to failure to pay maintenance fee
Effective date: 20000405
Apr 2, 2000LAPSLapse for failure to pay maintenance fees
Oct 26, 1999REMIMaintenance fee reminder mailed
Sep 21, 1995FPAYFee payment
Year of fee payment: 8
Aug 1, 1991FPAYFee payment
Year of fee payment: 4
Jun 13, 1986ASAssignment
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:MC CALLION, IAN M.;REEL/FRAME:004564/0295
Effective date: 19860612