|Publication number||US4760036 A|
|Application number||US 07/062,011|
|Publication date||Jul 26, 1988|
|Filing date||Jun 15, 1987|
|Priority date||Jun 15, 1987|
|Also published as||EP0295786A2, EP0295786A3|
|Publication number||062011, 07062011, US 4760036 A, US 4760036A, US-A-4760036, US4760036 A, US4760036A|
|Inventors||Peter J. Schubert|
|Original Assignee||Delco Electronics Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (27), Non-Patent Citations (2), Referenced by (42), Classifications (29), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to a process for preparing a silicon-on-insulator (SOI) wafer for use in the manufacture of integrated circuit devices.
Silicon-on-insulator wafers are of considerable interest in microelectronics because they make feasible integrated circuits with low parasitic capacitances and improved isolation between circuit components. To achieve the maximum benefits of SOI, it is important that the silicon be of high quality, especially with respect to its crystal structure.
Various techniques have been proposed for growing high quality monocrystalline silicon-on-insulator, but none has proved completely satisfactory.
One of the techniques which has had some success involves an epitaxial-lateral-overgrowth (ELO) technique. In this technique, a monocrystalline silicon wafer has its top surface oxidized to form an insulator layer and this layer is then opened to expose regions of the silicon substrate to serve as seed holes. There then follows an epitaxial deposition of silicon to fill selectively the seed holes with vertically grown epitaxial silicon without deposition on the oxide and then without interruption to grow the silicon also laterally away from the filled hole and over the oxide layer as well as vertically. This technique has the disadvantages that the lateral overgrowth usually proceeds only so far before either silicon nucleation occurs on the oxide which interferes with the epitaxial lateral growth or the overgrowth becomes polycrystalline. Moreover, because of the seed holes, it is not completely SOI. In one form of this technique, the seed holes are placed very close together to reduce the possibility of nucleation before the lateral overgrowth merges to form the continuous silicon fill-in. A disadvantage of this technique is that because of the larger area of seed holes, the result is even less true SOI.
The present invention is a process which permits a true SOI structure in that it leaves no seed holes in the final structure. In particular, the invention involves a two-step ELO technique. It involves a first standard ELO process, then an etching of the grown silicon selectively to expose the original seed holes, then oxidation of the silicon exposed at the seed holes to make the oxide layer continuous, and finally a second ELO process using the first ELO as the seed crystal for filling the holes etched in the first ELO layer with epitaxial silicon.
In an illustrative embodiment of the invention, a monocrystalline silicon substrate has its top surface oxidized to form an insulator oxide layer. This layer is then patterned to form seed holes spaced close enough to permit reliable ELO. The surface of the grown silicon layer is then oxidized and the second oxide layer formed is then patterned to open holes overlapping the seed holes formed in the first oxide layer. The grown silicon layer is then etched to expose the original substrate where the seed holes were formed. This exposed silicon substrate is then oxidized to make the first oxide layer continuous. This is followed by a second ELO process to fill the holes made to expose the substrate, in which process the silicon grows laterally from the silicon walls of the holes to form a planar surface. There then is removed the remainder of the second oxide layer over the top of the laterally grown silicon. There results the desired SOI structure in which the insulator layer is continuous so that the grown silicon is completely isolated from the original silicon substrate.
The invention will be better understood taken in conjunction with the accompanying drawings in which:
FIGS. 1 through 12 show in cross-section an SOI structure in successive stages of its preparation in accordance with an embodiment of the invention.
It is to be noted that the drawings are not to scale since the vertical dimensions are generally much smaller than the horizontal dimensions.
FIG. 1 shows a monocrystalline silicon substrate 10, advantageously cut on a <100> crystal plane and lightly doped to be relatively free of crystal defects. This surface of the substrate 10 is then oxidized in conventional fashion to form thereover an oxide layer 12, typically about one micron thick.
The oxide layer 12 is then patterned photolithographically in conventional fashion to form elongated openings 14 in the oxide layer, typically about one micron wide as shown in FIG. 2. The openings are spaced apart about twenty microns. This is sufficiently close such that ELO can be used readily to form a continuous, essentially monocrystalline, layer 16 over the substrate, as shown in FIG. 3, using the substrate silicon exposed at openings 14 for seeding in the manner known in the ELO art. If desirable, the quality of the grown layer 16 can be improved by known regrowth techniques, involving laser melting and freezing techniques.
The thickness of the layer grown need not be any thicker than can be reliably prepared in high quality form, for example, about 35 microns. If a lesser thickness is required, the reduction in thickness can be obtained by a silicon etch in conventional fashion after the inventive process has been completed. Typically, for ELO the silicon is grown in an oven at a temperature of about 800° C. and at a pressure of less than 10 Torr, in which hydrogen gas is flowed in at a rate of about 20 liters per minute, dichlorosilane gas at about 0.2 liters per minute, and hydrochloric acid at about 1 liter per minute. It is important to minimize carbon and oxygen impurities in the oven. The silicon grown typically will have a resistivity of between 50 and 100 ohm-centimeters.
Then the surface of the grown layer 16 is oxidized in conventional fashion to form thereover an oxide layer 18, typically about 1000 Angstroms thick, as seen in FIG. 4.
This layer 18 in turn is patterned by known photolithographic techniques to form openings 20 which overlap the narrower openings 14 in the first oxide layer 12 as shown in FIG. 5. Typically, these openings may be two or three microns wide centered to insure overlap.
Then using the remainder of layer 18 as a mask, the ELO layer 16 is etched anisotropically, typically by reactive ion etching (RIE) in known fashion, to form openings 22 in the layer 15 which extend down to the original silicon substrate 12, as shown in FIG. 6. It may prove advantageous in some instances to retain the photoresist (not shown) which had overlain the oxide 18 and been used for masking when forming the holes 20, as an additional mask when patterning the layer 16 to form the openings 22.
Next, a layer 24 of a suitable masking material, such as silicon nitride, is then conformally deposited in known fashion, typically by chemical vapor deposition, to a thickness of several thousand Angstroms, over the structure essentially to fill the openings in the layer 16, as seen in FIG. 7.
This is followed by another anisotropic etching step in known fashion, advantageously RIE, to remove most of the deposited silicon nitride, leaving only side wall spacers 26 in the opening 22 in the layer 16, as seen in FIG. 8. The spacers should be thin enough to leave fully exposed the original silicon substrate at the region of the seed holes 14.
Then the wafer is heated in an oxidizing atmosphere in the usual fashion to oxidize the exposed silicon substrate, the sidewalls of the silicon layer 16 being masked by the silicon nitride spacers 26 to be unaffected. This step serves to make continuous the original oxide layer 12, as seen in FIG. 9. The side wall spacers 26 can now be removed by an etchant that selectively attacks only the silicon nitride, such as phosphoric acid at 140° C., to reach the structure shown in FIG. 10.
Next follows a second ELO step of the kind previously described to fill the openings 22 in the layer 16 and to form a substantially planar surface for the merged silicon layer 28, as shown in FIG. 11.
Finally, the portions remaining of the oxide layer 18 are selectively removed to leave the true SOI structure shown in FIG. 12 comprising the original silicon substrate 10 whose surface is coated with the continuous oxide layer 12 over which lies the continuous monocrystalline silicon layer 28, completely isolated from the original substrate 10.
In some instances, it may prove desirable to improve the quality of the final layer 28 also by the known regrowth technique involving laser melting and freezing. Moreover, if additional thickness for the layer 28 is desired, this can be done by growing silicon epitaxially on it in conventional fashion. Layer 28 can be made thinner by silicon etching or polishing.
It can be appreciated that the embodiments described are merely illustrative of the general principles of the invention and that various modifications may be made without departing from its spirit and scope. For example, the various dimensions mentioned are merely illustrative and others are feasible. Similarly different materials, for example, for masking, can be used.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US31580 *||Feb 26, 1861||Samuel daskam||Improvement in furnaces for treating iron ores|
|US3544858 *||May 8, 1968||Dec 1, 1970||Philips Corp||Insulated gate field-effect transistor comprising a mesa channel and a thicker surrounding oxide|
|US3725751 *||Jan 20, 1970||Apr 3, 1973||Sony Corp||Solid state target electrode for pickup tubes|
|US3855009 *||Sep 20, 1973||Dec 17, 1974||Texas Instruments Inc||Ion-implantation and conventional epitaxy to produce dielectrically isolated silicon layers|
|US3958040 *||Aug 30, 1974||May 18, 1976||U.S. Philips Corporation||Semiconductor device manufacture|
|US4036672 *||May 5, 1976||Jul 19, 1977||Hitachi, Ltd.||Method of making a junction type field effect transistor|
|US4072545 *||May 21, 1976||Feb 7, 1978||International Business Machines Corp.||Raised source and drain igfet device fabrication|
|US4178197 *||Mar 5, 1979||Dec 11, 1979||International Business Machines Corporation||Formation of epitaxial tunnels utilizing oriented growth techniques|
|US4333965 *||Sep 15, 1980||Jun 8, 1982||General Electric Company||Method of making integrated circuits|
|US4358326 *||Nov 3, 1980||Nov 9, 1982||International Business Machines Corporation||Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing|
|US4384301 *||Oct 9, 1981||May 17, 1983||Texas Instruments Incorporated||High performance submicron metal-oxide-semiconductor field effect transistor device structure|
|US4408386 *||Dec 2, 1981||Oct 11, 1983||Oki Electric Industry Co., Ltd.||Method of manufacturing semiconductor integrated circuit devices|
|US4424621 *||Dec 30, 1981||Jan 10, 1984||International Business Machines Corporation||Method to fabricate stud structure for self-aligned metallization|
|US4444620 *||Sep 12, 1983||Apr 24, 1984||Bell Telephone Laboratories, Incorporated||Growth of oriented single crystal semiconductor on insulator|
|US4487635 *||Feb 14, 1983||Dec 11, 1984||Director-General Of The Agency Of Industrial Science & Technology||Method of fabricating a multi-layer type semiconductor device including crystal growth by spirally directing energy beam|
|US4494303 *||Mar 31, 1983||Jan 22, 1985||At&T Bell Laboratories||Method of making dielectrically isolated silicon devices|
|US4498226 *||Aug 27, 1982||Feb 12, 1985||Tokyo Shibaura Denki Kabushiki Kaisha||Method for manufacturing three-dimensional semiconductor device by sequential beam epitaxy|
|US4507158 *||Aug 12, 1983||Mar 26, 1985||Hewlett-Packard Co.||Trench isolated transistors in semiconductor films|
|US4522682 *||Jun 21, 1982||Jun 11, 1985||Rockwell International Corporation||Method for producing PNP type lateral transistor separated from substrate by O.D.E. for minimal interference therefrom|
|US4533431 *||Jan 13, 1984||Aug 6, 1985||Commissariat A L'energie Atomique||Process for producing conductors for integrated circuits using planar technology|
|US4570330 *||Jun 28, 1984||Feb 18, 1986||Gte Laboratories Incorporated||Method of producing isolated regions for an integrated circuit substrate|
|US4654958 *||Feb 11, 1985||Apr 7, 1987||Intel Corporation||Process for forming isolated silicon regions and field-effect devices on a silicon substrate|
|EP1045111A1 *||Apr 11, 2000||Oct 18, 2000||Hunter Douglas Industries B.V.||Side guide for a roller covering|
|JPS5237781A *||Title not available|
|JPS5742144A *||Title not available|
|JPS5853821A *||Title not available|
|JPS60144949A *||Title not available|
|1||Douglas, "The Route to 3-D Chips", High Technology, Sep. 1983, pp. 55-59.|
|2||*||Douglas, The Route to 3 D Chips , High Technology, Sep. 1983, pp. 55 59.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4818713 *||Oct 20, 1987||Apr 4, 1989||American Telephone And Telegraph Company, At&T Bell Laboratories||Techniques useful in fabricating semiconductor devices having submicron features|
|US4849370 *||Dec 21, 1987||Jul 18, 1989||Texas Instruments Incorporated||Anodizable strain layer for SOI semiconductor structures|
|US4874718 *||Jul 28, 1988||Oct 17, 1989||Mitsubishi Denki Kabushiki Kaisha||Method for forming SOI film|
|US4952526 *||Apr 4, 1989||Aug 28, 1990||Thomson-Csf||Method for the fabrication of an alternation of layers of monocrystalline semiconducting material and layers of insulating material|
|US5057450 *||Apr 1, 1991||Oct 15, 1991||International Business Machines Corporation||Method for fabricating silicon-on-insulator structures|
|US5057888 *||Jan 28, 1991||Oct 15, 1991||Micron Technology, Inc.||Double DRAM cell|
|US5110755 *||Jan 4, 1990||May 5, 1992||Westinghouse Electric Corp.||Process for forming a component insulator on a silicon substrate|
|US5122476 *||May 20, 1991||Jun 16, 1992||Micron Technology, Inc.||Double DRAM cell|
|US5143862 *||Nov 29, 1990||Sep 1, 1992||Texas Instruments Incorporated||SOI wafer fabrication by selective epitaxial growth|
|US5258318 *||May 15, 1992||Nov 2, 1993||International Business Machines Corporation||Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon|
|US5302544 *||Dec 17, 1992||Apr 12, 1994||Eastman Kodak Company||Method of making CCD having a single level electrode of single crystalline silicon|
|US5308445 *||Oct 5, 1992||May 3, 1994||Rohm Co., Ltd.||Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate|
|US5336633 *||Oct 23, 1992||Aug 9, 1994||Rohm Co., Ltd.||Method of growing single crystal silicon on insulator|
|US5338388 *||May 4, 1992||Aug 16, 1994||Mitsubishi Denki Kabushiki Kaisha||Method of forming single-crystal semiconductor films|
|US5417180 *||Jul 29, 1993||May 23, 1995||Rohm Co., Ltd.||Method for forming SOI structure|
|US5518953 *||Mar 15, 1994||May 21, 1996||Rohm Co., Ltd.||Method for manufacturing semiconductor device having grown layer on insulating layer|
|US5554870 *||Aug 2, 1995||Sep 10, 1996||Motorola, Inc.||Integrated circuit having both vertical and horizontal devices and process for making the same|
|US5635411 *||Jun 6, 1994||Jun 3, 1997||Rohm Co., Ltd.||Method of making semiconductor apparatus|
|US6274463||Jul 31, 2000||Aug 14, 2001||Hewlett-Packard Company||Fabrication of a photoconductive or a cathoconductive device using lateral solid overgrowth method|
|US6277703||May 14, 1999||Aug 21, 2001||Stmicroelectronics S.R.L.||Method for manufacturing an SOI wafer|
|US6355497||Jan 18, 2000||Mar 12, 2002||Xerox Corporation||Removable large area, low defect density films for led and laser diode growth|
|US6559035||Feb 5, 2002||May 6, 2003||Stmicroelectronics S.R.L.||Method for manufacturing an SOI wafer|
|US6831350||Oct 2, 2003||Dec 14, 2004||Freescale Semiconductor, Inc.||Semiconductor structure with different lattice constant materials and method for forming the same|
|US6919258||Oct 2, 2003||Jul 19, 2005||Freescale Semiconductor, Inc.||Semiconductor device incorporating a defect controlled strained channel structure and method of making the same|
|US7015517||May 25, 2005||Mar 21, 2006||Freescale Semiconductor, Inc.||Semiconductor device incorporating a defect controlled strained channel structure and method of making the same|
|US7560313 *||Mar 29, 2002||Jul 14, 2009||Shin-Etsu Handotai Co., Ltd.||SOI wafer and method for producing the same|
|US8034696 *||May 18, 2007||Oct 11, 2011||Renesas Electronics Corporation||Manufacturing method of semiconductor device|
|US8350269 *||Apr 25, 2012||Jan 8, 2013||International Business Machines Corporation||Semiconductor-on-insulator (SOI) structure and method of forming the SOI structure using a bulk semiconductor starting wafer|
|US8633055||Dec 13, 2011||Jan 21, 2014||International Business Machines Corporation||Graphene field effect transistor|
|US8673683||Jun 8, 2012||Mar 18, 2014||International Business Machines Corporation||Graphene field effect transistor|
|US8957405||Nov 11, 2013||Feb 17, 2015||International Business Machines Corporation||Graphene field effect transistor|
|US20040219370 *||Mar 29, 2002||Nov 4, 2004||Hiroji Aga||Soi wafer and its manufacturing method|
|US20050073028 *||Oct 2, 2003||Apr 7, 2005||Grant John M.||Semiconductor device incorporating a defect controlled strained channel structure and method of making the same|
|US20050205936 *||May 25, 2005||Sep 22, 2005||Grant John M|
|US20070054459 *||Nov 6, 2006||Mar 8, 2007||Shin-Etsu Handotai Co., Ltd.||SOI wafer and method for producing the same|
|US20070266933 *||May 18, 2007||Nov 22, 2007||Ryuta Tsuchiya||Manufacturing method of semiconductor device|
|US20120205742 *||Aug 16, 2012||International Business Machines Corporation||Semiconductor-on-insulator (soi) structure and method of forming the soi structure using a bulk semiconductor starting wafer|
|CN102915946B *||Oct 9, 2012||Feb 25, 2015||哈尔滨工程大学||Method for forming silicon-on-insulator structure|
|EP0929095A1 *||Jan 13, 1998||Jul 14, 1999||SGS-THOMSON MICROELECTRONICS S.r.l.||Method for producing an SOI wafer|
|EP1179619A1 *||Jul 31, 2001||Feb 13, 2002||Hewlett-Packard Company||Method for crystallising amorphous layers|
|WO2014190890A1 *||May 27, 2014||Dec 4, 2014||Institute Of Physics, Chinese Academy Of Sciences||Composite substrate having isolation layer and manufacturing method thereof|
|WO2015100245A1 *||Dec 22, 2014||Jul 2, 2015||University Of Houston System||Flexible single-crystalline semiconductor device and fabrication methods thereof|
|U.S. Classification||117/89, 438/481, 117/913, 257/E21.131, 148/DIG.154, 117/95, 148/DIG.152, 148/DIG.48, 148/DIG.26, 257/E21.566, 438/413, 117/935|
|International Classification||H01L27/00, H01L21/762, H01L21/263, H01L21/20, C30B29/06, C30B25/02|
|Cooperative Classification||Y10S117/913, Y10S148/048, Y10S148/152, Y10S148/154, Y10S148/026, H01L21/76248, H01L21/02639, H01L21/02532, H01L21/02381|
|European Classification||H01L21/20C, H01L21/762D6|
|Jul 16, 1987||AS||Assignment|
Owner name: DELCO ELECTRONICS CORPORATION, KOKOMO, INDIANA, A
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SCHUBERT, PETER J.;REEL/FRAME:004796/0066
Effective date: 19870618
Owner name: DELCO ELECTRONICS CORPORATION, KOKOMO, INDIANA, A
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHUBERT, PETER J.;REEL/FRAME:004796/0066
Effective date: 19870618
|Dec 13, 1991||FPAY||Fee payment|
Year of fee payment: 4
|Dec 26, 1995||FPAY||Fee payment|
Year of fee payment: 8
|Jan 3, 2000||FPAY||Fee payment|
Year of fee payment: 12