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Publication numberUS4763068 A
Publication typeGrant
Application numberUS 06/822,312
Publication dateAug 9, 1988
Filing dateJan 24, 1986
Priority dateJan 26, 1985
Fee statusPaid
Also published asCN1009311B, CN86100363A, DE3502638A1, EP0190455A1, EP0190455B1
Publication number06822312, 822312, US 4763068 A, US 4763068A, US-A-4763068, US4763068 A, US4763068A
InventorsRobert Schmitt, Peter Steffens
Original AssigneeMwb Messwandler-Bau Aktiengesellschaft
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method, circuit and apparatus for the elimination of the d.c. voltage components of a capacitive a.c. voltage divider
US 4763068 A
Abstract
In a method for the elimination of the d.c. voltage components of a capacitive a.c. voltage divider whose a.c. measuring voltage which may include a d.c. voltage component, is fed to a measurement transformer, the task is to be solved to remove as quickly as possible the d.c. voltage component of the a.c. measuring voltage also to the greatest extent possible without falsification of the reproduction of the middle or high voltage to be measured. This is achieved in that the a.c. measuring voltage (UM) is fed to a measuring amplifier (14) by way of two parallel lines (L1, L2) via a d.c. voltage blocking element (6). The a.c. measuring voltage (UM) is thereby fed directly by way of one line (L1) and the d.c. voltage component (UG) of the a.c. measuring voltage (UM) is determined in the other line (L2) in that the a.c. measuring voltage (UM) is subdivided into such small time sections (t) that an equal number of time sections is coordinated per cycle (T) or half cycle (T/2) and the a.c. measuring voltage is continuously integrated over a period (T) at the frequency (Tf) of the time sections (t). The thus-determined respective d.c. voltage value (UG) is fed to the measuring amplifier (14) in phase opposition to the original value and by way of the latter to the measurement transformer (16) (FIG. 1).
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Claims(19)
We claim:
1. A method for elimination of d.c. voltage components of a capacitive a.c. voltage divider, especially for middle and high voltages, whose a.c. measuring voltage, which may include a d.c. voltage component, is fed to a measurement transformer, comprising the steps of feeding the a.c. measuring voltage by way of a condenser to a measuring amplifier via two parallel lines, the a.c. measuring voltage being fed to the measuring amplifier directly by way of one line, determining in another line the d.c. voltage component of the a.c. measuring voltage by subdividing the a.c. measuring voltage by an analog-digital converter into small time sections such that an equal number of time sections is coordinated to each cycle or half cycle, continuously integrating at a frequency of the time sections the a.c. measuring voltage over a period of time, and feeding the thus determined, respective d.c. voltage values in opposite phase to said d.c. voltage component to the measuring amplifier and by way of said measuring amplifier to the measurement transformer.
2. A method for elimination of d.c. voltage components of a capacitive voltage divider, especially for middle and high voltages, whose a.c. measuring voltage which may include a d.c. voltage component, is fed to a measurement transformer, comprising the steps of feeding the a.c. measuring voltage by way of a condenser to a measuring amplifier via two parallel lines, the a.c. measuring voltage being fed directly by way of a first line, determining in the other line the d.c. voltage component of the a.c. measuring voltage by subdividing the a.c. measuring voltage into such small time sections that an equal number of time sections is coordinated to each half period, continuously forming at a frequency of the time sections from the instantaneous values of at least two successive time sections forming a partial interval of a half cycle, an average voltage value, comparing the average voltage value with a respective average voltage value of the time sections which are one half cycle earlier, and determining therefrom the voltage difference and feeding the same inverted to the measuring amplifier.
3. A method according to claim 2, wherein at least three consecutive time sections are used for the average voltage value formation.
4. A method according to claim 1, further comprising the steps of undertaking the subdivision of the a.c. measuring voltage into time sections by a clock-controlled analog-digital converter controlled by a clock generator, feeding digital information to a digital integrator controlled by clock pulses also controlling said analog-digital converter, feeding in this clock sequence over one a.c. voltage cycle the respective digital values of one cycle, determined by the digital integrator, to a digital-analog converter also controlled by the same clock generator, producing in the digital-analog converter from the digital value a d.c. voltage, and feeding the d.c. voltage to the measuring amplifier in opposite phase to a value actually present in the a.c. measuring voltage.
5. A method according to claim 4, wherein the a.c. measuring voltage in at least one of the two parallel lines is delayed in such a manner that a phase position of the voltage fed to the measuring amplifier is displaced exactly by one or several cycles with respect to the a.c. measuring voltage.
6. A method according to claim 5, further comprising the step of utilizing a microprocessor for forming algorithms.
7. A method according to claim 1, wherein the a.c. measuring voltage in at least one of the two parallel lines is delayed in such a manner that a phase position of the voltage fed to the measuring amplifier is displaced exactly by one or several cycles with respect to the a.c. measuring voltage.
8. A method according to claim 3, wherein the a.c. measuring voltage in at least one of the two parallel lines is delayed in such a manner that a phase position of the voltage fed to the measuring amplifier is displaced exactly by one or several half cycles with respect to the a.c. measuring voltage.
9. A method according to claim 1, wherein the a.c. measuring voltage in at least one of the two parallel lines is delayed in such a manner that the phase position of the voltage fed to the measuring amplifier is displaced exactly by one or several half cycles with respect to the a.c. measuring voltage.
10. A circuit for eliminating d.c. voltage components, comprising capacitive voltage divider means having a connecting point between its high end and low end condenser means, an isolating condenser connected with one electrode to said connecting point, another electrode of said isolating condenser being operatively connected to a measuring amplifier means by way of an impedance, an analog-digital converter means in series with a digital integrator means and a digital-analog converter means being operatively connected in parallel to said impedance, said analog-digital converter means, integrator means and digital-analog converter means being clocked and controlled from a common clock generator means, a measuring voltage being operable to be subdivided into equal time sections by the analog-digital converter means and a respective voltage value of each time section being operable to be fed in digital form to the digital integrator means, the digital integrator means being operable to integrate a desired a.c. measuring voltage from the digital voltage values over one cycle, and the digital integrator means being operable to continuously feed the integrated value corresponding to the respective d.c. voltage component of the a.c. measuring voltage, in the rhythm of the time sections in digital form to the digital-analog converter means, and the latter being operable to feed a d.c. voltage component corresponding to the respective time section in analog form and in opposite phase to the d.c. voltage component of the a.c. measuring voltage to the measuring amplifier means.
11. A circuit according to claim 10, further comprising an inverter means between said digital-analog converter means and the measuring amplifier means.
12. A circuit according to claim 10, wherein said digital-analog converter means inverts the analog d.c. voltage component.
13. A circuit according to claim 10, further comprising a microprocessor means operable as clock generator and control means.
14. A circuit according to claim 13, further comprising means for feeding an a.c. measuring voltage picked up from the capacitive voltage divider means to an ohmic voltage divider means, the isolating condenser means being operatively connected to a point of connection of the ohmic voltage divider means.
15. A circuit according to claim 14, further comprising amplifier means between the ohmic voltage divider means and the isolating condenser means.
16. A circuit according to claim 10, further comprising means for feeding an a.c. measuring voltage picked up from the capacitive voltage divider means to an ohmic voltage divider means, the isolating condenser means being operatively connected to a point of connection of the ohmic voltage divider means.
17. A circuit according to claim 10, further comprising amplifier means between the voltage divider means and the isolating condenser means.
18. An apparatus for eliminating d.c. voltage components of a capacitive a.c. voltage divider means, whose a.c. measuring voltage which may include a d.c. voltage component is fed to a measurement transformer, comprising isolating condenser means, microprocessor means, analog-digital converter means, digital integrator means, digital-analog converter means and measurement transformer means, said isolating condenser means being operatively connected to a point of connection of the capacitive voltage divider means, the isolating condenser means being operatively connected with the measurement transformer by way of two parallel line means, one of said line means being operatively connected with the measurement transformer to feed any present d.c. component in one phase and the other line feeding any possibly present d.c. voltage component to said measurement transformer in opposite phase, said other line including the analog-digital means in series with the integrator means and the digital-analog converter means, and the microprocessor means being operable to control the analog-digital converter means, the digital integrator means and the digital-analog converter means by a single clock generator.
19. An apparatus according to claim 18, further comprising measuring amplifier means, said two line means being operatively connected to the input of the measuring amplifier means and an output of said measuring amplifier means being operatively connected to said measurement transformer.
Description
BACKGROUND AND SUMMARY OF THE INVENTION

The present invention relates to a method for the elimination of the d.c. voltage components of a capacitive a.c. voltage divider, especially for middle and high voltages, as well as to a circuit for carrying out this method and to an apparatus with such a circuit.

Such a method, respectively, such an arrangement are described already in the DE-OS No. 26 34 595. The series circuit of a switch with a very low ohmic resistance is connected in this prior art arrangement as switching device in parallel to the condenser of a capacitive voltage divider connected to ground, and additionally a control device is connected in parallel thereto. The control device opens the switch after the reconnection of the a.c. voltage in dependence of the first passage through zero after a delay time of about one millisecond. Under normal operating conditions, the normal operating condition is reached thereby no later than a half cycle after the reconnection to the line and the input is short-circuited during this period of time.

However, the measurement of high voltages takes place at present for the most part by means of inductive voltage measuring transformers. The higher the voltage level, the more expensive become these installations.

Consequently, attempts were made in the past every so often to carry out the high voltage measurement by means of capacitive high voltage dividers and following measurement amplifier.

The occurrence of d.c. voltage terms in the capacitive divider thereby represents a problem. These d.c. voltages occur when the divider which is under high voltage, is disconnected at an instant in which the voltage is not equal to zero. A d.c. voltage then remains at the amplifier input. Even if this d.c. voltage is reduced by way of the input resistance of the amplifier, the charge which is stored in the high-end voltage condenser, occurs as d.c. voltage component during the reconnection of the high voltage, which d.c. voltage component is subadjacent to the a.c. voltage. This displaces the zero passages of the output voltage which are important for protective installations and with potential-free or floating transformer outputs leads to the saturation thereof.

In improving the aforementioned arrangement, a circuit is proposed in the DE-OS No. 28 46 285 in which the discharge impedance is interconnected in case of a determination of d.c. voltage components and is again disconnected after some cycles which causes the disadvantages described above only during a shorter period of time.

A second high voltage divider is provided in this literature which feeds a second amplifier input blocking a d.c. voltage, and dividers were proposed which include several measuring or control condensers in order to differently process different input voltages and to make logic decisions which alternately connect and disconnect for several half cycles an element of variable impedance at the measurement input in the sense of the d.c. voltage until the d.c. voltage has decayed.

The element with variable impedance is in the most simple case a resistance, and a switch arranged in series therewith. However, it may also be a semi-conductor controllable in its resistance or a register of switches with the same or different resistances as are known in connection with digital-analog converters.

Furthermore, amplifiers with purely electronic filters were made which filter the d.c. voltage components out of the measurement signal. However, it is thereby very difficult to bring about an acceptable compromise in the present-day requirements for accuracy in amplitude and phase, in the frequency response and the transient behavior. Furthermore, such an arrangement is difficult to monitor for its operating reliability--as takes place customarily with the so-called longitudinal differentiation--because the output voltage is not equal to the input voltage for a transition period of time.

Present-day rapid protective installations require already after milliseconds amplifier output voltages which are a good image of the high voltage and which contain no shifts or displacements leading to error or faulty switchings.

This task leads to the solutions known in the prior art according to the DE-OS No. 28 46 285 and the DE-OS No. 26 34 595. The basic concept of the DE-OS No. 26 34 595 is--in contrast to the subject matter according to the DE-OS No. 28 46 285--that the d.c. voltage component is not removed gradually in several steps but is removed totally from the simple high voltage divider in a short period of time and instantaneously at the earliest possible instant.

A falsification of the a.c. voltage to be measured always occurs with these prior art short-circuit arrangements in the middle and high voltage range.

In contrast thereto, the underlying problems are to be solved by the present invention to remove the d.c. voltage component of the a.c. measuring voltage as rapidly as possible and to the greatest possible extent without falsification of the reproduction of the middle or high voltage to be measured. Large, costly components such as, for example, inductive voltage converters, short-circuit switches or the like are thereby to be avoided.

The underlying problems are solved according to the present invention in that the a.c. measuring voltage is fed to a measuring amplifier by way of a condenser and by way of two parallel lines whereby the a.c. measuring voltage is fed directly by way of one line and the d.c. voltage component of the a.c. measuring voltage is determined in the other line in that the a.c. measuring voltage is divided into such small time section that an equal number of time sections is coordinated to each cycle or half cycle and the a.c. measuring voltage is continuously integrated over one cycle at the frequency of the time sections and the thus-determined respective d.c. voltage value is fed in phase opposition to the original value to the measuring amplifier and by way of the latter to the measurement transformer.

By digitalizing the a.c. measuring voltage in a parallel branch of the amplifier and by the integration of the d.c. voltage component obtained over a cycle of the a.c. measurement voltage and the inverted input thereof into the measurement amplifier, any influence on the a.c. measurement voltage is completely avoided and additionally the d.c. voltage component is completely compensated in a very short period of time. By the integration over a cycle, additionally higher frequency interference or noise voltages are eliminated so that actually only the pure d.c. voltage component is obtained and an accurate compensation is made possible thereby.

The same end result is obtained if the a.c. measuring voltage is digitalized in a parallel branch and forms the average value from several time sections of a half cycle and compares the same with the average value formed a half cycle earlier and feeds the obtained voltage difference inverted to the measuring amplifier. One obtains thereby a compensation already at an earlier point in time.

These and other objects, features and advantages of the present invention will become more apparent from the following description when taken in connection with the accompanying drawing which shows, for purposes of illustration only, two embodiments in accordance with the present invention, and wherein:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram in principle of one embodiment in accordance with the present invention;

FIG. 2 is a digitalized measuring voltage curve;

FIG. 3 is a diagram illustrating the operation with the engagement in the zero passage in the absence of a d.c. voltage component;

FIG. 4 is a diagram illustrating the operation with the engagement in the peak point in the absence of a d.c. voltage component;

FIG. 5 is a diagram illustrating the operation with the engagement in the zero passage in the presence of a d.c. voltage component; and

FIG. 6 is a diagram illustrating the operation with a half cycle time section comparison.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now to the drawing, and more particularly to FIG. 1, a capacitive voltage divider 4 formed of the high-end voltage condenser 2 and of the low-end voltage condenser 3 is connected to an a.c. voltage network 1. An isolating capacitor 6 is connected with its electrode 7 to the connecting point 5 of the capacitive voltage divider 4. Preferably a voltage divider 8, especially of ohmic impedances 9 and 10 is connected between the isolating condenser 6 and the connecting point 5. The voltage divider 8 serves to reduce the a.c. measuring value UM to values which are not harmful for the following components such as integrated semi-conductor circuits (IC's) i.e., for example, to 5 V. Possibly an amplifier 11 may be provided especially for accentuating or emphasizing the a.c. measuring voltage UM with respect to noise signals or interference voltages.

The other electrode 12 of the isolating condenser 6 is connected directly with a measuring amplifier 14 by means of a line L1, for example, by way of a resistance 13; the terminals of the primary winding 15 of the measurement transformer 16 are connected to the output of the measuring amplifier 14. According to a first embodiment of the present invention, the series circuit of an analog-digital converter 17 with a digital integrator 18 and with a digital-analog converter 19 as well as possibly with a resistance 20 is connected in the line L2 in parallel with the resistance 13. A microprocessor 21 serves to control the components 17, 18, 19 by way of an internal clock generator 22 and for the control with respect to time of the digital integrator 18 as well as possibly also for the delay of the measured values relative to the a.c. measuring voltage UM. A microprocessor is thereby favorably used which contains already the components such as, for example, RAMs and/or ROMs, by means of which an analog-digital converter, a digital integrator and a digital-analog converter can be realized. The realization then takes place by corresponding programming of the microprocessor. The control takes place by the integrated clock generator.

The operation of this circuit and the sequence of the d.c. voltage compensation of the d.c. voltage component UG contained in the a.c. measuring voltage UM by integration takes place as follows:

The a.c. measuring voltage UM which is present at the isolating condenser 6 at the electrode 12 thereof, is fed directly to the measuring amplifier 14 by way of the resistance 13. At the same time, the a.c. measuring voltage UM reaches the analog digital converter 17. The latter is controlled by the clock generator 22 at such a clock frequency that it subdivides the cycle duration T of the network frequency of the a.c. voltage network 1 into a large number of time sections t and for each time section t, produces the associated voltage value, especially in digital form, for example, in a four-, eight- or sixteen-bit sample. This value is fed to the integrator 18.

The latter is controlled with the same clock frequency Tf and at the same time in such a manner that it always integrates at the frequency of the clock pulses over a cycle duration T and produces the respective integrated value. This operation is illustrated more fully in FIG. 2. As can be seen, the cycle duration T is subdivided into time sections t. The integrator 18 forms always the integral over the cycle duration T, i.e., for example, from the instant of time to to to '. Without a d.c. voltage component, the integrated value at the time instant to ' is therefore equal to zero. Similarly, for example, it is at the instant of time t2'=0 because the integral value from t0 to t2 is eliminated over the cycle duration Tt2 (fine cross-hatched area) whereas that from to to t2 ' is added (coarsely cross-hatched area). In this manner, every d.c. voltage component occurring in a time section t can be determined immediately. The d.c. voltage value UGD which is eventually present in digital form, is fed to the D/A converter 19 which produces in its output the analog d.c. voltage UG. The latter is inverted either directly in the D/A converter 19 or in an inverter connected in the output thereof and is thus fed to the measuring amplifier 14 in opposite phase to the eventually present d.c. voltage component in the a.c. measuring voltage UM, which thus receives the pure a.c. measuring value.

Possibly the a.c. measuring voltage UM or the d.c. voltage component UG, respectively -UG is so delayed by a delay device, for example, by a corresponding programming of the microprocessor 21 that at the input of the measuring amplifier 14 the d.c. voltage component of a time section t corresponds to the same time section of the a.c. measuring voltage UM at the input of the measuring amplifier 14, i.e., both are in phase. Possibly the delay can be so selected that the two are mutually displaced up to a few cycles T whereas the time sections t correspond to one another.

In one example, with a network frequency of 50 Hz, one cycle has the time duration of 20 ms, i.e., T=20 ms. The latter forms the integration interval. For the input magnitude x(t) and the output value y(t), the following equation then applies: ##EQU1##

It is furthermore assumed that one cycle duration T is subdivided into 256 time sections t. The integral is then formed numerically according to the following recursive difference equation:

y(n)=y(n-1)+x(n)-x(n-256),

i.e., the actual integral is calculated from the integral obtained from one cycle T earlier plus the instantaneous detected value at the time Tn minus the detected value (n-256), i.e., 20 ms before. This has as a consequence that after one cycle duration T=20 ms after the application of the network voltage (at 50 Hz) the exact d.c. voltage component is known and is available for compensation.

With the assumed connecting instant of time in the zero passage and with an increasing voltage as illustrated in FIG. 3, one obtains without a d.c. voltage component in the a.c. measuring voltage UM by integration of this first cycle an integration curve which simulates in this first cycle a d.c. voltage component UG. However, this d.c. voltage component only occurs during the first cycle and effects in the most unfavorable case a slight shifting of the a.c. measuring voltage UM by 1/3 of the input amplitude. However, with the beginning of the second cycle, this deviation is eliminated.

FIG. 4 illustrates a corresponding change of the a.c. measuring voltage UM which does not include a d.c. voltage component, during the connection at the peak point of the positive half wave. As can be seen, the a.c. measuring voltage is thereby considerably less distorted.

Finally, the compensation of a d.c. voltage component UG of the a.c. measuring voltage UM is illustrated in FIG. 5 with connection in the zero passage of the a.c. voltage component and with a positive d.c. voltage component at the level of the peak value of the a.c. measuring voltage. It can be seen that after one cycle T, the d.c. voltage component is fully compensated and the pure a.c. voltage is therefore available for the measurement so that neither a saturation of the measurement transformer core nor a distortion by a unilateral core premagnetization by reason of a d.c. voltage component occurs in the measurement transformer.

The method according to the present invention, the associated circuit and the apparatus for the elimination of the d.c. voltage components are suitable for use in all types of a.c. voltage networks even though the preferred field of application are middle and high voltage networks.

In the embodiment in accordance with the present invention illustrated in FIG. 6, the cycles or half cycles are also subdivided into equal time sections t. However, in this case only a partial section Tx is measured during a half cycle T/2 which includes at least three successively following time sections t. The voltage average value UMx is formed from the individual instantaneous values Ut of the a.c. measuring voltage UM, for example, by the addition of the instantaneous values Ut and the division by the number of the utilized time sections t. By the use of several time sections t for the average value formation, voltage peaks or voltage collapses which occur do not appear fully in the measurement result, but the same are compensated.

The respective average voltage value UMx of a time section Tx is compared in each case with the average voltage value UMx ' determined one half cycle T/2 earlier and the obtained voltage is fed inverted to the measuring amplifier 14. In this manner already after one half cycle T/2 a complete compensation of an existing d.c. voltage component is achieved in the a.c. measuring voltage UM. A compensation takes place also in this case after each time section t.

Two measuring phases are illustrated in FIG. 6 whereby the first is cross-hatched coarsely from the left bottom toward the right top and the second is finely cross-hatched from the left top toward the right bottom and for the better differentiation, the latter is provided with the index 2.

The operation is essentially the same as in the first embodiment, only in this embodiment of FIG. 6, the average values are compared and, more particularly, already after a half cycle T/2. The circuit can thereby also be the same, only that in lieu of the integration an average value formation takes place. Both possibilities can be effected by a corresponding programming of the microprocessor 21, respectively, of the coordinated component or, for example, integrated with the microprocessor.

It should also be mentioned that according to the present invention at the instant of time of the connection, a comparison with the reference voltage zero is undertaken over a cycle duration with application of the integration, respectively, over a half cycle T/2 with the average value formation. A d.c. voltage compensation is obtained thereby from this instant which also brings about that the measurement transformer of the measuring circuit does not reach saturation.

While we have shown and described two embodiments in accordance with the present invention, it is understood that the same is not limited thereto but is susceptible of numerous changes and modifications as known to those skilled in the art, and we therefore do not wish to be limited to the details shown and described herein but intend to cover all such changes and modifications as are encompassed by the scope of the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3206686 *Dec 31, 1962Sep 14, 1965Gen ElectricDelay-time controller employing output of compared delayed and undelayed reference signal as delay-line correction signal
US3605012 *Jul 15, 1969Sep 14, 1971Us ArmyNoise cancellation filter system
US3622894 *Dec 7, 1970Nov 23, 1971IbmPredetection signal compensation
US3800236 *Feb 7, 1973Mar 26, 1974Bodenseewerk Perkin Elmer CoCircuit arrangement for base line compensation
US3940759 *Jun 24, 1974Feb 24, 1976Westinghouse Electric CorporationAnalog signal processing system with correction for amplifier offset
US4063447 *Mar 14, 1977Dec 20, 1977Honeywell, Inc.Bridge circuit with drift compensation
US4193039 *Feb 10, 1978Mar 11, 1980The Valeron CorporationAutomatic zeroing system
US4229703 *Feb 12, 1979Oct 21, 1980Varian Associates, Inc.Zero reference and offset compensation circuit
US4327390 *Apr 28, 1980Apr 27, 1982EnertecCapacitive voltage transformers with electronic output
US4406988 *Mar 2, 1981Sep 27, 1983Licentia Patent-Verwaltungs-GmbhCircuit for processing a digital signal
US4500837 *Jan 15, 1981Feb 19, 1985Westinghouse Electric Corp.Detection of DC content in an AC waveform
US4528678 *Jul 5, 1983Jul 9, 1985Westinghouse Electric Corp.Nonlinear noise reduction apparatus with memory
US4607278 *Sep 27, 1983Aug 19, 1986Itt Industries, Inc.Digital circuit for suppressing changes in a digital signal
US4641324 *Sep 14, 1984Feb 3, 1987Eastman Kodak CompanySignal correction apparatus
DE2634595A1 *Jul 31, 1976Mar 3, 1977Gen ElectricGeraet zur ueberwachung hoher wechselspannungen
DE2846285A1 *Oct 24, 1978Apr 26, 1979Hazemeijer BvKapazitiver wechselspannungsteiler
JPS58171109A * Title not available
Non-Patent Citations
Reference
1"The Transient Recorder", by Cargile et al., Research Development 1/73, vol. 24, #1, pp. 32-35.
2 *The Transient Recorder , by Cargile et al., Research Development 1/73, vol. 24, 1, pp. 32 35.
Referenced by
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US5132609 *Dec 19, 1990Jul 21, 1992Alcatel CitCircuit for measuring the level of an electrical signal and including offset correction means, and application thereof to amplifiers having automatic gain control
US5729477 *May 16, 1995Mar 17, 1998Gec Alsthom T & D SaMethod and apparatus for eliminating a disturbing component from a periodic signal, and application to an electronic capacitor voltage transformer
US6420875Mar 22, 2000Jul 16, 2002General Electric CompanyCVT transient filter
US8209139 *Jul 14, 2009Jun 26, 2012Raydium Semiconductor CorporationCapacitance evaluation circuit and electronic device using the same
US20100042346 *Jul 14, 2009Feb 18, 2010Raydium Semiconductor CorporationCapacitance evaluation circuit and electronic device using the same
US20100268081 *Dec 10, 2008Oct 21, 2010Hitachi Medical CorporationUltrasonic diagnostic apparatus and ultrasonic probe
Classifications
U.S. Classification324/126, 324/130
International ClassificationG01R17/06, G01R15/04, G01R15/06, G01R19/00
Cooperative ClassificationG01R17/06, G01R15/06
European ClassificationG01R15/06, G01R17/06
Legal Events
DateCodeEventDescription
Feb 8, 2000FPAYFee payment
Year of fee payment: 12
Sep 29, 1995FPAYFee payment
Year of fee payment: 8
Feb 4, 1992FPAYFee payment
Year of fee payment: 4
Jan 24, 1986ASAssignment
Owner name: MWB MESSWADLER-BAU AG D-8600 BAMBERG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:SCHMITT, ROBERT;STEFFENS, PETER;REEL/FRAME:004520/0219;SIGNING DATES FROM 19851212 TO 19851216
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCHMITT, ROBERT;STEFFENS, PETER;SIGNING DATES FROM 19851212 TO 19851216;REEL/FRAME:004520/0219
Owner name: MWB MESSWADLER-BAU AG,GERMANY