Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS4788582 A
Publication typeGrant
Application numberUS 06/929,056
Publication dateNov 29, 1988
Filing dateNov 10, 1986
Priority dateDec 16, 1982
Fee statusLapsed
Also published asCA1232051A1, DE3381711D1, EP0111899A2, EP0111899A3, EP0111899B1, US5151385
Publication number06929056, 929056, US 4788582 A, US 4788582A, US-A-4788582, US4788582 A, US4788582A
InventorsHideaki Yamamoto, Koichi Seki, Toshihiro Tanaka, Akira Sasano, Toshihisa Tsukada, Yasuharu Shimomoto, Toshio Nakano, Hideto Kanamori
Original AssigneeHitachi, Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device and method of manufacturing the same
US 4788582 A
Abstract
A semiconductor device such as a solar cell, photodiode and solid state imaging device comprises a semiconductor layer made of amorphous silicon formed on a given substrate, and a transparent conductive layer formed by an interfacial reaction between the amorphous silicon and a metallic film directly formed on the amorphous silicon. This transparent conductive layer is used as a transparent electrode of the device and if necessary the remainder after having partially removed the metallic film for the transparent conductive layer is used as a conductive layer and right shielding film.
Images(5)
Previous page
Next page
Claims(22)
We claim:
1. A semiconductor device comprising a substrate; a semiconductor layer made of amorphous silicon formed over said substrate; a transparent conductive layer formed by an interfacial reaction between the amorphous silicon layer and a portion of a metallic film directly formed on the amorphous silicon layer; and a reamining portion of said metallic film extending on said transparent conductive layer and being patterned to selectively expose a predetermined surface portion of said transparent conductive layer so that only said predetermined surface portion of said transparent conductive layer provides an exposed surface that serves as a light receiving window on which incident light directly impinges.
2. A semiconductor device of according to claim 1, wherein at least the portion of said metallic film that reacts with the amorphous silicon layer to form said transparent conductive layer contains at least one element selected from the group consisting of Cr, Mo, W, Ti, V, Zr, Nb, Ta, Hf, Ni, Pd, Co, Pt and Rh.
3. A semiconductor device according to claim 1, wherein an under electrode is formed on said substrate and said semiconductor layer is formed on the under electrode.
4. A semiconductor device according to claim 1, wherein the remaining patterned portion of said metallic film serves as an electrode.
5. A semiconductor device according to claim 4, wherein said electrode has a stripe form.
6. A semiconductor device according to claim 1, wherein the remaining patterned portion of said metallic film serves as a shading layer surrounding said light receiving window.
7. A semiconductor device comprising:
a substrate;
a semiconductor layer made of amorphous silicon formed over said substrate;
a transparent conductive layer fromed on said semiconductor layer, said transparent conductive layer consisting of an interfacial reaction product of the amorphous silicon of said semionductor layer and a metallic film formed on said semiconductor layer; and
a portion of said metallic film being disposed on said transparent conductive layer, said portion of said metallic film being patterned to selectively expose a predetermined surface portion of said transparent conductive layer so that only said predetermined surface portion of said transparent conductive layer provides an exposed surface that serves a light receiving window on which incident light directly impinges.
8. A semiconductor device according to claim 7, wherein said metallic film comprises a metal material that is at least one element selected from the group consisting of Cr, Mo, W, Ti, V, Zr, Nb, Ta, Hf, Ni, Pd, Co, Pt and Rh.
9. A semiconductor device according to claim 7, wherein said patterned portion of the metallic film serves as an electrode.
10. A semiconductor device according to claim 9, wherein said electrode has a stripe form.
11. A semicondcutor device according to claim 9, wherein said patterned portion of the metallic film serves as a shading layer.
12. A semiconductor device according to claim 7, further comprising an electrode formed between said substrate and said semiconductor layer.
13. A semiconductor device according to claim 7, wherein said patterned portion of the metallic film serves as an upper electrode and an under electrode is interposed between said semiconductor layer and said substrate.
14. A semiconductor device according to claim 8, a lower portion of wherein said metallic film is made of said at least one element selected from said group.
15. A semiconductor device according to claim 8 wherein a lower portion of said metallic film is made of a metal material different from said group.
16. A semiconductor device according to claim 8, wherein said metallic film includes a lower portion which adjoins said transparent conductive layer and which is made of sai at least one element of said group an upper portion of the metallic film being made of a metal material different from the at least one element selected from said group.
17. A semiconductor device comprising:
(a) a substrate;
(b) an amorphous silicon layer formed over said substrate.
(c) a transport conductive layer formed on said amorphous silicon layer, said transparent conductive layer consisting of an interfacial reaction product of the amorphous silicon of said amorphous silicon layer and a metallic film formed thereon, said metallic film comprising at least one element selected from the group consisting of Cr, Mo, W, Ti, V, Zr, Nb, Ta, Hf, Ni, Pd, Co, Pt and Rh; and
(d) a portion of said metallic film formed on said amorphous silicon layer remaining on said transparent conductive layer and being patterned to selectively expose a predetermined surface portion of said transparent conductive layer so that only said predetermined surface portion of said transparent conductive layer provides an exposed surface that serves as a light receiving window on which incident light directly impinges.
18. A semiconductor device according to claim 17, wherein a lower portion of said metallic film is made of said at least one element of said group.
19. A semiconductor device accoridng to claim 17, wherein a lower portion of said metallic film is made of a metal material different from said group.
20. A semiconductor device according to claim I7, wherein said metlalic film includes a portion lower which adjoins said transparent conductive layer and is made of said at least one element of said group and upper portion which is made of a metal material differnet from said group.
21. A semiconductor device comprising:
(a) a substrate;
(b) a semiconductor layer made of amorphou silicon formed on said substrate;
(c) a metallic film formed on said semiconductor layer;
(d) a transparent conductive layer interposed between said semiconductor layer and said metallic film, said transparent conductive layer consisting of an interfacial reaction product of the amorphous silicon of said semiconductor layer and metal material forming said metallic film; and
(e) said metallic film being patterned to selectively expose a predetermined surface portion of said transparent conductive layer so that only said predetermined surface portion of said transparent conductive layer provides an exposed surface that serves as a light receiving window on which incident light directly impinges.
22. A semiconductor device according to claim 21, wherein the metal material of said metallic film is at least one element selected from the group consisting of Cr, Mo, W, Ti, V, Zr, Nb, Ta, Hf, Ni, Pd, Co, Pt and Rh.
Description

This is a continuation of application Ser. No. 62,225, filed Dec. 16, 1983.

This invention relates to a semiconductor device having a transparent electrode and a method of manufacturing it which are applicable to a solar cell, photodiode, imaging device or the like.

As well known, such a structure as shown in FIG. 1 has been conventionally adopted in the solar cell, for instance. In FIG. 1, numeral 1 designates a substrate, 2 an under electrode, 3 a semiconductor, 4 a transparent electrode and 5 an upper electrode of a striped metal. In the structure of FIG. 1, light is irradiated to the transparent electrode 4 to extract holes and electrons so generated through the under electrode 2 and the upper electrode 5. And the photodiode, for example, has been conventionally implemented in a sectional structure such as shown in FIG. 2. In FIG. 2, numeral 6 designates a substrate, 7 an under electrode, 8 a semiconductor, 9 a transparent electrode and 10 an upper electrode for current extraction, being commonly made of metal. Light is caused to impinge on the transparent electrode 9 with the result that current according to the incident light flows between the under electrode 7 and the upper electrode 10.

As mentioned above, the conventional photosensitive element having a transparent electrode is of a double layer electrode structure in which an upper electrode made of metal is provided on the transparent electrode. This requires, as a manufacturing process, steps of forming the transparent electrode and working it; and forming the upper electrode of metal and working it. Further, as well known, an ITO (Indium Tin Oxide) is employed as a transparent electrode, which material is ordinarily formed by R.F. sputtering deposition. Thus, this material gives rise to any defects in a semiconductor surface in forming the ITO, and has a difficulty of obtaining an ITO film of good quality. Moreover, when the metal to be formed into an upper electrode is worked on the ITO film by photo-etching, ITO itself may be also disolved since it is a material of considerably weak chemical proof. As above, there have been a number of problems to be solved to use ITO as a transparent electrode.

There are the following articles related with ITO mentioned above:

(i) J. L. Vossen, RCA Rev., 32,289 (1971)

(ii) U.S. Pat. No. 3,749,658 (1973), to J. L. Vossen.

In view of the foregoing, it is an object of this invention to provide a semiconductor device having a transparent electrode which can reduce a great deal of electrode making steps where hydrogenerated amorphous silicon (hereinafter referred to as "a-Si:H") is used as a semiconductor layer and also solve the above mentioned problems; and a method of manufacturing it.

The gist of the device according to this invention is as follows; a semiconductor material having an a-Si:H layer is used and a transparent conductive layer, which is formed on an interface between the a-Si:H layer and a metallic film containing at least one selected from the group including Cr, Mo, W, Ti, V, Zr, Nb, Ta, Hf, Ni, Pd, Co, Pt and Rh through an interfacial reaction therebetween, is used as a transparent electrode.

Thus, the gist of the method of manufacturing the device is as follows:

An a-Si:H layer is formed on a given substrate, a given metallic film containing Cr, Mo, Pt, etc. mentioned above is formed on the a-Si:H layer and the interfacial reaction therebetween is caused to form the transparent conductive layer on the interface therebetween. And the step of removing the metallic film used to form this conductive layer is also included in this method.

Incidentally, as the metallic film, not only an elemental substance of the metals mentioned above but also the film including the above mentioned metal such as the mixture, alloy, Cr-Al, Cr-Ni, Cr-Ni-Al, etc. can be employed.

The thickness of this metallic film is not critical since it is removed after having formed the transparent conductive layer, and the thickness thereof is normally within the range of 50 to 2000 Å, and more preferably within the range of 500 to 2000 Å. An undue thin film is inferior in uniformity of the film while an undue thick film doesn't give rise to any specific advantage but increases the possibility of adversely affecting the semiconductor layer which is attributable to the stress by the metallic film.

The reacting temperature is within the range of 100 to 250 C. In particular, the temperature beyond 250 C. is not preferable since an a-Si:H will degenerate at this temperature. The reacting time is within the range of 20 minutes to one hour. Undue long heating will not provide any specific advantage.

Heat treatment may be performed either during the step of forming the metallic film (i.e. evaporation in state of heating substrate) or after having formed the metallic film.

Further, in a case where the surface of the a-Si:H layer, which appears to be a so-called surrace oxide layer, is removed immediately before the metallic film is formed on the a-Si:H layer, a transparent conductive layer can be formed without any specific heat treatment. That is, the heat treatment at 60 to 70 C. is performed for a sample by a metal evaporation source, thus forming the transparent conductive layer.

The a-Si:H of any one of p, i and n conduction type constitutes the transparent conductive layer. It is of course that the a-Si:H may contain an impurity such as P, B, N, C, O or Ge.

The amorphous silicon which terminates a dangling bond thereof by F, in place of H normally introduced for this purpose, also constitutes the transparent conductive layer.

The thus formed transparent conductive layer is sufficiently practicable from the viewpoint light transparentness and also practicable in the resistance since it is less than about 10 kΩ/□.

This invention uses, as a transparent electrode, a transparent conductive layer formed by an interfacial reaction between the amorphous silicon and metal on the basis of the above discovery. In accordance with the present invention, a solar cell such as shown in FIG. 1 for example, is completed by only the steps of forming an a-Si:H on a semiconductor 3, depositing Cr thereon by evaporation by heat and removing Cr while causing a necessary Cr portion to remain. The number of fabricating steps is reduced by half as compared with the conventional method. Such a problem as may occur in the case of using ITO does not occur. It has been confirmed in the method according to this invention that any method of vacuum-deposition, electron beam deposition and sputtering deposition naturally constitutes entirely the same transparent electrode in property. Hydrogenated amorphous silicon or n-type amorphous silicon doped with P is preferably employed in this invention. But, these amorphous silicons are susceptible to natural oxidation so that when it is left in air during one month or so, an oxidation film being several tens Å thick will be formed. Thus, forming Cr on the oxidation film will not constitute a transparent conductive layer since this oxidation film acts as a reaction stopper. Therefore, this invention must be adapted after this oxidation film has been removed by the etchant of HF system. The hydrogenated amorphous silicon doped with B is more stable than the above materials in chemical property so that even when it is left in air during ten months or so any oxidation film will not be constituted, which always allows a desired conductive layer to be obtained.

The foregoing and other objects, features and advantages of the invention will be apparent from the following, more particular description of the preferred embodiments of the invention as illustrated in accompanying drawings wherein:

FIG. 1 is a sectional view of the conventional solar cell;

FIG. 2 is a sectional view of the conventional photodiode;

FIG. 3 is a sectional view of one embodiment of the solar cell according to this invention;

FIGS. 4A and 4B are a plan view and sectional view of one embodiment of the photodiode according to this invention, respectively;

FIG. 5 is a diagram for explaining a sensor of matrix drive contact type;

FIGS. 6A and 6B are a plan view and a sectional view of one embodiment of this invention;

FIGS. 7A-7F, FIG. 8 and FIG. 9 are sectional views of other embodiments according to this invention, respectively; and

FIG. 10 is a plan view of the embodiment of FIG. 9 according to this invention.

Hereinafter, explanation will be made on the embodiments referring to the drawings.

Embodiment 1

The example in which this invention is applied to a solar cell will be explained referring to FIG. 3.

First, a Cr electrode 12 is formed on a glass substrate 11 by sputtering deposition in an atmosphere such as Ar gas, with its film thickness being 0.3 μm. Plasma CVD (Chemical Vapor Deposition) is performed at the substrate temperature of 230 C. to form a hydrogenated amorphous silicon (a-Si:H) 13 containing P (n-layer) on the Cr electrode 12 using a mixed gas composed of PH3 gas and SiH4 gas (mixture ratio: PH3 /SiH4 ≧0.5 V %); to form an a-Si:H 14 (i-layer) on the n-layer using only SiH4 gas: and to form an a-Si:H 15 containing B (p-layer) on the i-layer using a mixed gas composed of B2 H6 gas and SiH4 gas (mixture ratio: B2 H6 /SiH4 ≧0.5 V %), sequentially. The film thickness of each layer may be about 300 Å for the n-layer, about 5400 Å for the i-layer and about 200 Å for the p-layer, for example. Next, at the substrate temperature within the range of 100 to 250 C. since the reacting speed slows down at the temperature below 100 C. while a higher proportion of hydrogen atoms may be decomposed at the temperature above 250 C., deposition is performed to form a Cr layer being 0.1 μm thick on the entire surface of the P-layer, succeeded by forming an Al layer being 1 μm thick thereon. The time required for heat treatment in this case is about 60 to 30 minutes. Although it is of course that only the Cr layer may be formed with the thickness of 0.4 μm, it is more advantageous to use the Al layer since it reduces an electric resistance. Namely, the range of 0.1 to 0.4 μm about the thickness of the Cr layer is preferably used since it facilitates succeeding treatments and places the electric resistace within an optimum range. In the final step, photoetching is performed to remove the Cr-Al portion other than the Cr-Al portion to be a stripe electrode 17. Incidentally, a phosphoric acid etching liquid is used for Al while ammonium cerium (IV) nitrate solution is used for Cr. Thus, a transparent electrode 16 and the stripe electrode 17 are formed, thereby completing a solar cell. In the embodiment mentioned above, the a-Si:H's are stacked on the glass substrate 11 in the order of n, i and p layer, but they may be stacked in the entirely opposite order (i.e. p, i and n).

EMBODIMENT 2

The example in which this invention is applied to a photo diode will be explained referring to FIGS. 4A and 4B which are a plan view and sectional view, respectively.

First, a Cr layer being 0.3 μm thick is formed on a glass substrate 18 and photoetching is performed for the Cr layer to form a Cr electrode 19. As in the embodiment 1, an n-layer 20, i-layer 21 and p-layer, which are a-Si:H's, respectively, are sequentially formed on the Cr electrode 19 by means of plasma CVD and thereafter photoetching is performed to remove the a-Si:H while a part of the a-Si:H is left. It is carried out by plasma etching using CF4 gas. Thereafter, an SiO2 layer 23 being 2 μm thick is formed on the resultant entire surface by sputtering deposition and the SiO2 on the aSi:H and the peripheral portion of the substrate is removed by photoetching. The SiO2 is removed by a hydrofluoric acid etching liquid. And at the substrate temperature of the range of 100 to 250 C., another Cr layer being 0.1 μm thick and an Al layer being 1 μm thick are formed on the resultant surface by vacuum deposition. At the final step, the Cr-Al layer other than a part 24 of the Cr-Al layer is removed by photo-etching. It is of course that the Cr-Al layer on a contact hole in the SiO2 layer 23 on the a-Si:H layers is removed. A transparent electrode 25 remains on the contact hole, which is formed by the interdependence (interfacial reaction) between the Cr-Al layer and the a-Si:H, and is to be a light window for the photodiode. As described above, when the Cr-Al layer corresponding to the portion to which light is intended to be incident is removed, the transparent electrode remains on the portion while the remaining Cr-Al layer also acts as a metal for light shading, thereby specifying a light window area correctly and easily. Thus, the photodiode is completed.

For simplicity of explanation, the example of making one photodiode has been described in the above. However, one-dimensional or two-dimensional photodiode array can be easily made in entirely the same manner by replacing a photomask. Incidentally, in the above embodiment, the Al layer.is formed on the Cr layer, but in place of Cr a metal such as CrNi having Cr as a main component, Mo or W can be used and instead of Al, such a metal as Au, Ni and Pt can be used. And the p-layer 22 of a-Si:H can be done without in practical use.

Embodiment 3

There has been proposed a matrix contact type sensor as a linear sensor array such as disclosed in Japanese Patent Application Laid-Open No. 52-129258 laid open on 1982. As shown in FIG. 5, this kind of sensor is of a configuration in which a plurality of pair of diodes (designated with DB and DP in the figure) connected in series the polalities of which are opposite to each other are arranged in one dimension. In FIG. 5, numeral 25 designates a drive circuit and 27 is a detect circuit.

This invention is most suitable to fabricate a linear sensor array of diode arrangement. The fabricating process will be explained referring to FIGS. 6A and 6B which illustrate a plan structure and a sectional structure, respectively. A Cr film being 0.2 μm thick is formed on a glass substrate 28 at the substrate temperature of 200 C. by vacuum deposition or sputtering deposition. Next, a Cr electrode 29 is formed by photo-etching. As in the embodiments 1 and 2, an a-Si:H film 37 is stacked and worked as shown in the figure. This film is formed at the substrate temperature of 200 to 250 C. by plasma CVD (Chemical Vapor Deposition). This film includes an n-layer, an i-layer and a p layer. And the n-layer is formed using a mixed gas composed of PH3 gas and SiH4 gas (mixture ratio: PH3 /SiH4 ≧0.5 vol %) as a raw material gas. The i-layer is formed using SiH4. The p-layer is formed using a mixed gas composed of B2 H6 gas and SiH4 gas (mixture ratio: B2 H6 /SiH4 ≧0.5 vol %). The film thickness of each layer may be about 300 Å (n-layer), about 5400 Å (i-layer) and about 250 Å (p-layer). This a-Si:H film is etched while causing the portion to be diodes to remain. Next, an insulating film 30 such as SiO2 glass is formed with the thickness of upwards of 1 μm by sputtering deposition and contacts holes 31, 32, 33 and 34 are photo-etched. Hydrofluoric acid is employed as an etching liquid. A Cr film being 0.1 μm thick and an Al film being 1.5 μm thick are formed on the resultant entire surface at the substrate temperature of 100 to 250 C. Thereafter, a Cr-Al electrode 35 is formed by photoetching, and at a same time the Cr-Al film is removed in the contact hole 32 on the photodiode. Thus, a transparent electrode 36 of transparent conductive layer remains on the photodiode, which is to be a window for incident light. As such, the application of this invention to this embodiment ensures that a linear sensor array sensor of matrix drive type is made through a simple and easy fabricating process. Although the Cr electrode 29 was employed in this embodiment such a metal as Ta, NiCr, Mo, W, Al, Pt, Pd, Ni etc. can also be used as an electrode. The multiple layer including these metals may be used.

Furthermore, in this embodiment the double layer composed of Cr and Al was adopted as a metal film for developing a transparent electrode and the upper metallic wiring 35 obtained by working the metal film. A single layer or multiple layer, however, may be used provided that its structure is such that one selected from the group including Cr, Mo, Ti, V, Zr, Nb, Ta, W, Hf, Ni, Pd, Co, Pt and Rh or the metal having the selected one element as a main component is in contact with the amorphous silicon film. And in this embodiment, stacking was carried during heating but heating may be performed at 100 to 250 C. after the stacking.

Moreover, although a blocking diode was placed at a common electrode side in this embodiment, the blocking diode and the photodiode may be replaced by each other.

There are liner sensor array arrangements such as shown in FIGS. 7A to 7F in addition to the above described arrangement. One photosensitive element is constituted by the blocking diode DB and the photodiode DP in FIGS. 7A and 7B, by the blocking diode DB and a photoconductive film 52 in FIGS. 7C and 7D, and by the photodiode DP and a capacitor consisting of an upper metal electrode 42, an insulator 53 and an under metallic electrode 29 in FIGS. 7E and 7F, respectively. FIGS. 7A, 7C and 7E illustrate such a structure that two cells are arranged holizontally while FIGS. 7B, 7D and 7F illustrate such a structure that they are arranged vertically. It is evident that this invention is applicable to all the structures shown in these figures in such a manner that the previously mentioned transparent electrode is formed on only the contact hole over the photodiode and the photoconductive film as a window for incident light in these figures. In this embodiment, a p-i-n diode was adopted for each diode but a Schottky diode may also be employed.

Incidentally, in FIGS. 7A to 7F, reference numeral 28 designates a glass substrate; 29 an under metallic electrode; 30 an insulating film; 37, 37' a semiconductor material for constituting a diode; 40, 49, 50 a p-type semiconductor layer, i-type semiconductor layer and n-type semiconductor layer, respectively; 42 an upper metallic electrode; and 51 a transparent electrode according to this invention.

EMBODIMENT 4

The sectional structure of this embodiment is illustrated in FIG. 8, which is the same as the embodiment 3 except that in the embodiment 3 the transparent electrode 36 is caused to remain on only the photodiode while in this embodiment 4, Cr-Al, which corresponds to the part indicated by letter "A" in the neighbourhood of the photodiode, is removed to form a hole. Such an arrangement enables the light L to enter from the lower side of the glass substrate 28 as indicated by an arrow. That is, this arrangement can be adapted to such a device that the light L is caused to enter from the lower side of the glass substrate 28, and the light reflected at a manuscript M placed in proximity to the sensor is caused to enter the photodiode thereby to read the manuscript M through photo-electric conversion.

EMBODIMENT 5

Explanation will be made on the embodiment that this invention is adapted to a solid state imaging device using a photoconductive film.

As disclosed in Japanese Patent Application Laid-Open No. 51-10715 laid open on 1981, this device is such that a photoconductive film made of a photoconductor such as an a-Si:H for photo-electric conversion is formed on a semiconductor substrate (IC substrate for scanning) having at least switches two-dimentionally arranged and a scanner for transmitting photoelectrons derived through the switches and corresponding to an optical image. FIG. 9 shows a basic structure of this device. The IC part for scanning is made by an ordinary process for manufacturing a semiconductor device. First, a thin SiO2 film being about 800 Å is formed on a p-type Si substrate 60, and an Si3 N4 is formed on a predetermined area of the SiO2 film, with its thickness being about 1400 Å. The SiO2 film is made by a common CVD technique and the Si3 N4 film is made by the CVD technique in N2 atmosphere. Next, the Si substrate is subjected to local oxidation in such an atmosphere as H2 :O2 =1:8 to form an SiO2 layer 68: This method is directed to local oxidation of Si for an isolation between elements commonly called LOCOS. The above Si3 N4 film and SiO2 film are once removed partially and a gate insulating film 71 for an MOS transistor is formed by an SiO2 film.

Next, a gate portion 69 of polysilicon and, diffusion areas 70, 61 are formed and an SiO2 film 72 is formed on the resultant surface. A window for deriving an electrode for the diffusion area 61 is bored in this film 72 by etching. Al is deposited to form an electrode with its thickness being 8000 Å. An SiO2 film 63 being 1500 Å thick is formed, an window for deriving an electrode is bored on the diffusion area 7a by etching, and Al or Mo is deposited with its thickness of 1 μm as an electrode 64. Incidentally, the electrode 64 is formed so wide as to cover the diffusion areas 70 and 61 and the gate portion. This is because an incident light to a signal processing area between elements may cause an undesired blooming.

A photoconductive film 65 is formed by sputtering in an atmosphere of the mixed gas composed of Ar and H at 0.2 Torr. The hydrogen condent is 6 mol %. That is, the reactive sputtering is performed at a frequency of 13.56 MHz and input of 300 W using a silicon target to stack the photoconductive film 65 of 1 μm on the IC substrate for scanning. Thereafter, Cr is stacked by 2000 Å at the substrate temperature of 100 to 250 C. by sputtering or vacuum deposition. Next, patterning is carried out so as to section the photosensitive element as shown in a plan view of a photosensitive part of FIG. 10. Thus, a transparent conductive film 66 is formed on the photosensitive element, which also acts as a shading 67 enhance a resolution so as to restrict an angle of the incident light for one photosensitive element.

Although MOS transistor was used as a scanning IC in this embodiment, a CCD or BBD may also be adapted in place of the MOS transistor.

Where the shading 67 is not required, the remainder of Cr at only the peripheral portion of a photoconductive layer will not cause any serious problem.

B and P were used as a dopant for the a-Si:H in this embodiment, but it is evident that N, C, O, G, etc. may be used. And F may be used as a terminator of a dangling bond instead of H.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3778684 *Jan 13, 1972Dec 11, 1973Licentia GmbhSemiconductor element and method of making it
US4142195 *Jul 30, 1976Feb 27, 1979Rca CorporationSchottky barrier semiconductor device and method of making same
US4278704 *Jan 30, 1980Jul 14, 1981Rca CorporationMethod for forming an electrical contact to a solar cell
US4322453 *Dec 8, 1980Mar 30, 1982International Business Machines CorporationConductivity WSi2 (tungsten silicide) films by Pt preanneal layering
US4554478 *May 25, 1983Nov 19, 1985Hitachi, Ltd.Photoelectric conversion element
JPS48979A * Title not available
Non-Patent Citations
Reference
1Coleman, M. G. et al. "The Pd2 Si-(Pd)-Ni-Solder Plated Matellization System for Silicon Solar Cells", 13th IEEE Photovoltaic Specialists Conference, Washington, 5-8 Jun. 1978, pp. 597-602.
2 *Coleman, M. G. et al. The Pd 2 Si (Pd) Ni Solder Plated Matellization System for Silicon Solar Cells , 13th IEEE Photovoltaic Specialists Conference, Washington, 5 8 Jun. 1978, pp. 597 602.
3Han M. K. et al. "Influence of Thin Metal as a Top Electrode on the Characteristics of P-I-Na-Si:H Solar Cells", Journal of Applied Physics, vol. 52, No. 4, Apr. 1981, pp. 3073-3075.
4 *Han M. K. et al. Influence of Thin Metal as a Top Electrode on the Characteristics of P I Na Si:H Solar Cells , Journal of Applied Physics, vol. 52, No. 4, Apr. 1981, pp. 3073 3075.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5039852 *Dec 14, 1989Aug 13, 1991Kanegafuchi Chemical Industry Co., Ltd.Semiconductor image sensor
US5091764 *Sep 28, 1989Feb 25, 1992Kanegafuchi Kagaku Kogyo Kabushiki KaishaSemiconductor device having a transparent electrode and amorphous semiconductor layers
US5119170 *Sep 9, 1991Jun 2, 1992Seiko Epson Corp.Thin film metal interconnects in integrated circuit structures to reduce circuit operation speed delay
US5151385 *Oct 3, 1988Sep 29, 1992Hitachi, Ltd.Method of manufacturing a metallic silicide transparent electrode
US5254480 *Feb 20, 1992Oct 19, 1993Minnesota Mining And Manufacturing CompanyProcess for producing a large area solid state radiation detector
US5291036 *Nov 16, 1992Mar 1, 1994Minnesota Mining And Manufacturing CompanyAmorphous silicon sensor
US5525527 *Feb 3, 1995Jun 11, 1996Minnesota Mining And Manufacturing CompanyProcess for producing a solid state radiation detector
US5818053 *Jun 5, 1996Oct 6, 1998Imation Corp.Multi-module solid state radiation detector with continuous photoconductor layer and fabrication method
US5942756 *Nov 3, 1997Aug 24, 1999Imation Corp.Radiation detector and fabrication method
US6262421Apr 18, 2000Jul 17, 2001Imation Corp.Solid state radiation detector for x-ray imaging
US7382034May 15, 2002Jun 3, 2008Stmicroelectronics NvOptoelectronic component having a conductive contact structure
CN101128933BFeb 22, 2006May 19, 2010Oc欧瑞康巴尔斯公司Method of fabricating an image sensor device with reduced pixel cross-talk
WO2002093653A2 *May 15, 2002Nov 21, 2002Jens PrimaOptoelectronic component having a conductive contact structure
WO2006089447A1 *Feb 22, 2006Aug 31, 2006Unaxis Balzers AgMethod of fabricating an image sensor device with reduced pixel cross-talk
Classifications
U.S. Classification257/749, 257/E31.122, 136/258, 438/98, 257/768, 438/655, 257/E31.126, 438/683, 136/256, 438/682
International ClassificationH01L31/10, H01L31/04, H01L31/0224, H01L31/18, H01L27/14, H01L31/0216, H01L31/20
Cooperative ClassificationY10S148/147, H01L31/1884, H01L31/02164, H01L31/022466, H01L31/202, Y02E10/50
European ClassificationH01L31/0216B2B, H01L31/0224C, H01L31/20B, H01L31/18J
Legal Events
DateCodeEventDescription
Jan 30, 2001FPExpired due to failure to pay maintenance fee
Effective date: 20001129
Nov 26, 2000LAPSLapse for failure to pay maintenance fees
Jun 20, 2000REMIMaintenance fee reminder mailed
Jul 9, 1996REMIMaintenance fee reminder mailed
May 2, 1996FPAYFee payment
Year of fee payment: 8
Mar 30, 1992FPAYFee payment
Year of fee payment: 4