|Publication number||US4794543 A|
|Application number||US 07/062,377|
|Publication date||Dec 27, 1988|
|Filing date||Jun 15, 1987|
|Priority date||Dec 24, 1984|
|Publication number||062377, 07062377, US 4794543 A, US 4794543A, US-A-4794543, US4794543 A, US4794543A|
|Inventors||Mohammed Enein, Everett P. Strickland|
|Original Assignee||Hazeltine Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (12), Classifications (8), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 685,830, filed 12/24/84, now abandoned.
1. Field of the Invention
The invention generally relates to receivers for receiving scanning signals and, in particular, to an apparatus which receives signals having a predetermined time varying format such as a microwave landing system (MLS) receiver for receiving scanning signals provided by an MLS ground system.
2. Description of the Prior Art
The International Civil Aviation Organization (ICAO) has adopted a time reference scanning beam (TRSB) technique as the standard for civil microwave landing systems. MLS ground systems provide elevation (EL) and azimuth (AZ) scanning beams, each including a TO scan followed by a FRO scan, defining the area of coverage of the ground system. An MLS receiver located in an aircraft receives the EL scan and AZ scan and is able to determine the angular displacement of the MLS receiver in the aircraft with respect to the ground system. To do this, it is necessary to establish the centroids of the spatially received signals which result from the swept EL and AZ scanning beams because the azimuth and elevation angles are a function of the time difference between the TO and FRO scans of each beam.
It is an object of this invention to provide a receiver with a signal processor for determining the centroids of received signals which result from spatially swept scanning beams.
The apparatus according to the invention is for determining the centroid of a received pulse-type signal. The apparatus includes means for detecting the received signal. Means for converting the detected signal into a corresponding digital signal are provided. First threshold detection means are provided for determining the centroid of the digital signal with reference to a first predefined amplitude level below the peak level of the digital signal. Second threshold detection means are provided for determining the centroid of the digital signal with reference to a second predefined amplitude level below the peak of the digital signal. Means are provided for averaging the centroids determined by the first and second threshold means. The average of the centroids represents the time at which the centroid of the received signal occurs.
For a better understanding of the present invention, together with other and further objects, reference is made to the following description, taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.
FIG. 1 is a block diagram of an MLS receiver.
FIG. 2 is a block diagram illustrating a split gate signal processor as part of a digital processor of an MLS receiver as shown in FIG. 1.
FIG. 3 is a block diagram of a multi level split gate signal processor according to the invention.
FIGS. 4a and 4b are graphs illustrating the operation of the multi level split gate preprocessor of FIG. 3.
As illustrated in FIG. 1, the MLS receiver is provided with an antenna switch 1 which connects either the forward antenna or the rear antenna to front end 2. A control unit (not shown) provides channel selection information to frequency synthesizer 3 which, in turn, provides the appropriate reference frequency to front end 2 for down conversion of the received radio frequency (RF) signal to an intermediate frequency (IF). The control unit also provides power "on" information to power supply 4 which supplies voltages to the various components of the receiver.
MLS receivers require an IF amplifier having a dynamic range which exceeds 80 dB. In order to achieve such a dynamic range, the receiver according to FIG. 1 includes an IF amplifier chain including a first IF amplifier 5 followed by a second IF amplifier consisting of linear IF amplifier 6 and logarithmic IF amplifier 7. The chain is followed by a third IF amplifier 8. Linear IF amplifier 6 and third IF amplifier 8 are provided with local oscillator (LO) frequencies by synthesizer 3 depending on the channel selection. This chain of amplifiers is designed with a linear-logarithmic response so that the logarithmic IF amplifier properties may be used without the difficulties attendant with an amplifier having a particular characteristic over the entire range.
For small signals, linear amplifiers 5 and 6 provide sufficient gain for the logarithmic IF amplifier 7 to operate within its range. As the signal level increases beyond an established level on an overall response curve of logarithmic IF amplifier 7, an AGC (automatic gain control) voltage is applied to linear IF amplifier 6 via line 9 to decrease the totl gain of the linear amplifier so that logarithmic IF amplifier 7 is operating within its range. When the signal level provided by linear IF amplifier 6 decreases below an established level on the overall response curve of logarithmic IF amplifier 7, the AGC voltage remains constant and the gain of linear IF amplifier 6 is at a maximum. The result is that the first and linear IF amplifiers 5 and 6, respectively, maintain operation within the logarithmic response of the receiver characteristic as defined by logarithmic IF amplifier 7.
According to the ICAO standard, the scanning signals detected by the receiver are encoded with differential phase shift keying (DPSK) data. The output of third IF amplifier 8 is provided to DPSK demodulator 10 which is followed by Barker synchronization correlator 11 for decoding the data provided to input/output 12. Localizer and glide slope select information from the control unit (not shown) along with the decoded data are provided to the input/output 12 which controls antenna switch 1 and the deviation or "flag" indicators of the receiver. Input/output 12 also provides digital information to the control unit and provides control information to digital processor 13.
After amplification by amplifiers 5 and 6, the video information is provided to logarithmic IF amplifier 7. Logarithmic video information provided by logarithmic IF amplifier 7 is provided to envelope processor 14. Since the receiver operates in a time division multiplexed mode in which the relative amplitudes of successive azimuth and elevation signals of interest may vary greatly but are predictable based on previously received signals, the previously received amplitude levels of the azimuth and elevation signals are stored for use in controlling the gain of linear IF amplifier 6. This allows the appropriate AGC voltage to be applied via line 9 prior to the anticipated detection of each angle function. Digital microprocessor 13 accomplishes this control.
FIG. 2 illustrates in block diagram form the portions of digital microprocessor 13 which are associated with split gate processor 100 according to the invention. Incoming data is demodulated by DPSK demodulator 10 and decoded by Barker syncronization correlator 11. The demodulated data from demodulator 10 is provided to input/output 12 and the correlated data from correlator 11 provides identification information to CPU 17 as well as clock information to real time clock 20. Log video information is converted to digital information by analog-to-digital converter 15 and is stored in first-in-first out (FIFO) memory 41 before processing by split gate processor 100.
In a preferred environment in which multipath and other distortion effects are not present, it is possible to enable a counter when a received pulse-type signal rises above a predetermined value below the peak amplitude of the signal. The counter may then be stopped when the amplitude falls below the same level on the other side of the peak. The centroid is then found by determining from the counter the time between rise and fall and relating it to a reference time. This is known as dwell gate processing. A received signal which is not affected by multipath as illustrated in FIG. 4a may be analyzed in this way. However, when the shape of the received signal within a dwell gate is distorted by a multipath return, as illustrated in FIG. 4b, the apparent centroid is skewed from the true value.
In order to minimize error due to multipath, the invention analyzes the wave shape of the received signal. One way to accomplish this analysis is to establish a number of dwell gates at different levels below the peak of the received signal. In this manner, the centroid of the received signal is determined by observing the time intervals at representative levels of the signal. Generally, three levels are sufficient to define the centroid of the received signal effectively. This is known as a split gate processor.
In order to fully understand the function of split gate processor 100 of the invention as illustrated in FIG. 3, it is necessary to describe the technique used in establishing the thresholds and determining the amplitude of the received pulse-type signal which results from the scanning MLS beam. The detected analog signal is obtained by processing the received signal through a linear/logarithmic amplifier chain as illustrated in FIG. 1 so that the output amplitude is maintained within the limits of the logarithmic transfer function. With such a transfer function, an incremental difference in the input signal is represented by a fixed level at the output at any point within the dynamic range of the system.
As illustrated in FIG. 3, the received signal is digitized by the A/D converter 15 and the results are stored in FIFO memory 41. The peak of the received signal is determined by digital peak detector 101. The peak information is provided to AGC switch 21 for averaging and to one input of threshold detectors 102, 103 and 104. The digitized signal is delayed by delay 120 to compensate for the time it takes peak detector 101 to complete its detection cycle and provide the detected information to an input of threshold detectors 102, 103, and 104. The digitized, delayed signal is then provided to another input of threshold detectors 102, 103, 104 which repectively examine the delayed signal for points 5 db, 3 db, and 1 db below the peak by subtracting the respective numbers representing those relationships from the peak value. Since each measurement is being performed in real time, it is possible to determine when the 5 db point occurs on the rise of the pulse and when it occurs again on the decay. A counter is started when the first 5 db point occurs of the pulse and stopped when the second 5 db point occurs on the decay of the pulse.
In particular, threshold detector 102 detects amplitudes of the delayed, digitized signal which are 1 db below the peak detected by digital peak detector 101. When a signal amplitude of 1 db below the peak is detected, counter 105 is enabled and CPU 17 is signaled via control line 135 to store the time at which counter 105 was enabled. When the signal is again detected on the decay at 1 db below the peak, detector 102 disables counter 105. The total count from counter 105 indicates the time between the 1 db below peak levels. Referring to FIG. 4a, counter 105 would be enabled at time t3 and disabled at time t4 with CPU 17 storing time t3 and counter 105 storing a count representing the total time c between t3 and t4. Referring to FIG. 4b illustrating the multipath case, counter 105 would be enabled at time t11 and disabled at time t12 with CPU 17 storing time t11 and counter 105 storing a count representing the total time f between t11 and t12. Thereafter, CPU 17 performs the necessary calculations to derive the midpoint in time of the period detected at the 1 db below peak level. Similar counting and storing occurs with respect to counters 106 and 107 at the 3 db amd 5 db below peak levels. Eventually, CPU 17 averages the separate times represented by counters 105, 106, and 107 to determine the result of the information provided by all three counters and to determine the centroid of the received signal.
Threshold detector 103 detects amplitudes of the delayed, digitized signal which are 3 db below the peak detected by digital peak detector 101. When a signal amplitude of 3 db below the peak is detected, counter 106 is enabled and CPU 17 is signaled via control line 136 to store the time at which counter 106 was enabled. When the signal is again detected on the decay at 3 db below the peak, detector 103 disables counter 106. The total count from counter 106 indicates the time between the 3 db below peak levels. Referring to FIG. 4a, counter 106 would be enabled at time t2 and disabled at time t5 with CPU 17 storing time t2 and counter 106 storing a count representing the total time b between t2 and t5. Referring to FIG. 4a illustrating the multipath case, counter 106 would be enabled at times t8 and t10 and disabled at times t9 and t13, respectively, with CPU 17 storing time t8 and counter 106 storing a count representing the total time g between t8 and t9 and with CPU 17 storing time t10 and counter 106 storing a count representing the total time e between t10 and t13. Thereafter, CPU 17 performs the necessary calculations to derive (for example by averaging) the midpoints in time of the periods detected at the 3 db below peak levels.
Preferably, CPU 17 is programmed with an algorithm which rejects the extra crossings observed at any level. The result of such rejection is that the total error due to multipath distortion is minimized by the averaging process.
In particular, CPU 17 may be programmed to reject crossing t8 and t9 in the 3 db below peak level. Based on such rejection, CPU 17 performs the necessary calculations to derive the midpoint in time of the unrejected period t10 -t13 detected at the 3 db below peak level. Similarly, all levels below the detected level, i.e. the 5 db below peak level, would be adjusted by subtracting the period between the rejected crossings. Threshold detector 104 detects amplitudes of the delayed, digitized signal which are 5 db below the peak detected by digital peak detector 101. When a signal amplitude of 5 db below the peak is detected, counter 107 is enabled and CPU 17 is signaled via control line 137 to store the time at which counter 107 was enabled. When the signal is again detected on the decay at 5 db below the peak, detector 104 disables counter 107. The total count from counter 107 indicates the time between the 5 db below peak levels. Referring to FIG. 4a, counter 107 would be enabled at time t1 and disabled at time t6 with CPU 17 storing time t1 and counter 107 storing a count representing the total time a between t1 and t6. Referring to FIG. 4b illustrating the multipath case, counter 107 would be enabled at time t7 and disabled at time t14 with CPU 17 storing the enabling time t7. Thereafter, CPU 17 subtracts period g from the total count corresponding to total time d and performs the necessary calculations to derive the midpoint in time of the corrected period detected at the 5 db below peak level. Finally, CPU 17 averages the separate corrected times to determine the result of the information provided by all three counters to determine the centroid of the received signal.
While there have been described what are at present considered to be the preferred embodiments of this invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention and it is, therefore, aimed to cover all such changes and modifications as fall within the true spirit and scope of the invention.
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|U.S. Classification||702/66, 708/200, 342/408, 375/342, 342/94|
|May 26, 1992||FPAY||Fee payment|
Year of fee payment: 4
|Jun 25, 1996||FPAY||Fee payment|
Year of fee payment: 8
|Jun 26, 2000||FPAY||Fee payment|
Year of fee payment: 12