Publication number | US4796260 A |

Publication type | Grant |

Application number | US 07/032,011 |

Publication date | Jan 3, 1989 |

Filing date | Mar 30, 1987 |

Priority date | Mar 30, 1987 |

Fee status | Paid |

Publication number | 032011, 07032011, US 4796260 A, US 4796260A, US-A-4796260, US4796260 A, US4796260A |

Inventors | Donald L. Schilling, David Manela |

Original Assignee | Scs Telecom, Inc. |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (4), Non-Patent Citations (6), Referenced by (168), Classifications (12), Legal Events (5) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 4796260 A

Abstract

A Schilling-Manela encoding method is provided comprising the steps of storing a block of a data-bit sequence in a memory, calculating parity-check symbols from parity-line symbols having p-bits per symbol along parity lines, and setting the parity-check symbols equal to the modulo-2^{p} sum of the parity-line symbols. A Schilling-Manela decoding method is provided comprising the steps of storing an encoded data-bit sequence in a memory. The encoded-data-bit sequence includes a parity-check-symbol sequence which is stored in parity-memory cells, and a data-bit sequence which is blocked and stored in information-memory cells. The parity-check symbols and the parity-line symbols along the parity lines in the information-memory cells are found. The count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error is incremented and the largest-number cell in the composite-error graph having the largest number is determined. The largest number is compared to a threshold, and a new data symbol is chosen to minimize the count in the largest-number cell and substituted into the stored data-bit sequence.

Claims(29)

1. A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing a block of a data-symbol sequence in memory means having g rows by h columns of information-memory cells;

calculating parity-check symbols from parity-line symbols having p-bits per symbol, along a first and a second set of parity lines, each of the first set of parity lines having a straight diagonal path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a straight diagonal path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo-2^{p} the parity-line symbols along each of the parity lines, respectively;

setting the parity-check symbol for each parity line equal to the modulo-2^{p} sum of the parity-line symbols along each parity line, respectively;

storing the parity-check symbols in r parity-memory cells of said memory means, and

outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

2. A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing a block of a data-symbol sequence in memory means having at least g rows by h columns of information-memory cells;

calculating parity-check symbols from parity-line symbols having p bits per symbol, along at least two parity paths having different slopes in the g rows by h columns of said information-memory cells by adding modulo-2^{p} the parity-line symbols along each of the parity paths; and

setting the parity-check symbol for each parity path equal to the modulo-2^{p} sum of the parity-line symbols along each of the parity paths, respectively.

3. The process for encoding the Schilling-Manela error correcting code as set forth in claim 1 or 2, wherein the steps of:

calculating parity-check symbols from parity-line symbols includes calculating parity-check symbols from data symbols; and

setting parity-check symbols for each parity line equal to the modulo-2^{p} sum of the parity-line symbols includes setting the parity-check symbols for each parity line equal to the modulo 2 sum of the data symbols.

4. A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing a block of a data-bit sequence in memory means having g rows by h columns of information-memory cells;

calculating parity-check bits from parity-line bits, along at least a first and a second set of parity lines, each of the first set of parity lines having a straight diagonal path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a straight diagonal path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo 2 the parity-line bits along each of the parity lines, respectively;

setting the parity-check bit for each parity line equal to the modulo 2 sum of the parity-line bits along each parity line, respectively;

storing the parity-check bits in r parity-memory cells of said memory means, and

outputting an encoded data-bit sequence comprising the data bit sequence and the parity-check bits.

5. A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing an encoded-data-bit sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the g rows by h columns of information-memory cells;

finding the parity-check symbols and the parity-line symbols along the parity lines in the g rows by h columns of information-memory cells, having an error;

incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error;

determining the largest-number cell in the composite-error graph having the largest number;

comparing the largest number to a threshold;

determining, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, wherein the new-data symbol minimizes the count in the largest-number cell; and

substituting the new-data symbol into the stored data-symbol sequence.

6. A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing an encoded-data-bit sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells, and a data-bit sequence blocked and stored in the g rows by h columns of information-memory cells;

finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error;

incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error;

determining the largest-number cell in the composite-error graph having the largest number;

comparing the largest number to a threshold; and

inverting, provided the largest number exceeds, the threshold, the data symbol in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell.

7. The process for decoding a Schilling-Manela error correcting and detecting code as set forth in claim 6, further comprising the steps of:

repeating the steps of

finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error;

incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error;

determining the largest-number cell in the composite-error graph having the largest number;

comparing the largest number to a threshold;

inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell;

until the largest number does not exceed the threshold, thereby determining all of the composite cells exceeding a threshold, and testing one at a time by inverting the bit in that composite cell exceeding the threshold and determining a new composite-error graph for each subsequent cell inversion.

8. A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing an encoded-data-bit sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells, and a data-bit sequence blocked and stored in the g rows by h columns of information-memory cells;

finding the parity-check bit and the parity-line bits along a first parity line in the g rows by h columns of information memory cells, having an error;

finding the parity-check bit and the parity-line bits along a second parity line in the g rows by h columns of information memory cells, having an error;

inverting the data bit at the intersection of the first and second parity lines; and

outputting the corrected data-bit sequence.

9. A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing an encoded-data-symbol sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having information symbols blocked and stored in the g rows by h columns of information-memory cells;

finding the parity-check symbol and parity-line symbols along a first parity line in the g rows by h columns of information memory cells, having an error;

finding the parity-check symbol and parity-line symbols along a second parity line in the g rows by h columns of information memory cells, having an error;

comparing the parity-check symbols and parity-line symbols along the first and second parity lines, respectively, for determining the parity-line symbol having an error;

substituting a new-parity-line symbol for the parity-line symbol having an error so that first and second parity lines are not in error; and

outputting the corrected data-symbol sequence.

10. A Schilling-Manela error correcting and detecting code encoding apparatus comprising:

memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-symbol sequence; and

processor means coupled to said memory means for calculating parity-check symbols from parity-line symbols having p-bits per symbol, along a first and a second set of parity lines, each of the first set of parity lines having a straight diagonal path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a straight diagonal path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo-2^{p} the parity-line symbols along each of the parity lines, respectively, and setting the parity-check symbol for each parity line equal to the modulo-2^{p} sum of the parity-line symbols along each parity line, respectively, and storing the parity-check symbols in the r parity-memory cells of said memory means, and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

11. A Schilling-Manela error correcting and detecting code encoding apparatus comprising:

memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-symbol sequence; and

processor means coupled to said memory means for calculating a plurality of parity-check symbols from parity-line symbols having p bits per symbol, along a plurality of parity paths in the g rows by h columns of said information-memory cells by adding modulo-2^{p} the parity-line symbols along each of the parity paths, and setting the parity-check symbol for each parity path equal to the modulo-2^{p} sum of the parity-line symbols along each of the parity paths, respectively.

12. A Schilling-Manela error correcting and detecting code encoding apparatus comprising:

memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-bit sequence; and

processor means coupled to said memory means for calculating parity-check bits from parity-line bits, along a first and a second set of parity lines, each of the first set of parity lines having a path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo 2 the parity-line bits along each of the parity lines, respectively, setting the parity-check bit for each parity line equal to the modulo 2 sum of the parity-line bits along each parity line, respectively, storing the parity-check bits in r parity-memory cells of said memory means, and outputting an encoded data-bit sequence comprising the data bit sequence and the parity-check bits.

13. The Schilling-Manela encoding apparatus as set forth in claim 10 or 12 wherein said processor means calculates parity-check bits along the first set of parity lines having the first diagonal path with a 45° slope and along the second set of parity lines having the second diagonal path with a -45° slope.

14. The Schilling-Manela encoding apparatus as set forth in claim 11 wherein said processor means further includes calculating parity-check bits from data bits along a plurality of independently sloped parity lines in which the slopes may be all positive, all negative or employ some positive and some negative slopes.

15. A Schilling-Manela decoding apparatus comprising:

memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-symbol sequence, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check bits stored in the r parity-memory cells and a data-symbol sequence having information symbols stored in the g rows by h columns of said information-memory cells;

a composite-error graph having g rows by h columns of composite cells; and

processor means coupled to said memory means and said composite-error graph for finding the parity-check symbols and the parity-line symbols along the parity lines in the g rows by h columns of information-memory cells, having an error, incrementing the count of each composite cell on the composite-error graph traversed by the path of each of the parity lines having an error, determining the largest-number cell in the composite-error graph having the largest number, comparing the largest number to a threshold, determining, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, wherein the new-data symbol minimizes the count in the largest-number cell, and substituting the new-data symbol into the information-memory cells.

16. A Schilling-Manela decoding apparatus comprising:

memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-bit sequence, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells and a data-bit sequence having information bits stored in the g rows by h columns of said information-memory cells;

a composite-error graph having g rows by h columns of composite cells; and

processor means coupled to said memory means and said composite-error graph for finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error, incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error, determining the largest-number cell in the composite-error graph having the largest number, comparing the largest number to a threshold, and inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell.

17. A Schilling-Manela decoding apparatus comprising:

memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-bit sequence, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells and a data-bit sequence having information bits stored in the g rows by h columns of said information-memory cells;

a composite-error graph having g rows by h columns of composite cells; and

processor means coupled to said memory means and said composite-error graph for finding the parity-check bit and the parity-line bits along a first parity line in the g rows by h columns of information memory cells, having an error, finding the parity-check bit and the parity-line bits along a second parity line in the g rows by h columns of information memory cells, having an error, inverting the data bit at the intersection of the first and second parity lines, and outputting the corrected data-bit sequence.

18. A process for communicating in an ARQ system with the Schilling-Manela FEC and detection code comprising the steps of:incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error;

storing a block of a data-symbol sequence in transmit-memory means having at least g rows by h columns of information-memory cells;

calculating parity-check symbols from parity-line symbols having p bits per symbol, along at least two parity paths having different slopes in the g rows by h columns of said information-memory cells by adding modulo-2^{p} the parity-line symbols along each of the parity paths;

setting the parity-check symbol for each parity path equal to the modulo-2^{p} sum of the parity-line symbols along each of the parity paths, respectively;

transmitting an encoded-data-symbol sequence over a communications channel having a feedback channel, wherein said encoded-data-symbol sequence includes the parity-check-symbol sequence and the data-symbol sequence;

storing the encoded-data-symbol sequence in receiver-memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error;

determining the largest-number cell in the composite-error graph having the largest number;

comparing the largest number to a threshold;

inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell;

sending a retransmit request to the transmitter if some errors are not correctable;

generating a second set of parity-check symbols from the data-bit sequence stored in the transmit memory means;

sending the second set of parity-check symbols over the communications channel; and

using the second set of parity-check symbols, repeating the steps of

finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error;

determining the largest-number cell in the composite-error graph having the largest number;

comparing the largest number to a threshold;

inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell.

19. A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of:incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error;

storing an encoded-data-bit sequence in memory means having λ-dimensional information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the λ-dimensional information-memory cells;

finding the parity-check symbols and the parity-line symbols along the parity lines in the information-memory cells, having an error;

determining the largest-number cell in the composite-error graph having the largest number;

comparing the largest number to a threshold;

determining, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, wherein the new-data symbol minimizes the count in the largest-number cell; and

substituting the new-data symbol into the stored data-symbol sequence.

20. A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing an encoded-data-symbol sequence in memory means having λ-dimensional information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having information symbols blocked and stored in the λ-dimensional information-memory cells;

finding the parity-check symbol and parity-line symbols along a first parity line in the information memory cells, having an error;

finding the parity-check symbol and parity-line symbols along a second parity line in the information memory cells, having an error;

comparing the parity-check symbols and parity-line symbols along the first and second parity lines, respectively, for determining the parity-line symbol having an error;

substituting a new-parity-line symbol for the parity-line symbol having an error so that first and second parity lines are not in error; and

outputting the corrected data-symbol sequence.

21. A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing an encoded-data-bit sequence in memory means having information-memory cells and r parity-memory cells, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells, and a data-bit sequence having information bits blocked and stored in the information-memory cells;

finding the parity-check bit and parity-line bits along a first parity line in the information memory cells, having an erasure; and

setting the erasure equal to the modulo 2 sum of the parity check bits plus the parity lines bits along the parity line.

22. A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing an encoded-data-symbol sequence in memory means having information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having information symbols blocked and stored in the information-memory cells;

finding the parity-check symbol and parity-line symbols along a first parity line in the information memory cells, having an erasure; and

setting the erasure equal to the modulo 2^{p} sum of the parity check symbols plus the parity lines symbols along the parity line.

23. A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells;

calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, by setting the parity-check symbol for each of the first set of parity-check symbols for each parity line equal to the modulo-2^{p} sum of the data symbols along each parity line, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells, and said first set of parity-check symbols forms a first parity row located in said parity-check memory cells;

calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, by setting the parity-check symbol for each of the second set of parity-check symbols for each parity line equal to the modulo-2^{p} sum of the data symbols along each parity line, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells, and said second set of parity-check symbols form a second parity row located in said parity-check memory cells; and

outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

24. A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of:

storing a block of a data-symbol sequence having data symbols with P-bits pre symbol, in memory means having information-memory cells and parity-check memory cells;

calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, by setting the parity-check symbol for each of the first set of parity-check symbols for each parity line equal to the modulo-2^{p} sum of the data symbols along each parity line, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells, and said first set of parity-check symbols forms a first parity row located in said parity-check memory cells;

calculating a second set of parity-check symbols from the data symbols along a second set of parity lines, by setting the parity-check symbol for each of the second set of parity-check symbols for each parity line equal to the modulo-2^{p} sum of the data symbols along each parity line, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells, and said second set of parity-check symbols form a second parity row located in said parity-check memory cells;

calculating at least a third set of parity-check symbols from the data symbols along a third set of parity lines, by setting the parity-check symbol for each of the third set of parity-check symbols for each parity line equal to the modulo-2^{p} sum of the data symbols along each parity line, wherein each parity line of the third set of parity lines has a path with a third slope traversing through said information-memory cells, and said third set of parity-check symbols form a third parity row located in said parity-check memory cells; and

outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

25. A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of:outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells;

calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells;

calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has path with a second slope traversing through said information-memory cells; and

26. A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of:outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells;

calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells;

calculating a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells;

calculating at least a third set of parity-check symbols from the data symbols along a third set of parity lines, wherein each parity line of the third set of parity lines has a path with a third slope traversing through said information-memory cells; and

27. A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of:storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells;

storing said first set of parity-check symbols in a first parity row located in said parity-check memory cells;

calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells;

storing said second set of parity-check symbols in a second parity row located in said parity-check memory cells; and

28. A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of:storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells; outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

storing said first set of parity-check symbols in a first parity row located in said parity-check memory cells;

calculating a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells;

storing said second set of parity-check symbols in a second parity row located in said parity-check memory cells;

calculating at least a third set of parity-check symbols from the data symbols along a third set of parity lines, wherein each parity line of the third set of parity lines has a path with a third slope traversing through said information-memory cells;

storing said third set of parity-check symbols in a third parity row located in said parity-check memory cells; and

29. A Schilling-Manela error correcting and detecting code encoding apparatus comprising:

memory means coupled to a data source for storing a block of a data-symbol sequence; and

processor means coupled to said memory means for calculating first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells, and said first set of parity-check symbols forms a first parity row located in said parity-check memory cells, calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells, and said second set of parity-check symbols form a second parity row located in said parity-check memory cells, and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Description

This invention relates to forward error correction and detection codes, and more particularly to a forward error correction and detection code method and apparatus having parity check bits (or symbols) added to information bits (or symbols) to form a codeword.

This patent is related to the following patent applications: Donald L. Schilling and David Manela, "PASM and TASM Forward Error Correction and Detection Code Method and Apparatus," Ser. No. 07/080,767, filed Aug. 3, 1987; Donald L. Schilling and David Manela, "SM Codec Method and Apparatus," Ser. No. 07/122,948, filed Nov. 19, 1987; and, Donald L. Schilling and David Manela, "PASM and TASM Forward Error Correction and Detection Code Method and Apparatus," Ser. No. 07/119,932, filed Nov. 13, 1987.

A forward error correction (FEC) or detection code has r bits, called parity check bits, added to k information data bits to form an n=k+r bit codeword. The r parity-check bits are added in such a way as to allow a specified number of errors to be detected or corrected. The algorithm employed to generate the r parity-check bits for given information bits differs for each code.

Specific forward error correction and detection codes which are well known in the prior art include the Reed-Solomon code, the Golay code, error correcting/detecting codes using the Hadamard matrix, the BCH code and the Hamming code. Each of these codes employs a different algorithm for generating the parity check bits and a different algorithm for recovering the original k data bits or for detecting errors. Texts describing such prior art codes include: H. Taub and D. L. Schilling, Principles of Communication Systems, 2 Ed., McGraw-Hill Book Company (1986); S. Lin and D. J. Costello, Jr., Error Control Coding: Fundamentals and Applications, Prentice-Hall, Inc., (1983); and R. G. Gallager, Information Theory and Reliable Communications, John Wiley and Sons, Inc., (1968).

The forward error correction and detection codes are characterized by their algorithm for encoding and decoding and also by several other properties:

1. Code rate, R: The code rate is the ratio of information data bits, k, to the sum, n, of information data bits and parity check bits, r. Thus, the number of bits in a codeword is n=k+r and the code rate R=k/n.

2. Hamming distance. The minimum number of bits by which codewords differ is called the Hamming distance, d. If there are k information bits in an uncoded word, there are 2^{k} possible uncoded information words. For example, if k =4 there are 16 possible uncoded words: 0000, . . . ,1111. An error in any bit will make the word look like a different one of the 2^{k} words and therefore an error cannot be detected or corrected. However, if r parity check bits are added to the k-bit uncoded word, an n-bit codeword is formed. Hence, there are 2^{n} possible words of which only 2^{k} are used. The selection of the codewords so as to ensure a maximum separation between the codewords is what makes a good code. For example, a Hamming code containing k= 4 information bits and n=7 coded bits has 2^{4} =16 codewords of a possible 2^{7} =128 words. This is called a (n,k) or (7,4) code of rate R=4/7. These codewords are selected so that each codeword differs by 3 bits. Thus, a single error can be detected and corrected while two errors on a codeword cannot be corrected. In the above example, d=3.

3. Error Detection: In general, codes can detect d-1 errors in a codeword.

4. Error Correction: In general, a code can correct t errors in a codeword, where ##EQU1## depending on whether d is odd or even, respectively. An approximate upper bound on the number of errors, t, that a code can correct is

t≦r/4+1/2 (2)

5. Erasures: Side information can be used to ascertain that specific bit(s) in a codeword had an increased probability of error. On such occasions those bits can be erased, replacing them by an X rather than by a 1 or 0 in the decoding algorithm. The number of erasures that a code can correct in a codeword is

E≦d-1 (3)

If errors and erasures can both occur in a codeword

d>E+2t (4)

For example, if d=8, and there are 1 erasure and 2 errors present, the decoded word will be corrected.

6. Burst Codes: Some codes are designed so that errors can be efficiently corrected if they occur randomly, while other codes are designed so that they can correct a burst, or cluster, of bits where each bit may be in error with high probability. Such codes are called burst correction codes and can correct bursts of length B bits provided that an error-free gap of G bits occurs between bursts. The Reiger bound states that ##EQU2## The Reed-Solomon code is an example of a burst correcting code capable of correcting either errors or erasures.

7. Concatenation: Concatenation is encoding data using one code and then the encoded data again is encoded using a second code. A reason for using concatenation is that one code can correct random errors and when failing will generate a burst of errors which the second code can correct. A convolutional code frequently is concatenated with a Reed-Solomon code.

An object of the present invention is to provide a forward error correction (FEC) and detection code method and apparatus.

Another object of the present invention is to provide an FEC and detection code method and apparatus that is very efficient for burst error detection and correction.

A further object of the present invention is to provide an FEC and detection code for operating in an ARQ system using efficient code combining.

A still further object of the present invention is to provide an FEC and detection code capable of correcting errors and/or erasures.

A further object of the present invention is to provide an FEC and detection code method and apparatus that is easier to implement than many prior art codes.

An additional object of the present invention is to provide an FEC and detection code method and apparatus that is more powerful and less complex than many prior art codes.

According to the present invention, as embodied and broadly described herein, a Schilling-Manela encoding method is provided comprising the steps of storing a block of a data-symbol sequence in memory means having g rows by h columns of information-memory cells, calculating parity-check symbols from parity-line symbols having p-bits per symbol, along at least a first and a second set of parity lines. Each of the first set of parity lines can have a straight diagonal path with a first slope through the g rows by h columns of the information-memory cells and each of the second set of parity lines can have a straight diagonal path with a second slope through the g rows by h columns of the information-memory cells. Alternatively, each of the first and second set of parity lines can have curved paths through the g rows by h columns of the information-memory cells. The parity-check symbols are calculated by adding modulo-2^{p} the parity-line symbols along each of the parity lines, respectively, and setting the parity-check symbol for each parity line equal to the modulo-2^{p} sum of the parity-line symbols along each parity line. The parity-check symbols are stored in r parity-memory cells of the memory means, and an encoded-data-bit sequence is outputted comprising the data-bit sequence and the parity-check symbols.

The present invention also includes a Schilling-Manela decoding method comprising the steps of storing an encoded data-symbol sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein the encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the g rows by h columns of information-memory cells. The parity-check symbols and the parity-line symbols along the parity lines in the g rows by h columns of information-memory cells, having an error, are found. The count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error is incremented and the largest-number cell in the composite error graph having the largest number is determined. The largest number is compared to a threshold, and provided the largest number exceeds the threshold, a new-data symbol is determined for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite error graph having the largest number. The new-data symbol is chosen to minimize the count in the largest-number cell, and the new-data symbol is substituted into the stored data-bit sequence.

The present invention further includes an apparatus for encoding and decoding a Schilling-Manela forward error correction and detection code. The apparatus for encoding a Schilling-Manela error correction code comprises memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-symbol sequence, and processor means coupled to the memory means for calculating parity-check symbols from parity-line symbols having p-bits per symbol, along a first and a second set of parity lines. Each of the first set of parity lines may have a straight diagonal path with a first slope through the g rows by h columns of the information-memory cells. Each of the second set of parity lines may have a straight diagonal path with a second slope through the g rows by h columns of the information-memory cells. Alternatively, each of the first and second set of parity lines can have curved paths through the g rows by h columns of the information-memory cells. The processor means may be embodied as a processor. The processor adds modulo-2^{p} the parity-line symbols along each of the parity lines, respectively, and sets the parity-check symbol for each parity line equal to the modulo-2^{p} sum of the parity-line symbols along each parity line, respectively. The processor stores the parity-check symbols in the r parity-memory cells of the memory means, and outputs an encoded data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

The apparatus for decoding a Schilling-Manela error correction code comprises memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded data-symbol sequence, a composite-error graph having g rows by h columns of composite cells, and processor means coupled to the memory means and composite-error graph for finding the parity-check symbols and the parity-line symbols along the parity lines in the g rows by h columns of information-memory cells, having an error. The encoded data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells and a data-symbol sequence having information-symbols stored in the g rows by h columns of the information-memory cells. The processor increments the count of each composite cell on the composite-error graph traversed by the path of each of the parity lines having an error, determines the largest-number cell in the composite-error graph having the largest number, and compares the largest number to a threshold. Provided the largest number exceeds the threshold, the processor determines a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number. The new-data symbol minimizes the count in the largest-number cell, and the processor substitutes the new-data symbol into the stored data-symbol sequence. This process is repeated until the largest number found does not exceed the threshold, at which time the decoding process ceases.

Without departing from the spirit or scope of the present invention, the method and apparatus of the present invention may include having the data-symbol sequence blocked and stored in a λ-dimensional memory. In this more general case, there would be sufficient rows and columns to correspond to the λ-dimensional system. Further, parity-check symbols can be calculated from parity-line symbols along parity lines having curved paths passing through the λ-dimensional system.

Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate a preferred embodiment of the invention, and together with the description, serve to explain the principles of the invention.

FIG. 1 shows a flow diagram of a Schilling-Manela encoding method according to a first embodiment of the present invention;

FIG. 2A shows a g×h block of data in which the data was entered row by row;

FIG. 2B shows a g×h block of data in which the data was entered column by column;

FIG. 3 shows a flow diagram of a first species of a Schilling-Manela decoding method according to the present invention;

FIG. 4A shows an encoded data block;

FIG. 4B illustrates a possible transmission by row;

FIG. 4C illustrates a received codeword with an error;

FIG. 4D shows a graph after all checks are made;

FIG. 4E illustrates a composite-error graph;

FIG. 5 shows a partially decoded word;

FIG. 6A shows a resulting composite-error graph;

FIG. 6B shows a resulting partially decoded word;

FIG. 7 shows a resulting composite-error graph;

FIG. 8 shows a flow diagram of a second species of a Schilling-Manela decoding method according to the present invention;

FIG. 9A shows a code block of (g=6, h=10) gh=60 data bits;

FIG. 9B shows parity-check bits from a parity line that is vertical (pc)_{1} and from a parity line that is at 45° (pc)_{2} ;

FIG. 10 illustrates that when two parity lines are in error, their intersection indicates that the bit in row 3 and column 4 is in error and should be inverted;

FIG. 11A shows an encoded data block;

FIG. 11B illustrates a possible transmission by row;

FIG. 11C illustrates possible received bits with burst errors in the top row;

FIG. 11D illustrates the error graph and that when parity lines are all positive slope, the cell having the largest value in the lowest column and in the lowest number row is selected;

FIG. 11E illustrates a partially corrected bit pattern;

FIG. 11F illustrates the partially corrected error graph;

FIG. 11G and 11H illustrate additional corrections;

FIG. 12 illustrates that a simple erasure on bit location (2,4) can be corrected by the column four vertical parity line;

FIG. 13 illustrates that erasure along the diagonal can be corrected;

FIG. 14A and 14B show block diagrams of Schilling-Manela encoding and decoding apparatus according to the present invention; and

FIG. 15 shows how the Schilling-Manela FEC and detection code can be used in an Automatic Repeat Request System.

Reference will now be made to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings.

Referring to FIG. 1, a preferred embodiment of a Schilling-Manela error correcting and detecting code encoding method is shown comprising the steps of entering and storing 110 a block of a data-bit sequence in memory means having g rows by h columns of information-memory cells. The memory means may be embodied as a memory including a random access memory, or any other memory wherein data readily may be accessed. The memory may include r parity-memory cells for storing r parity symbols. The method includes calculating 112 parity-check symbols from parity-line symbols having p-bits per symbol. The plurality of parity-line symbols typically are along a plurality of parity paths. The parity paths may be parity lines, L_{i}. The parity-check symbols S_{i} are stored 114 in the r parity-memory cells. The method determines I16 whether all the parity-check symbols, I_{max}, have been calculated, and outputs 120 an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols. If all the parity-check symbols, S_{i}, have not been calculated, then the process increments 118 to the next parity line and calculates the next parity symbol, S_{i+1}.

In a first preferred embodiment of the encoding method according to the present invention, the parity-check symbols may be parity-check bits, and the parity-line symbols may be parity-line bits. In this first embodiment, the method may comprise calculating parity-check bits from parity-line bits, along a first and a second set of parity lines. Each of the first set of parity lines can have a straight diagonal path with a first slope through the g rows by h columns of the information-memory cells. Each of the second set of parity lines can have a straight diagonal path with a second slope through the g rows by h columns of the information memory cells. Alternatively, each of the first and second set of parity lines can have curved paths through the g rows by h columns of the information-memory cells. The parity-check bits are calculated by adding modulo 2 the parity-line bits along each of the parity lines, and setting the parity check bit for each parity line equal to the modulo 2 sum of the parity-line bits along each parity line, respectively. Accordingly, the parity-check bits are stored in the r parity-memory cells of the memory.

A second preferred embodiment of the Schilling-Manela error correcting and detecting encoding method using the flow chart of FIG. 1, includes entering the data to form a g row by h column data block in the information-memory cell. In an optimal mode, the parity-check bits are calculated by starting with the parity lines having either all positive or all negative slopes. The first parity line starts with the bit (1,1) and the last parity line includes bit (g,h). The slope i is then incremented and the process is repeated. If negative slope lines are used, then the same process is employed to calculate all parity check bits of each line of slope i. Now, however, the process starts with bit (1,h) and ends with bit (g,1). When i=I_{max} the process is completed and all data bits and all parity check bits are transmitted. It is in the spirit of this invention that each parity line includes each bit (or symbol) and it is not important which order the parity lines are obtained.

The information data bits are first collected by the encoder to form a g row by h column block of data in the information memory cells, as shown in FIG. 2A and 2B. Note, that the data can be entered into the encoder row-by-row, as illustrated in FIG. 2A, or column-by-column, as illustrated in FIG. 2B. After the block of data is entered into the encoder, parity-check bits are added. To illustrate the algorithm for adding parity-check bits consider that the first h parity-check bits are obtained by modulo 2 adding a column of data-bits and setting the parity-check bit so that the parity-check bit is equal to the modulo 2 sum of the data bits. Thus, in FIG. 2B, for the i^{th} column, the i^{th} parity-check bit is ##EQU3## where i=0, 1, 2, . . . , h-1

Let us further assume that the second set of parity-check bits are formed by modulo 2 adding the data bits along a 45° diagonal (slope=+1). Thus, in FIG. 2B, ##EQU4## where i=-g+1, . . . , 0, 1, 2, . . . , h-1

According to the present invention, parity-check bits can be formed from different diagonals and the diagonals can have a positive or a negative slope. The spirit of the invention is that any selection of data bits, be it on a straight diagonal line or a curved line can be used to generate the parity check bits. Each such line is called a parity line.

Referring to Equation 7, there are values of

a.sub.(i+j)g-(j-1) (8)

which are non-existent. For example, consider i=h-1 and j=2. In this case one has a.sub.(h+1)g-1. Since gh is the largest subscript possible, a.sub.(h+1)g-1 is non-existent. Whenever such a non-existent data bit is required, it is assumed to be a 0-bit. Assuming such data bits to be a 1-bit does not alter the spirit of the present invention but merely its implementation. Conceptually, one can imagine that the data block shown in FIG. 2A and 2B has 0-bits in all columns to the left and to the right of the data block. These 0-bits are not transmitted and therefore do not affect the code rate.

The rate of the Schilling-Manela error correcting and detecting code is a function of the number of rows g, columns h, and the number and the slope of parity lines, i.e., different sloped lines, w, used, where w=r/h. The code rate R is approximately given by ##EQU5##

According to the present invention a Schilling-Manela decoding method is provided. A first species of the Schilling-Manela decoding method according to the present invention, as illustrated in FIG. 3, includes the steps of entering, blocking and storing 210 an encoded-data-symbol sequence in memory means having at least g rows by h columns of information-memory cells, and r parity-memory cells with w parity lines. The memory means may be embodied as a memory including a random access memory, or any other memory wherein data readily may be accessed. The encoded-data-symbol sequence includes r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the g rows by h columns of the information-memory cells.

The first species of the Schilling-Manela decoding method includes finding 212 the parity-check symbols and the parity-line symbols along the parity lines L_{i} in the g rows by h columns of the information memory cells, having an error. At the same time, the method uses a graph, and enters a 1-bit on each cell in the graph traversed by the path of each parity line L_{i} having an error. At the end of generating a graph for each parity line L_{i} having an error, the graphs generated from each parity line L_{i} are added together to make a composite-error graph. Alternatively, the method can employ a composite-error graph directly, and increment 214 the count of each composite cell on the composite-error graph traversed by the path of each of the parity lines having an error.

The first species of the Schilling-Manela decoding method according to the present invention, determines 216 whether all the parity lines having an error have been entered onto the composite-error graph, and determines 218 the largest-number cell in the composite-error graph having the largest number. Accordingly, the largest number is compared 220 to a threshold and, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells which corresponds to the largest number cell in the composite-error graph having the largest number, is determined 222. For optimum performance of burst error correction, the threshold might be set to be greater than or equal to w/2. For optimum performance of random error correction, the thresholds might be set to be greater than or equal to w/2+1. The new-data symbol is chosen so as to minimize the cell count in the largest number cell on the composite-error graph. The new-data symbol is substituted into the information-memory cells. In the event the largest number does not exceed the threshold, then the Schilling-Manela decoding method outputs 226 the data.

To illustrate the first species of the Schilling-Manela decoding method, consider the encoded data block as shown in FIG. 4A which may be transmitted by row as shown in FIG. 4B. Note that the code rate is ##EQU6## The received codeword with errors is shown in FIG. 4C. In this particular embodiment of the first species of the Schilling-Manela decoding method, the parity-check symbols are parity-check bits and the parity-line symbols are parity-line bits. The modulo 2 sum of each and every parity line is computed for each slope. In this example, there are six vertical parity lines, eight 45° parity lines and eight -45° parity lines. If any parity line is in error a 1-bit is entered in the cells traversed by the path of the parity line, of a graph. If the parity line is not in error a 0-bit is entered in the cells traversed by the path of the parity line, of a graph. FIG. 4D shows the graphs after a vertical check, a +45° check and a -45° check was taken. Note that the vertical check "sees" a error in columns 3 and 5, and that 2 diagonals indicate errors in the +45° diagonal check and that 2 diagonals indicate errors in the -45° diagonal check.

A composite-error graph, shown in FIG. 4E, is formed. The graph includes composite cells showing the sum of the errors. The maximum number in a composite cell is equal to the number of parity check rows employed. A typical threshold might be T-1, indicating that peak values of 2 or 3 are used as error indicators. To correct an error each cell is searched to find the largest number on the composite-error graph. If only a single composite cell contains this largest number, then the bit in that row and column is inverted and the procedure is repeated. In FIG. 4E row 2, column 3, is selected and that bit, (2,3) is inverted. The process is repeated using the partially decoded word shown in FIG. 5.

Proceeding as above, the next composite map is as shown in FIG. 6A and the next partial decoding is shown in FIG. 6B. FIG. 7 shows that all errors have been corrected.

If erasures and error are present simultaneously in a received data block then each erasure is first replaced by a 1 and then by a 0. In each case each cell in the composite-error graph receives a number denoting the number of parity check lines containing errors caused by each selection for the erasures. The bit selection chosen is the one which minimizes the number in the cell containing the erasure. Then, the standard error correction is performed.

A second species of the Schilling-Manela decoding method according to the present invention, as illustrated in FIG. 8, includes the steps of entering, storing and blocking 150 an encoded-data-symbol sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells. The encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having gh information symbols blocked and stored in the g rows by h columns of information-memory cells. The method includes finding 152 the parity-check symbol and parity-line symbols along a first parity line, L_{j}, in the g rows by h columns of information memory cells, having an error, storing parity line, L_{j}, and finding 156 the parity-check symbol and parity-line symbols along a second parity line, L_{k}, in the g rows by h columns of information memory cells, having an error. The steps further include comparing 160 the parity-check symbols and parity-line symbols along the first and second parity lines, respectively, for determining the parity-line symbol having an error, and substituting 162 a new-parity-line symbol for the parity-line symbol having an error so that first and second parity lines are not in error. The decoding method determines 164, 168 whether all parity lines having an error have been processed, and increments 166, 170 to a next parity line if they have not all been processed. If all the parity lines have been compared, then the corrected data-bit sequence is outputted 172.

To illustrate a particular preferred embodiment of the second species of the Schilling-Manela decoding method according to the present invention, consider the input data-bit sequence being blocked and stored as a code block having g=6 rows and h=10 columns, shown in FIG. 9A.

The encoded data sequence is shown in FIG. 9B. The received encoded-data bits have errors or erasures. Referring to FIG. 10, each positive slope (45°) parity line is checked until a line is found which indicates errors and which has the left most footprint. The footprint is defined as the bit occurring in row g at the most left hand column. A second line of different (vertical) slope having the next earliest footprint is selected. The intersection of these two lines is the bit which is in error. This bit is inverted. Each parity line is rechecked, since correcting an error will alter the error status of some of the parity lines. This process is continued both from the left (positive sloped lines) and then from the right (negative sloped lines) until there are no bit changes occurring in a cycle. If there are still parity lines in error, the errors exist but cannot be corrected. For example, if there were two errors in the parity-check bits, one in row 1, column 6, and the other in row 8, column 8, then an error would be created in cell (3,8).

To illustrate the burst error correction capability of the Schilling-Manela encoder and decoder consider the data block and parity-check bits shown in FIG. 11A. Note that for optimal performance all parity lines must be in the same direction and should be interleaved with data rows. These bits are transmitted, row by row as shown in FIG. 11B. Interleaving is not shown in this example. There are 18 information bits, 18 parity check bits and therefore 36 transmitted bits. Thus the code rate is R=18/36=0.5.

FIG. 11C shows that the bits are received with row one in error.

FIG. 11D shows a composite-error graph indicating a burst of errors. The procedure is to select the bit in row 1, column 1, for inversion when the parity lines are positive.

FIG. 11E shows the partially decoded word and FIG. 11F shows the resulting error graph. Next invert the bit adjacent to the 0 providing the threshold is exceeded. In this case T=1. FIG. 11G shows the partially decoded word and 11H indicates the cell exceeding the threshold adjacent to the 0. This procedure continues until the maximum number in a cell is less than the threshold. For this example, the process continues until the number in the cells decreases below 2. In general, if there are w parity lines, then w/2-1 is the desired threshold. If w=2, then the threshold is w/2.

Note, that in general, all combinations can be attempted, and the combination resulting in a minimized cell count, chosen.

To illustrate the operation of the Schilling-Manela error correcting and detecting code, consider the rate R=0.7 code shown in FIG. 9A and 9B. FIG. 9B shows the parity check bits (pc), formed from the 45° parity lines. Note that (pc)_{2} contains h+(g-1) bits in order that a (pc)_{2} bit be generated for each and every 45° line. The data bits and the parity check bits are now transmitted row by row. Such transmission is required for error decoding.

If any bit is received in error, two parity check lines, one from the (pc)_{1} lines and one from the (pc)_{2} lines will not add to 0. Their intersecticn is the bit which is in error. If a burst of errors occurs such that the probability of an error in any bit in the sequence is P_{ii} then the vertical parity lines will denote errors. Starting with the diagonal parity line on the left and moving toward the right the parity lines with errors, one-by-one, are check for intersections.

For example, the data stream shown in FIG. 9B is received as shown in FIG. 10. Note that a vertical and a horizontal parity line indicate an error. Thus the bit which is common to both lines is assumed to be in error and is inverted in the decoder.

If, in FIG. 10, bit (2,4) were erased then either the vertical parity line or diagonal parity line containing this bit could be used to determine the correct bit. This conclusion is made apparent by referring to FIG. 12. Since there are an odd number of 1-bis in column 4, and even parity has been assumed (odd parity could also be used) the (2,4) bit must be a 1-bit.

However, the power of erasure decoding occurs in the erasure pattern shown in FIG. 13. Note that by using the vertical parity line of column 4, the erasure at bit (3,4) is set equal to 1. Then the erasure at (2,5) is corrected by using the diagonal parity line d to set bit (2,5) equal to 0. Finally, either the vertical parity line of column 5 or the diagonal parity line e can be used to set bit (3,5) equal to 1.

The use of additional diagonal parity lines of either positive or negative shape serves to increase the power of the code. In a particular embodiment, 45° diagonal (slope 1/1=1), vertical and -45° diagonal (slope=-1) parity lines have been used. Also, the number of parity lines can be increased to 4 and to 5 by adding parity lines of slope ±1/2.

Using negative parity lines the decoding method can be from left-to-right and also from right-to-left.

Further, since intersections having errors are being searched, such intersections can be calculated in parallel and not necessarily restricted to a sequential search which was described above decoding algorithms, of which there are many, can use this information.

The Schilling-Manela error correcting and detecting code can be concatenated with any other code. One preferred approach is to form a codeword using each row or by using each column. However, diagonal codewords can also be used.

For example, if the Schilling-Manela error correcting and detecting code is constructed using rows containing m=11 bits, then by adding the appropriate 5 additional bits to each row forms an extended Hamming code on each row. The Hamming code can correct a single error per row and detect up to 4 errors.

In such a receiver, the Hamming code is first decoded. The resulting Schilling-Manela error correcting and detecting code encoded word now has been partially corrected and where not corrected we know, with high probability, in which rows errors exist.

The present invention further includes an apparatus for encoding and decoding a Schilling-Manela error correction code. The apparatus for encoding a Schilling-Manela error correction code, as illustrated in FIG. 14A, comprises memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-bit sequence, and processor means coupled to the memory means for calculating parity-check symbols from parity-line symbols having p-bits per symbol, along a first and a second set of parity lines. The memory means may be embodied as memory 510 and processor means may be embodied as processor 512.

In the memory, each of the first set of parity lines may have a straight diagonal path with a first slope through the g rows by h columns of the information-memory cells. Each of the second set of parity lines may have a straight diagonal path with second slope through the g rows by h columns of the information-memory cells. The processor 512 adds, modulo-2^{p}, the parity-line symbols along each of the parity lines, respectively, and sets the parity-check symbol for each parity line equal to the modulo-2^{p} sum of the parity-line symbols along each parity line, respectively. The processor 512 stores the parity-check symbols in the r parity-memory cells of the memory 510, and outputs an encoded-data-bit sequence comprising the data-bit sequence and the parity-check symbols.

The apparatus for decoding a Schilling-Manela error correction code, as shown in FIG. 14B, comprises memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-symbol sequence, a composite-error graph 534 having g rows by h columns of composite cells, and processor means coupled to the memory means and composite-error graph 534 for finding the parity-check symbols and the parity-line symbols along the parity lines in the g rows by h columns of information-memory cells, having an error. The processor means may be embodied as processor 532 and memory means may be embodied as memory 530. The encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells and a data-symbol sequence having information-symbols stored in the g rows by h columns of the information-memory cells. The processor 532 increments the count of each composite cell on the composite-error graph traversed by the path of each of the parity lines having an error, determines the largest-number cell in the composite-error graph 534 having the largest number, and compares the largest number to a threshold. Provided the largest number exceeds the threshold, the processor 532 determines a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number. The new-data symbol minimizes the count in the largest-number cell, and the processor 532 substitutes the new-data symbol into the stored data-bit sequence.

Consider communicating using the Schilling-Manela error correcting and detecting code when a feedback channel is available as shown in FIG. 15. If errors are detected and are too numerous to be corrected, the feedback channel is used to notify the encoder. The encoder then sends one or more additional rows of parity check bits which significantly increases the power of the code.

In any ARQ system the probability of an undetected error is of extreme importance. Here, if each parity line checks the data only, then the probability of an undetected error, P_{und}, is

P_{und}αp^{w+1}

where p is the probability of a bit being in error and w is the number of different sloped parity lines. If each sloped line checks all data and the previously evaluated parity lines, then P_{und} decreases dramatically.

Using this system, the average code rate remains high and only those messages which were initially received incorrectly, need have additional parity check bits sent.

In this system a block of data D_{1} is encoded with w parity lines. For example, let w=12. The block of data D_{1} is transmitted with w_{11} <w parity lines. For example, let w_{11} =4. At the receiver, error correction occurs. If the errors are all corrected, the data is outputted. If some errors are not correctable, the received data block D_{1} and the associated w_{1} parity lines are stored. A retransmit request is returned to the sender.

Depending on system delays a data block D_{2} is sent with w_{22} parity lines and w_{21} parity lines which came from block of data D_{1} and which was stored in memory. If w_{11} =4 and w_{21} =4, then at the receiver the FEC code decodes data block D_{1} and again decodes data bIock D_{1} now using w_{11} +w_{21} parity lines. For example, if w_{11} =4, then the probability of a bit error in D_{1} after the first decoding is of the order p_{1} αp^{2}, while since w_{11} +w_{21} =8, the probability of a bit error in D_{2} after the second decoding is p_{2} αp^{4}.

This technique is more efficient than other ARQ systems since only a new set of parity-check bits are retransmitted, while other techniques retransmit the entire data block. Also, the power of the code increases as the sum of the number of parity lines received. Other codes do not have this capability.

The encoder apparatus and procedures described above used parity check lines to modulo-2^{p} sum the data symbols along each parity line. It is within the spirit of this invention to have an encoding procedure for summing data symbols along parity lines having a first slope, then sum the data symbols and the first parity-check symbols along parity lines having a second slope, sum data symbols and the first and second parity line check symbols along parity lines having a third slope, etc. The first, second, third, . . . , w^{th} slopes can be chosen arbitrarily. The decoding method and apparatus for this extension of encoding remains unchanged.

The invention described above is a special case of a 2-dimensional array. It is within the spirit of the present invention that a 3-dimensional array of data symbols can be formed and parity check symbols obtained in the encoder. The decoder method and apparatus would operate the same as described above. Further, it is within the spirit of the present invention that a λ-dimensional array of data symbols be formed and the same encoding and decoding procedures be employed. In this more general case, there would be sufficient rows and columns to correspond to the λ-dimensional system. Further, parity-check symbols can be calculated from parity-line symbols along parity lines having curved paths passing through the λ-dimensional system.

The Schilling-Manela code is a very efficient burst detecting and correcting code. It meets the Reiger bound. However, the Schilling-Manela error correcting and detecting code can correct, more random errors per codeword than the Reed-Solomon code and is easier to implement. Thus, the Schilling-Manela error correcting and detecting code is more powerful and less complex than the other competitive code.

It will be apparent to those skilled in the art that various modifications can be made to the Schilling-Manela forward error correction and detection code method and apparatus of the instant invention without departing from the scope or spirit of the invention, and it is intended that the present invention cover modifications and variations of the Schilling-Manela forward error correction and detection code method and apparatus provided they come within the scope of the appended claims and their equivalents.

Patent Citations

Cited Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US3475724 * | Oct 8, 1965 | Oct 28, 1969 | Bell Telephone Labor Inc | Error control system |

US4205324 * | Mar 7, 1978 | May 27, 1980 | International Business Machines Corporation | Methods and means for simultaneously correcting several channels in error in a parallel multi channel data system using continuously modifiable syndromes and selective generation of internal channel pointers |

US4435807 * | Jan 27, 1982 | Mar 6, 1984 | Scott Edward W | Orchard error correction system |

US4716567 * | Feb 10, 1986 | Dec 29, 1987 | Hitachi, Ltd. | Method of transmitting digital data in which error detection codes are dispersed using alternate delay times |

Non-Patent Citations

Reference | ||
---|---|---|

1 | David M. Mandelbaum, "Some Classes of Multiple-Burst Error-Correct Codes Using Threshold Decoding", IEEE Transactions on Information Theory, vol. IT-18, No. 2, Mar. 1972, pp. 285-292. | |

2 | * | David M. Mandelbaum, Some Classes of Multiple Burst Error Correct Codes Using Threshold Decoding , IEEE Transactions on Information Theory, vol. IT 18, No. 2, Mar. 1972, pp. 285 292. |

3 | John P. Robinson and Arthur J. Bernstein, "A Class of Binary Recurrent Codes with Limited Error Propagation", IEEE Transactions on Information Theory, vol. IT-13, No. 1, Jan., 1967, pp. 106-113. | |

4 | * | John P. Robinson and Arthur J. Bernstein, A Class of Binary Recurrent Codes with Limited Error Propagation , IEEE Transactions on Information Theory, vol. IT 13, No. 1, Jan., 1967, pp. 106 113. |

5 | Mario Blaum and Patrick G. Farrell, "A Class of Burst Error-Correcting Array Codes", IEEE Transactions on Information Theory, vol. IT-32, No. 6, Nov., 1986, pp. 836-839. | |

6 | * | Mario Blaum and Patrick G. Farrell, A Class of Burst Error Correcting Array Codes , IEEE Transactions on Information Theory, vol. IT 32, No. 6, Nov., 1986, pp. 836 839. |

Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US4847842 * | Nov 19, 1987 | Jul 11, 1989 | Scs Telecom, Inc. | SM codec method and apparatus |

US4849974 * | Nov 13, 1987 | Jul 18, 1989 | Scs Telecom, Inc. | PASM and TASM forward error correction and detection code method and apparatus |

US5271012 * | Feb 11, 1991 | Dec 14, 1993 | International Business Machines Corporation | Method and means for encoding and rebuilding data contents of up to two unavailable DASDs in an array of DASDs |

US5289497 * | May 23, 1991 | Feb 22, 1994 | Interdigital Technology Corporation | Broadcast synchronized communication system |

US5351246 * | Jan 3, 1994 | Sep 27, 1994 | International Business Machines Corporation | Method and means for coding and rebuilding that data contents of unavailable DASDs or rebuilding the contents of DASDs in error in the presence of reduced number of unavailable DASDs in a DASD array |

US5373511 * | May 4, 1992 | Dec 13, 1994 | Motorola, Inc. | Method for decoding a reed solomon encoded signal with inner code and apparatus for doing same |

US5442652 * | Jan 25, 1994 | Aug 15, 1995 | Interdigital Technology Corp. | Broadcast synchronized communication system |

US5546409 * | Jan 25, 1995 | Aug 13, 1996 | Canon Kabushiki Kaisha | Error correction encoding and decoding system |

US5644695 * | Jul 15, 1994 | Jul 1, 1997 | International Business Machines Corporation | Array combinatorial decoding with multiple error and erasure detection and location using cyclic equivalence testing |

US5708667 * | Jan 9, 1997 | Jan 13, 1998 | Fujitsu Limited | Method for detecting and correcting error by means of a high-dimension matrix and device using the same |

US5719883 * | Sep 21, 1994 | Feb 17, 1998 | Lucent Technologies Inc. | Adaptive ARQ/FEC technique for multitone transmission |

US5745509 * | Nov 17, 1995 | Apr 28, 1998 | U.S. Philips Corporation | Transmission system via communications protected by an error management code |

US6137844 * | Mar 30, 1998 | Oct 24, 2000 | Oki Telecom, Inc. | Digital filter for noise and error removal in transmitted analog signals |

US6247157 * | May 13, 1998 | Jun 12, 2001 | Intel Corporation | Method of encoding data signals for storage |

US6418549 | Jul 12, 1999 | Jul 9, 2002 | Merunetworks, Inc. | Data transmission using arithmetic coding based continuous error detection |

US6430230 * | Jun 30, 1999 | Aug 6, 2002 | Agilent Technologies, Inc. | Methods of encoding payload bits for transmission |

US6532556 * | Jan 27, 2000 | Mar 11, 2003 | Multi Level Memory Technology | Data management for multi-bit-per-cell memories |

US6581178 | Feb 10, 2000 | Jun 17, 2003 | Nec Corporation | Error correction coding/decoding method and apparatus |

US6976146 | May 21, 2002 | Dec 13, 2005 | Network Appliance, Inc. | System and method for emulating block appended checksums on storage devices by sector stealing |

US6993701 | Dec 28, 2001 | Jan 31, 2006 | Network Appliance, Inc. | Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array |

US7073115 | Dec 28, 2001 | Jul 4, 2006 | Network Appliance, Inc. | Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups |

US7080278 | Mar 8, 2002 | Jul 18, 2006 | Network Appliance, Inc. | Technique for correcting multiple storage device failures in a storage array |

US7111147 | Mar 21, 2003 | Sep 19, 2006 | Network Appliance, Inc. | Location-independent RAID group virtual block management |

US7143235 | Mar 21, 2003 | Nov 28, 2006 | Network Appliance, Inc. | Proposed configuration management behaviors in a raid subsystem |

US7185144 | Nov 24, 2003 | Feb 27, 2007 | Network Appliance, Inc. | Semi-static distribution technique |

US7200715 | Mar 21, 2002 | Apr 3, 2007 | Network Appliance, Inc. | Method for writing contiguous arrays of stripes in a RAID storage system using mapped block writes |

US7203892 | Dec 16, 2005 | Apr 10, 2007 | Network Appliance, Inc. | Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array |

US7254813 | Mar 21, 2002 | Aug 7, 2007 | Network Appliance, Inc. | Method and apparatus for resource allocation in a raid system |

US7263629 | Nov 24, 2003 | Aug 28, 2007 | Network Appliance, Inc. | Uniform and symmetric double failure correcting technique for protecting against two disk failures in a disk array |

US7275179 | Apr 24, 2003 | Sep 25, 2007 | Network Appliance, Inc. | System and method for reducing unrecoverable media errors in a disk subsystem |

US7283937 * | Dec 21, 2005 | Oct 16, 2007 | Palo Alto Research Center Incorporated | Method, apparatus, and program product for distinguishing valid data from noise data in a data set |

US7328305 | Nov 3, 2003 | Feb 5, 2008 | Network Appliance, Inc. | Dynamic parity distribution technique |

US7328364 | Mar 21, 2003 | Feb 5, 2008 | Network Appliance, Inc. | Technique for coherent suspension of I/O operations in a RAID subsystem |

US7346831 | Nov 13, 2001 | Mar 18, 2008 | Network Appliance, Inc. | Parity assignment technique for parity declustering in a parity array of a storage system |

US7356752 | Mar 14, 2001 | Apr 8, 2008 | Comtech Telecommunications Corp. | Enhanced turbo product codes |

US7366837 | Apr 29, 2005 | Apr 29, 2008 | Network Appliance, Inc. | Data placement technique for striping data containers across volumes of a storage system cluster |

US7398460 | Jan 31, 2005 | Jul 8, 2008 | Network Appliance, Inc. | Technique for efficiently organizing and distributing parity blocks among storage devices of a storage array |

US7409625 | Feb 23, 2007 | Aug 5, 2008 | Network Appliance, Inc. | Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array |

US7424637 | Mar 21, 2003 | Sep 9, 2008 | Networks Appliance, Inc. | Technique for managing addition of disks to a volume of a storage system |

US7430706 * | Feb 16, 2007 | Sep 30, 2008 | Lattice Semiconductor Corporation | Diagonal interleaved parity calculator |

US7437652 | Apr 12, 2006 | Oct 14, 2008 | Network Appliance, Inc. | Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups |

US7437727 | Mar 21, 2002 | Oct 14, 2008 | Network Appliance, Inc. | Method and apparatus for runtime resource deadlock avoidance in a raid system |

US7447938 | May 3, 2007 | Nov 4, 2008 | Network Appliance, Inc. | System and method for reducing unrecoverable media errors in a disk subsystem |

US7509525 | Jun 2, 2006 | Mar 24, 2009 | Network Appliance, Inc. | Technique for correcting multiple storage device failures in a storage array |

US7539991 | Mar 21, 2002 | May 26, 2009 | Netapp, Inc. | Method and apparatus for decomposing I/O tasks in a raid system |

US7613947 | Nov 30, 2006 | Nov 3, 2009 | Netapp, Inc. | System and method for storage takeover |

US7613984 | Dec 29, 2006 | Nov 3, 2009 | Netapp, Inc. | System and method for symmetric triple parity for failing storage devices |

US7627715 | Jan 31, 2005 | Dec 1, 2009 | Netapp, Inc. | Concentrated parity technique for handling double failures and enabling storage of more than one parity block per stripe on a storage device of a storage array |

US7640484 | Dec 15, 2005 | Dec 29, 2009 | Netapp, Inc. | Triple parity technique for enabling efficient recovery from triple failures in a storage array |

US7647451 | Apr 24, 2008 | Jan 12, 2010 | Netapp, Inc. | Data placement technique for striping data containers across volumes of a storage system cluster |

US7647526 | Dec 6, 2006 | Jan 12, 2010 | Netapp, Inc. | Reducing reconstruct input/output operations in storage systems |

US7660966 | Aug 2, 2006 | Feb 9, 2010 | Netapp, Inc. | Location-independent RAID group virtual block management |

US7661020 | May 22, 2008 | Feb 9, 2010 | Netapp, Inc. | System and method for reducing unrecoverable media errors |

US7664913 | Mar 21, 2003 | Feb 16, 2010 | Netapp, Inc. | Query-based spares management technique |

US7680834 | Jun 8, 2004 | Mar 16, 2010 | Bakbone Software, Inc. | Method and system for no downtime resychronization for real-time, continuous data protection |

US7685462 | Jan 8, 2008 | Mar 23, 2010 | Netapp, Inc. | Technique for coherent suspension of I/O operations in a RAID subsystem |

US7689602 | Jul 20, 2005 | Mar 30, 2010 | Bakbone Software, Inc. | Method of creating hierarchical indices for a distributed object system |

US7694173 | Aug 22, 2008 | Apr 6, 2010 | Netapp, Inc. | Technique for managing addition of disks to a volume of a storage system |

US7716566 | Jul 22, 2005 | May 11, 2010 | Seachange International, Inc. | Data error control |

US7788521 | Jul 20, 2005 | Aug 31, 2010 | Bakbone Software, Inc. | Method and system for virtual on-demand recovery for real-time, continuous data protection |

US7822921 | Oct 31, 2006 | Oct 26, 2010 | Netapp, Inc. | System and method for optimizing write operations in storage systems |

US7836331 | May 15, 2007 | Nov 16, 2010 | Netapp, Inc. | System and method for protecting the contents of memory during error conditions |

US7840837 | Apr 27, 2007 | Nov 23, 2010 | Netapp, Inc. | System and method for protecting memory during system initialization |

US7882425 | Mar 22, 2010 | Feb 1, 2011 | Seachange International, Inc. | Data error control |

US7904913 | Nov 1, 2005 | Mar 8, 2011 | Bakbone Software, Inc. | Management interface for a system that provides automated, real-time, continuous data protection |

US7921257 | Dec 27, 2007 | Apr 5, 2011 | Netapp, Inc. | Dynamic parity distribution technique |

US7926059 | May 13, 2009 | Apr 12, 2011 | Netapp, Inc. | Method and apparatus for decomposing I/O tasks in a RAID system |

US7930475 | Feb 22, 2007 | Apr 19, 2011 | Netapp, Inc. | Method for writing contiguous arrays of stripes in a RAID storage system using mapped block writes |

US7930587 | Aug 27, 2009 | Apr 19, 2011 | Netapp, Inc. | System and method for storage takeover |

US7941733 * | Feb 13, 2007 | May 10, 2011 | Kabushiki Kaisha Toshiba | Semiconductor memory device |

US7954034 * | Sep 30, 2005 | May 31, 2011 | Emc Corporation | Method of and system for protecting data during conversion from an ECC protection scheme to a parity protection scheme |

US7970996 | Nov 30, 2009 | Jun 28, 2011 | Netapp, Inc. | Concentrated parity technique for handling double failures and enabling storage of more than one parity block per stripe on a storage device of a storage array |

US7975102 | Aug 6, 2007 | Jul 5, 2011 | Netapp, Inc. | Technique to avoid cascaded hot spotting |

US7979404 | Sep 17, 2004 | Jul 12, 2011 | Quest Software, Inc. | Extracting data changes and storing data history to allow for instantaneous access to and reconstruction of any point-in-time data |

US7979441 | Jan 21, 2010 | Jul 12, 2011 | Quest Software, Inc. | Method of creating hierarchical indices for a distributed object system |

US7979633 | Apr 2, 2004 | Jul 12, 2011 | Netapp, Inc. | Method for writing contiguous arrays of stripes in a RAID storage system |

US7979779 | Sep 15, 2009 | Jul 12, 2011 | Netapp, Inc. | System and method for symmetric triple parity for failing storage devices |

US7984328 | Dec 18, 2009 | Jul 19, 2011 | Netapp, Inc. | System and method for reducing unrecoverable media errors |

US8010874 | Nov 6, 2009 | Aug 30, 2011 | Netapp, Inc. | Triple parity technique for enabling efficient recovery from triple failures in a storage array |

US8015472 | Aug 21, 2008 | Sep 6, 2011 | Netapp, Inc. | Triple parity technique for enabling efficient recovery from triple failures in a storage array |

US8032704 | Jul 31, 2009 | Oct 4, 2011 | Netapp, Inc. | Data placement technique for striping data containers across volumes of a storage system cluster |

US8041924 | Dec 17, 2009 | Oct 18, 2011 | Netapp, Inc. | Location-independent raid group virtual block management |

US8060889 | Jun 22, 2009 | Nov 15, 2011 | Quest Software, Inc. | Method and system for real-time event journaling to provide enterprise data services |

US8108429 | May 6, 2005 | Jan 31, 2012 | Quest Software, Inc. | System for moving real-time data events across a plurality of devices in a network for simultaneous data protection, replication, and access services |

US8131723 | Mar 31, 2008 | Mar 6, 2012 | Quest Software, Inc. | Recovering a file system to any point-in-time in the past with guaranteed structure, content consistency and integrity |

US8151140 | Jul 28, 2010 | Apr 3, 2012 | Quest Software, Inc. | Method and system for virtual on-demand recovery for real-time, continuous data protection |

US8156282 | Sep 21, 2010 | Apr 10, 2012 | Netapp, Inc. | System and method for optimizing write operations in storage systems |

US8181090 | Aug 31, 2011 | May 15, 2012 | Netapp, Inc. | Triple parity technique for enabling efficient recovery from triple failures in a storage array |

US8195628 | Oct 11, 2010 | Jun 5, 2012 | Quest Software, Inc. | Method and system for data reduction |

US8200706 | Jul 11, 2011 | Jun 12, 2012 | Quest Software, Inc. | Method of creating hierarchical indices for a distributed object system |

US8201055 | Apr 5, 2011 | Jun 12, 2012 | Kabushiki Kaisha Toshiba | Semiconductor memory device |

US8209587 | Apr 12, 2007 | Jun 26, 2012 | Netapp, Inc. | System and method for eliminating zeroing of disk drives in RAID arrays |

US8230316 | Jan 22, 2009 | Jul 24, 2012 | Nevion Usa, Inc. | Forward error correction for burst and random packet loss for real-time multi-media communication |

US8352523 | Sep 23, 2011 | Jan 8, 2013 | Quest Software, Inc. | Recovering a file system to any point-in-time in the past with guaranteed structure, content consistency and integrity |

US8364648 | Apr 9, 2008 | Jan 29, 2013 | Quest Software, Inc. | Recovering a database to any point-in-time in the past with guaranteed data consistency |

US8365017 | Jun 27, 2012 | Jan 29, 2013 | Quest Software, Inc. | Method and system for virtual on-demand recovery |

US8375248 | Mar 30, 2012 | Feb 12, 2013 | Quest Software, Inc. | Method and system for virtual on-demand recovery |

US8402346 | Sep 25, 2009 | Mar 19, 2013 | Netapp, Inc. | N-way parity technique for enabling recovery from up to N storage device failures |

US8429198 | Jun 6, 2012 | Apr 23, 2013 | Quest Software, Inc. | Method of creating hierarchical indices for a distributed object system |

US8468304 | Jun 7, 2011 | Jun 18, 2013 | Netapp, Inc. | Concentrated parity technique for handling double failures and enabling storage of more than one parity block per stripe on a storage device of a storage array |

US8473833 | May 22, 2012 | Jun 25, 2013 | Nevion Usa, Inc. | Forward error correction method |

US8495417 | Jan 9, 2009 | Jul 23, 2013 | Netapp, Inc. | System and method for redundancy-protected aggregates |

US8516342 | May 15, 2012 | Aug 20, 2013 | Netapp, Inc. | Triple parity technique for enabling efficient recovery from triple failures in a storage array |

US8544023 | Oct 11, 2010 | Sep 24, 2013 | Dell Software Inc. | Management interface for a system that provides automated, real-time, continuous data protection |

US8560503 | Jan 26, 2006 | Oct 15, 2013 | Netapp, Inc. | Content addressable storage system |

US8560773 | May 26, 2011 | Oct 15, 2013 | Netapp, Inc. | Technique to avoid cascaded hot spotting |

US8621465 | Mar 15, 2011 | Dec 31, 2013 | Netapp, Inc. | Method and apparatus for decomposing I/O tasks in a RAID system |

US8639974 | Dec 20, 2012 | Jan 28, 2014 | Dell Software Inc. | Method and system for virtual on-demand recovery |

US8650167 | Jun 1, 2012 | Feb 11, 2014 | Dell Software Inc. | Method and system for data reduction |

US8712970 | Jan 28, 2013 | Apr 29, 2014 | Dell Software Inc. | Recovering a database to any point-in-time in the past with guaranteed data consistency |

US8880814 | Oct 15, 2013 | Nov 4, 2014 | Netapp, Inc. | Technique to avoid cascaded hot spotting |

US8898536 | Apr 27, 2007 | Nov 25, 2014 | Netapp, Inc. | Multi-core engine for detecting bit errors |

US8972347 | Dec 14, 2012 | Mar 3, 2015 | Dell Software Inc. | Recovering a file system to any point-in-time in the past with guaranteed structure, content consistency and integrity |

US9158579 | Nov 10, 2008 | Oct 13, 2015 | Netapp, Inc. | System having operation queues corresponding to operation execution time |

US9348693 * | May 23, 2013 | May 24, 2016 | Phison Electronics Corp. | Data accessing method for flash memory module |

US9411514 | Dec 20, 2013 | Aug 9, 2016 | Netapp, Inc. | Method and apparatus for decomposing I/O tasks in a RAID system |

US9418110 * | Jun 30, 2008 | Aug 16, 2016 | Emc Corporation | Intelligent, scalable, low-overhead mechanism for data retrieval in a distributed network environment |

US9430278 | Aug 28, 2015 | Aug 30, 2016 | Netapp, Inc. | System having operation queues corresponding to operation execution time |

US20010050622 * | Mar 14, 2001 | Dec 13, 2001 | Hewitt Eric John | Enhanced turbo product codes |

US20030033570 * | May 9, 2002 | Feb 13, 2003 | Khannanov Roman R. | Method and apparatus for encoding and decoding low density parity check codes and low density turbo product codes |

US20030126522 * | Dec 28, 2001 | Jul 3, 2003 | English Robert M. | Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups |

US20030126523 * | Dec 28, 2001 | Jul 3, 2003 | Corbett Peter F. | |

US20030182348 * | Mar 21, 2002 | Sep 25, 2003 | James Leong | Method and apparatus for runtime resource deadlock avoidance in a raid system |

US20030182502 * | Mar 21, 2002 | Sep 25, 2003 | Network Appliance, Inc. | Method for writing contiguous arrays of stripes in a RAID storage system |

US20030182503 * | Mar 21, 2002 | Sep 25, 2003 | James Leong | Method and apparatus for resource allocation in a raid system |

US20040205387 * | Apr 2, 2004 | Oct 14, 2004 | Kleiman Steven R. | Method for writing contiguous arrays of stripes in a RAID storage system |

US20050097270 * | Nov 3, 2003 | May 5, 2005 | Kleiman Steven R. | Dynamic parity distribution technique |

US20050114593 * | Mar 21, 2003 | May 26, 2005 | Cassell Loellyn J. | Query-based spares management technique |

US20050114594 * | Nov 24, 2003 | May 26, 2005 | Corbett Peter F. | Semi-static distribution technique |

US20050114727 * | Nov 24, 2003 | May 26, 2005 | Corbett Peter F. | Uniform and symmetric double failure correcting technique for protecting against two disk failures in a disk array |

US20050262097 * | May 6, 2005 | Nov 24, 2005 | Sim-Tang Siew Y | System for moving real-time data events across a plurality of devices in a network for simultaneous data protection, replication, and access services |

US20060075281 * | Sep 27, 2004 | Apr 6, 2006 | Kimmel Jeffrey S | Use of application-level context information to detect corrupted data in a storage system |

US20060101384 * | Nov 1, 2005 | May 11, 2006 | Sim-Tang Siew Y | Management interface for a system that provides automated, real-time, continuous data protection |

US20060156178 * | Jul 22, 2005 | Jul 13, 2006 | Xiaobing Lee | Data error control |

US20060184731 * | Apr 29, 2005 | Aug 17, 2006 | Corbett Peter F | Data placement technique for striping data containers across volumes of a storage system cluster |

US20060242542 * | Apr 12, 2006 | Oct 26, 2006 | English Robert M | |

US20060271734 * | Aug 2, 2006 | Nov 30, 2006 | Strange Stephen H | Location-independent RAID group virtual block management |

US20070064771 * | Nov 22, 2006 | Mar 22, 2007 | Interdigital Technology Corporation | Receiving and selectively transmitting frequency hopped data signals using a plurality of antennas |

US20070089045 * | Dec 15, 2005 | Apr 19, 2007 | Corbett Peter F | Triple parity technique for enabling efficient recovery from triple failures in a storage array |

US20070143081 * | Dec 21, 2005 | Jun 21, 2007 | Palo Alto Research Center Incorporated | Method, apparatus, and program product for distinguishing valid data from noise data in a data set |

US20070180348 * | Feb 23, 2007 | Aug 2, 2007 | Corbett Peter F | |

US20070198626 * | Feb 13, 2007 | Aug 23, 2007 | Kabushiki Kaisha Toshiba | Semiconductor memory device |

US20070266291 * | Mar 27, 2007 | Nov 15, 2007 | Kabushiki Kaisha Toshiba | Semiconductor memory device |

US20080016435 * | Dec 29, 2006 | Jan 17, 2008 | Atul Goel | System and method for symmetric triple parity |

US20080270776 * | Apr 27, 2007 | Oct 30, 2008 | George Totolos | System and method for protecting memory during system initialization |

US20090222829 * | May 13, 2009 | Sep 3, 2009 | James Leong | Method and apparatus for decomposing i/o tasks in a raid system |

US20090249164 * | Aug 2, 2007 | Oct 1, 2009 | Jorg Hammer | Method for serial asynchronous transmission of data in an arragement for the monitoring, controlling, and regulating an operational control facility of building |

US20090327818 * | Apr 27, 2007 | Dec 31, 2009 | Network Appliance, Inc. | Multi-core engine for detecting bit errors |

US20100050015 * | Nov 6, 2009 | Feb 25, 2010 | Corbett Peter F | Triple parity technique for enabling efficient recovery from triple failures in a storage array |

US20100095060 * | Dec 17, 2009 | Apr 15, 2010 | Strange Stephen H | Location-independent raid group virtual block management |

US20100146004 * | Jan 21, 2010 | Jun 10, 2010 | Siew Yong Sim-Tang | Method Of Creating Hierarchical Indices For A Distributed Object System |

US20100180153 * | Jan 9, 2009 | Jul 15, 2010 | Netapp, Inc. | System and method for redundancy-protected aggregates |

US20100192049 * | Mar 22, 2010 | Jul 29, 2010 | Seachange International, Inc. | Data Error Control |

US20100198788 * | Jan 29, 2010 | Aug 5, 2010 | Siew Yong Sim-Tang | Method and system for no downtime resynchronization for real-time, continuous data protection |

US20110010599 * | Sep 25, 2009 | Jan 13, 2011 | Netapp, Inc. | N-way parity technique for enabling recovery from up to n storage device failures |

US20110185261 * | Apr 5, 2011 | Jul 28, 2011 | Kabushiki Kaisha Toshiba | Semiconductor memory device |

US20110191780 * | Mar 15, 2011 | Aug 4, 2011 | Netapp, Inc. | Method and apparatus for decomposing i/o tasks in a raid system |

US20130254629 * | May 23, 2013 | Sep 26, 2013 | Phison Electronics Corp. | Data accessing method for flash memory module |

EP0523969A1 * | Jul 15, 1992 | Jan 20, 1993 | Canon Kabushiki Kaisha | Error correction encoding and decoding system |

EP0715430A1 | Nov 21, 1995 | Jun 5, 1996 | Trt Telecommunications Radioelectriques Et Telephoniques | Transmission system with error correcting coding using parity codes |

EP1030456A2 * | Feb 14, 2000 | Aug 23, 2000 | Nec Corporation | Error correction coding/decoding method and apparatus |

EP1030456A3 * | Feb 14, 2000 | Jan 9, 2002 | Nec Corporation | Error correction coding/decoding method and apparatus |

EP1887446A1 * | Aug 2, 2006 | Feb 13, 2008 | Siemens Aktiengesellschaft | Method for serial asynchronous transfer of data in an arrangement for the surveillance, control and regulation of a technical installation of a building automation system |

WO2001069797A2 * | Mar 14, 2001 | Sep 20, 2001 | Advanced Hardware Architectures, Inc. | Enhanced turbo product codes |

WO2001069797A3 * | Mar 14, 2001 | Feb 28, 2002 | Advanced Hardware Architecture | Enhanced turbo product codes |

WO2003088501A2 * | Apr 17, 2003 | Oct 23, 2003 | Koninklijke Philips Electronics N.V. | Signal, storage medium, method and device for encoding, method and device for decoding |

WO2003088501A3 * | Apr 17, 2003 | Dec 24, 2003 | Willem M J M Coene | Signal, storage medium, method and device for encoding, method and device for decoding |

WO2008015262A1 * | Aug 2, 2007 | Feb 7, 2008 | Siemens Schweiz Ag | Method for the serial asynchronous transmission of data in an arrangement for the monitoring, controlling, and regulating of an operational control facility of a building |

Classifications

U.S. Classification | 714/755, 714/766 |

International Classification | H03M13/29, H03M13/05 |

Cooperative Classification | H03M13/2921, H03M13/29, H03M13/2918, H03M13/05 |

European Classification | H03M13/29B7, H03M13/29B5, H03M13/05, H03M13/29 |

Legal Events

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Sep 9, 1988 | AS | Assignment | Owner name: SCS TELECOM, INC., 107 HAVEN AVENUE, PORT WASHINGT Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:SCHILLING, DONALD L.;MANELA, DAVID;REEL/FRAME:004941/0854 Effective date: 19870918 Owner name: SCS TELECOM, INC., A CORP. OF NY,NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCHILLING, DONALD L.;MANELA, DAVID;REEL/FRAME:004941/0854 Effective date: 19870918 |

May 19, 1992 | FPAY | Fee payment | Year of fee payment: 4 |

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