|Publication number||US4811185 A|
|Application number||US 07/108,462|
|Publication date||Mar 7, 1989|
|Filing date||Oct 15, 1987|
|Priority date||Oct 15, 1987|
|Also published as||EP0336952A1, EP0336952A4, WO1989003610A1|
|Publication number||07108462, 108462, US 4811185 A, US 4811185A, US-A-4811185, US4811185 A, US4811185A|
|Inventors||Alex Cook, Sampat S. Shekhawat|
|Original Assignee||Sundstrand Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Non-Patent Citations (3), Referenced by (27), Classifications (7), Legal Events (10)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a DC to DC power converter an, more particularly, to a converter which provides an output voltage at a level midway between two DC voltages.
DC to DC power converters are used to convert a DC input voltage provided by a DC power source at a first level to a DC output voltage at a second level.
One example is a neutral forming converter for providing a voltage at a neutral level for an AC load.
Turnbull U.S. Pat. No. 3,775,663 discloses an inverter with an electronically controlled neutral terminal for direct connection to an AC load. Input terminals receive a DC input voltage. A half-bridge inverter is coupled between the input terminals and includes series-connected solid-state switches. A pair of capacitors is coupled between the input terminals and an inductor is coupled between the junction of the solid state switches and the junction of the capacitors. The neutral terminal is coupled to the junction of the inductor with the capacitors. The switches are alternately rendered conductive by closed-loop circuitry to maintain the voltage at the neutral terminal at a neutral voltage.
According to Turnbull, the inductor must be relatively large to minimize ripple current. Due to the large inductor, the switch conduction time must be modified by the closed-loop circuitry to allow the neutral to present a sufficiently low impedance to the load and to load changes.
In accordance with the present invention, a DC to DC power converter is provided which can be used as a neutral forming converter. The converter requires neither a large filtering inductor nor closed-loop gating circuitry. Thus response time is shortened and complex circuitry is eliminated.
According to a first embodiment, the converter has first and second input terminals and an output terminal and provides an output voltage at the output terminal which is at a potential halfway between first and second DC potentials applied by a DC power source across the first and second input terminals.
The converter comprises first and second switches connected at a switch junction in series between the first and second input terminals, first and second series-connected unidirectional current-conducting devices, e.g. diodes, coupled at a further junction across the first and second input terminals, an energy storage element such as a transformer comprising two windings magnetically linked having first and second terminals or ends and a third terminal or center-tap, the first and second ends being coupled between the switch junction and the further junction and the center-tap being coupled to the output terminal, and means for alternately operating the first and the second switches at substantially equal duty cycles or factors such that a voltage substantially midway between the first and second DC potentials is produced at the output terminal.
The converter further includes a filter network connected to the center-tap of the transducer. The filter network comprises a first capacitor coupled between the first input terminal and the output terminal and a second capacitor coupled between the second input terminal and the output terminal.
According to a second embodiment, the first and second diodes are replaced by third and fourth switches, resulting in a further reduction in ripple current.
Other features and advantages of the invention will be apparent from the following description taken in connection with the drawings, wherein:
FIG. 1 is a block diagram of a first embodiment of a converter according to the present invention coupled to a DC power supply;
FIG. 2 is a schematic diagram of the converter shown in FIG. 1;
FIG. 3 is a waveform diagram illustrating illustration of the switches in the converter of FIG. 2; and
FIG. 4 is a schematic diagram of a converter according to a second embodiment of the present invention.
A DC to DC converter 10 having first and second converter input terminals 12, 14 connected to a DC-power supply 15 and a converter output terminal 16 coupled to an AC load 20, is illustrated in FIG. 1. The DC power supply 15 provides DC power comprising a first supply voltage V1 at a first power supply output terminal 24 and a second supply voltage V2 at a second power supply output terminal 26. The DC power supply further provides the DC power to an inverter 27 which converts the DC power to three-phase AC power for use by the AC load 20.
In accordance with the present invention, a converter output voltage V0 is produced by the converter 10 at the converter output terminal 16, wherein the average converter output voltage V0 is halfway between the first and second supply voltages V1 and V2.
In the preferred embodiment, voltages V1 and V2 are of equal magnitude and opposite polarity. Thus, the converter 10 develops an output voltage Vo of zero volts. However, the converter 10 can be used to provide a DC voltage at a level halfway between any other two input voltage levels without departing from the scope of the present invention.
A schematic diagram of the first embodiment of the converter 10 is illustrated in FIG. 2.
The converter 10 includes a first bus 30 coupled to the first converter input terminal 12 and a second bus 32 coupled to the second converter input terminal 14.
First and second switches or transistors 34, 36, preferably MOSFET's, are connected in series at a transistor junction 37 between the first and second busses 30, 32. In the event bipolar transistors are used for the first and second switches, an antiparallel diode is coupled across each of the bipolar transistors to prevent damage due to reverse current.
First and second unidirectional current-conducting devices, such as diodes 38, 40 are also connected in series at a further or diode junction 41 across the first and second busses 30, 32 and are poled such that they are in reverse-bias relationship relative to the DC power provided by the DC power supply 15.
An energy storage element in the form of a transformer 42 comprises first and second magnetically-linked windings 43, 44 and has first and second terminals or ends 45, 46 and a third terminal or center-tap 48. The transformer 42 has a 1:1 turns ratio and can be, for example, an auto-transformer. The first and second terminals 45, 46 are coupled between the transistor junction 37 and the diode junction 41. The third terminal or center-tap 48 is coupled to the converter output terminal 16. A first capacitor 52 is connected between the third output terminal 20 and the first bus 30, and a second capacitor 54 is connected between the third output terminal 20 and the second bus 32. The first and second capacitors 52, 54 operate as an output filter to reduce output ripple.
Transistor gating circuitry 56 operates the first and second switches 34, 36.
A waveform diagram illustrating the output of the transistor gating circuitry 56 is illustrated in FIG. 3. During operation, the transistor gating circuitry 56 alternately turns on the first and second switches 34, 36, via transistor control leads 57, 58, respectively, for equal time intervals. It is preferred that each of the switches 34, 36 operate at just less than 50% duty factor, such that a short dwell interval is interposed between turn off of one of the switches and turn on of the other. The dwell interval is of a duration sufficient to prevent shoot-through.
Referring again to FIG. 2, during operation, when the first switch 34 is on and the second switch 36 is off, the first voltage V1 appears at the transistor junction 37, neglecting the voltage drop across the switch 34. Owing to the 1:1 turns ratio of the windings 43, 44, the voltage drops across the windings 43, 44 are equal. Hence, the voltage Vd at the diode 41 is equal to V1 -2(V1 -Vc), where Vc is the voltage at the center-tap 48, provided that the voltage Vd is greater than one diode drop below V2. Alternatively, when the first switch 34 is off and the second switch 36 is on, the second voltage V2 transistor junction 37, neglecting the drop across the second switch 36. The voltage Vd at the diode junction 41, in this case, is equal to V2 +2(Vc -V2), provided that the voltage Vd is less than one diode drop above V1. The voltage Vd cannot be less than one diode drop below the voltage V2 nor can it exceed one diode drop above V1 due to the presence of the diodes 38, 40.
By alternately switching the first and second switches 34, 36 rapidly, the center-tap voltage Vc will settle at an average level halfway between the first and second supply voltages V1, V2, thus providing at the converter output terminal 16 a filtered output voltage Vo midway between the first and second supply voltages V1, V2.
For high power applications, the first and second switches 34, 36 are switched at a frequency on the order of 5-10 kHz. For lower power applications, the switching frequency is higher.
The converter 10 will passively maintain the output voltage halfway between the first and second supply voltages V1, V2, even when the AC load 20 is unbalanced because any DC potential across the transformer resulting from the imbalance of the AC load 20 will cause a current to flow out through one of the diodes 38, 40, thus discharging the DC potential. This occurs every time the appropriate switch is on, and hence the filter capacitors will charge and discharge once every cycle. The peak-to-peak ripple voltage is given by ##EQU1## I is the neutral current; T is the off-time of either switch; and
C1 and C2 are the capacitances of the output capacitors 52, 54.
The ripple can be almost entirely eliminated by using an embodiment comprising a full bridge circuit, as illustrated in FIG. 4. According to this embodiment, the diodes 38 and 40 are replaced by third and fourth switches or transistors 70, 72.
The third and fourth switches 70, 72 are preferably MOSFET's. In the event bipolar transistors are used for the third and fourth switches, an antiparallel diodes is coupled across each of the bipolar transistors to prevent damage due to reverse current. The switch 70 is operated with the switch 36 while the switch 72 is operated with the switch 34. Ripple is reduced in this embodiment, since the only capacitor charge time is now the off-period during which neither pair of the switches is on. A further benefit of this embodiment is that the switches share the neutral current and each switch only conducts approximately half of the neutral current.
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|US3775663 *||Aug 24, 1972||Nov 27, 1973||Gen Electric||Inverter with electronically controlled neutral terminal|
|US4020361 *||Oct 4, 1974||Apr 26, 1977||Delta Electronic Control Corporation||Switching mode power controller of large dynamic range|
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|3||Pp. 9-191 and 9-192 of the "Unitrode Linear IC Data Book 1987-1988" by Unitrodue Corporation, copyright 1987.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5092302 *||Dec 26, 1990||Mar 3, 1992||Ford Motor Company||Fuel pump speed control by dc-dc converter|
|US5128852 *||Apr 23, 1991||Jul 7, 1992||Siemens Nixdorf Informationssysteme Ag||Current-fed push-pull converter|
|US5396165 *||Feb 2, 1993||Mar 7, 1995||Teledyne Industries, Inc.||Efficient power transfer system|
|US5583421 *||Aug 10, 1994||Dec 10, 1996||Hewlett-Packard Company||Sepic converter with transformerless line isolation|
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|US20130127358 *||Nov 17, 2011||May 23, 2013||Gang Yao||Led power source with over-voltage protection|
|USRE46256||May 24, 2013||Dec 27, 2016||Advanced Micro Devices, Inc.||Asymmetric topology to boost low load efficiency in multi-phase switch-mode power conversion|
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|WO2001084063A3 *||May 3, 2001||Mar 7, 2002||Horton Inc||A cooling system with brushless dc ring motor fan|
|U.S. Classification||363/17, 363/24, 363/98, 363/62|
|Dec 7, 1987||AS||Assignment|
Owner name: SUNDSTRAND CORPORATION, A DE CORP.
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:COOK, ALEX;SHEKHAWAT, SAMPAT S.;REEL/FRAME:004797/0201
Effective date: 19871005
Owner name: SUNDSTRAND CORPORATION, A DE CORP.,ILLINOIS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:COOK, ALEX;SHEKHAWAT, SAMPAT S.;REEL/FRAME:004797/0201
Effective date: 19871005
|Oct 6, 1992||REMI||Maintenance fee reminder mailed|
|Oct 14, 1992||REMI||Maintenance fee reminder mailed|
|Nov 23, 1992||SULP||Surcharge for late payment|
|Nov 23, 1992||FPAY||Fee payment|
Year of fee payment: 4
|Sep 18, 1996||SULP||Surcharge for late payment|
|Sep 18, 1996||FPAY||Fee payment|
Year of fee payment: 8
|Sep 26, 2000||REMI||Maintenance fee reminder mailed|
|Mar 4, 2001||LAPS||Lapse for failure to pay maintenance fees|
|May 8, 2001||FP||Expired due to failure to pay maintenance fee|
Effective date: 20010307