|Publication number||US4818711 A|
|Application number||US 07/090,334|
|Publication date||Apr 4, 1989|
|Filing date||Aug 28, 1987|
|Priority date||Aug 28, 1987|
|Publication number||07090334, 090334, US 4818711 A, US 4818711A, US-A-4818711, US4818711 A, US4818711A|
|Inventors||Himanshu Choksi, Daniel Tang|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Referenced by (12), Classifications (18), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to the field of growing high quality oxides on the surface of ion implanted polysilicon.
2. Prior Art
In the field of growing oxide layers on the surface of polysilicon for use as an interpoly dielectric, it is desired to grow an oxide layer with improved electrical and physical characteristics. There are three generally followed methods of growing oxides on an ion implanted polysilicon layer having a variety of disadvantages.
In a first method, the polysilicon is deposited by a chemical vapor deposition (CVD) process at a temperature of above approximately 600° and diffusion doped using a gaseous (generally POC13) source. The oxide layer is then thermally grown on the film surface. This method suffers from several serious problems. First, the upper surface of the polysilicon film is rough, leading to poor electrical characteristics in the oxide layer grown on the polysilicon film due to localized field enhancement. Second, the heavy doping level leads to dopant segregtion at the grain boundaries. This leads to non-uniform oxide thickness and results in poor electrical characteristics of the oxide. Third, the quality of the oxide grown on this polysilicon film is poor due to the incorporation of phosphorous from the grain boundaries and results in a low breakdown voltage of the oxide. Fourth, the growth of the polysilicon grains through the subsequent thermal cycles causes residual stress in the oxide which reduces the breakdown voltage further.
A second method of developing the oxide layer is to deposit silicon by a CVD process at a temperature below approximately 580° C. The silicon is then diffusion doped using a gaseous (generally POC13) source. The oxide is then thermally grown on the film surface. Although low temperature deposited silicon film is initially smooth, it recrystallizes during the doping cycle resulting in very large grains. The thickness of the oxide layer grown on such a film varies from grain to grain because different crystal faces are exposed to the oxidation ambient by different grains. It is well known that different crystallographic faces oxidize at different rates. The nonuniform oxide thickness results in non-uniform electrical characteristics. In addition, the "steps" caused as a result at grain boundaries can act as charge injection sites.
A third method involves deposition of a silicon film by a CVD process above approximately 600° C. A dopant is then introduced into the film by means of an ion implantation process. The thermal oxide layer is then grown on the surface of this polysilicon film. This method also results in a rough upper surface of the polysilicon film. The oxide grown on it, therefore, has a low breakdown voltage due to localized field enhancement.
A method for growing a high quality oxide layer on the surface of an ion implanted polysilicon for use as an interpoly dielectric is described. The method involves deposition of a silicon film on an oxide layer on a silicon wafer using a chemical vapor deposition (CVD) process. The silicon film is then implanted using phosphorous ions. The wafers are sent to a diffusion tube to activate the dopant. This operation is carried out in an ambient of dry oxygen. The dopant is activated and the film is now polysilicon as a result of the recrystallization. The wafers are then implanted using argon ions. The implantation is carried out through the oxide layer. The surface layers of the polysilicon film are rendered amorphous as a result of this implant. This oxide layer is then removed and the wafer is again sent through a diffusion tube in an ambient of pure dry oxygen resulting in growing another oxide layer.
The polysilicon layer resulting from this method has a dual structure. The upper surface of the film is smooth with small equiaxed grains. The physical and electrical properties of the oxide grown on this film are, therefore, very uniform. The overall doping level is relatively low resulting in little or no dopant segregation. The lower layer of the film has very large grains and the dopant activation is high and resistivity is low.
Overall, the polysilicon film uniformity is excellent which results in reproducible electrical and physical properties.
FIG. 1 is a cross sectional elevation view of a processing step of the preferred embodiment showing formation of an insulation layer on a semiconductor substrate.
FIG. 2 is a cross sectional elevation view of a processing step of the preferred embodiment showing formation of a silicon film on the insulation layer.
FIG. 3 is a cross sectional elevation view of a processing step of the preferred embodiment showing the silicon film being bombarded with phosphorous ions.
FIG. 4 is a cross sectional elevation view of a processing step of the preferred embodiment showing the film now being polysilicon and showing a second insulation layer grown on the film.
FIG. 5 is a cross sectional elevation view of a processing step of the preferred embodiment showing the wafer being bombarded with argon ions.
FIG. 6 is a cross sectional elevation view of a processing step of the preferred embodiment showing the second insulation layer being removed.
FIG. 7 is a cross sectional elevation view of a processing step of the preferred embodiment showing formation of a new insulation layer on the polysilicon film.
A process for formation of a high quality thermally grown oxide on the surface of an ion implanted polysilicon film for use as an interpoly dielectric is described. In the following description, numerous specific details are set forth such as processing parameters, types of materials, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known structures and techniques have not been shown in detail in order not to unnecessarily obscure the present invention.
The present invention discloses a method of forming a polysilicon film which has a dual structure, the upper surface of which is smooth with small grains. This surface allows an oxide grown on the film to have excellent physical and electrical properties. The lower layer of the film has very large grains as a consequent of low temperature deposition. The dopant activation is high and resistivity is low, thus this part of the film carries the major part of any current flowing through the film. In addition, the resistivity of the polysilicon film is very uniform across the wafer and the magnitude of the resistivity is a considerably lower of that obtained by a similar implant dose into silicon deposited in the polycrystalline form. This is due to the high level of dopant activation achieved using this approach. The low resistivity results in a significant advantage in creating high density circuits.
Referring now to FIG. 1, a wafer as may be utilized by the present invention is disclosed. In the preferred embodiment, an oxide layer 11 is deposited on a single crystal silicon wafer 10 using any of a number of well known processing methods. The prior processing history of the wafer is immaterial to the present invention.
An amorphous silicon film 12 is then deposited on the oxide layer as shown in FIG. 2. The deposition of the silicon film is carried out in any commercially available chemical vapor deposition (CVD) reactor by employing a deposition temperature of approximately 560°. The thickness of the silicon film 12 depends on the application, in the preferred embodiment the silicon film is approximately 3000 angstroms thick.
The amorphous silicon film 12 is then implanted using phosphorous ions as illustrated in FIG. 3. The implantation may be done with any commercially available ion implantation machine. In the preferred embodiment the phosphorous ions are accelerated to approximately 75 keV and the flux of the ions used in the preferred embodiment is approximately 6E14/cm2.
The wafers are then sent into a diffusion tube to activate the dopant. This operation is carried out in an ambient of dry oxygen at a temperature of approximately 920° C. As illustrated in FIG. 4, an oxide film 13 is grown as a result and in the preferred embodiment is approximately 280 angstroms thick. The dopant is activated and the film 14 is now polysilicon as a result of recrystallization.
As shown in FIG. 5, the wafers are then implanted using singly charged argon ions at an energy of approximately 40 keV in a flux of approximately 6E14/cm2. The implantation of the argon ions is carried out through the oxide layer 13 and the surface layers of the polysilicon film 14 are rendered amorphous as a result of this implant.
The oxide layer 13 is then removed as illustrated in FIG. 6. In the preferred embodiment the oxide layer 13 is removed by dipping the wafers in a solution of 5:1 water:HF. It will be obvious to one of ordinary skill in the art that the exact ratio of water to HF may be varied and that other methods of removing the oxide layer 13 may be utilized without departing from the spirit of the invention.
The wafers are then sent through a diffusion tube and a new oxide layer is grown on the polysilicon film. In the preferred embodiment, the temperature in the diffusion tube is maintained at approximately 1000° C. and the ambient during the oxidation is pure dry oxygen.
In the preferred embodiment of the present invention, argon is chosen as the implant species because it is an inert element and, therefore, does not affect the resistivity of the film. Since argon's atomic radius is significantly different than that of silicon, incorporating argon atoms into the silicon lattice results in a large amount of strain which retards the growth of silicon grains during subsequent high temperature processing. The argon ions are implanted through the oxide layer because implanting through the oxide results in the incorporation of small amounts of oxygen atoms in the silicon lattice. The amorphous oxide film prevents any channeling effect of Argon atoms during implant and allows the implant process to produce an amorphous layer with uniform thickness. The oxygen also stabilizes the small grains up to temperatures above 1000° C. This helps to maintain the small grain size through subsequent processing.
The second oxide layer grown on the polysilicon film has extremely uniform and excellent electrical properties for several reasons. First, the amorphous polysilicon film presents random orientations to the oxidizing ambient and the oxide grown on this surface is, therefore, extremely uniform. The wave length and amplitude of any undulations in the oxide thickness is very small. Second, the method precludes the segregation of dopant (phosphorous) at grain boundaries and therefore the oxide grown on the polysilicon is of high quality. The oxide sustains higher breakdown voltage and the number and density of oxide defects is minimized.
An alternative to the preferred embodiment of the present invention consists of implantation of the argon ions without first growing the oxide layer on the polysilicon film. The polysilicon film is then implanted with oxygen atoms and an oxide layer is grown on the polysilicon film. This method still results in the incorporation of small amounts of oxygen atoms in the silicon lattice which helps to maintain the small grain size of the polysilicon film through subsequent processing.
Thus, a method for growing a high quality oxide layer on a polysilicon film for use as an interpoly dielectric is disclosed.
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|U.S. Classification||438/491, 438/966, 438/585, 438/532, 438/528, 257/E21.316, 257/E21.301, 438/659|
|International Classification||H01L21/316, H01L21/768, H01L21/3215, H01L21/265, H01L21/321|
|Cooperative Classification||Y10S438/966, H01L21/32105, H01L21/32155|
|European Classification||H01L21/3215B, H01L21/321C|
|Aug 28, 1987||AS||Assignment|
Owner name: INTEL CORPORATION, 3065 BOWERS AVENUE, SANTA CLARA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:CHOKSI, HIMANSHU;TANG, DANIEL;REEL/FRAME:004776/0762
Effective date: 19870731
Owner name: INTEL CORPORATION, A CORP. OF CA.,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOKSI, HIMANSHU;TANG, DANIEL;REEL/FRAME:004776/0762
Effective date: 19870731
|May 28, 1991||CC||Certificate of correction|
|Sep 30, 1992||FPAY||Fee payment|
Year of fee payment: 4
|Sep 30, 1996||FPAY||Fee payment|
Year of fee payment: 8
|Oct 3, 2000||FPAY||Fee payment|
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|Oct 24, 2000||REMI||Maintenance fee reminder mailed|