|Publication number||US4834660 A|
|Application number||US 07/057,558|
|Publication date||May 30, 1989|
|Filing date||Jun 3, 1987|
|Priority date||Jun 3, 1987|
|Publication number||057558, 07057558, US 4834660 A, US 4834660A, US-A-4834660, US4834660 A, US4834660A|
|Original Assignee||Harris Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (40), Non-Patent Citations (7), Referenced by (25), Classifications (6), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to a zero insertion force interconnect system wherein the connector for connecting a daughter board to a mother board is an integral part of and is formed simultaneously with construction of the mother and daughter boards and etching of the circuit traces thereon.
Electrical printed circuit boards (or printed wiring boards) with their mounted circuit components are well known and have long provided an advantageous technique for assembling electronic components in an orderly fashion and connecting these components together to form electronic circuits. The interconnections between these electronic components can be formed by printing or machine-depositing conductors on an insulating surface of the printed circuit board. Alternatively, the insulating surface is covered with a conductive material, the desired interconnection paths are masked, and the remaining unmasked portions of the conductive surface are etched away. The insulating layer of the printed circuit board is usually composed of phenolic-glass epoxy laminate, polyimide laminate, or ceramic. The conductive interconnecting material is usually copper.
With advances in the development of miniaturized and micro-electronic circuits for printed circuit boards, it has become necessary, and increasingly difficult, to develop interconnection techniques for accurately connecting adjacent circuit elements on a printed circuit board and interconnecting adjacent printed circuit boards. In the early 1960's the dual in-line package (DIP) became a popular package for integrated circuits. The DIP has a lead spacing of 100 mils. With increasing miniaturization and the desire to place more integrated circuits onto a circuit board, flat pack integrated circuit packages were developed and saw industry-wide use in the mid to late 1960's. Because lead spacing for flat pack packages is 50 mils, more flat pack packages than dual-in-line packages can be interconnected on a given printed circuit board. With the continued development of still smaller and more complicated integrated circuits, known as very high-speed integrated circuits (VHSIC), lead spacing has decreased to 20 mils.
As more components are mounted on a printed circuit board, it becomes necessary to provide more interconnection points between printed circuit boards of an electronic system. As is well known in the art, the typical technique for interconnecting boards is by providing a row of contacts or pins along one edge of each board such that each board (referred to as daughter board) may be plugged into a matching socket located on a mother board, establishing an interference contact. Interconnection wiring is provided between the pins on the daughter board and the daughter board electronic components, and between the socket on the mother board and the mother board electronic components. Both the contacts and sockets have to be built with care and accuracy to provide a reliable contact between the boards; the cost of providing these interconnections using the prior art methods can easily become a substantial part of the total system cost. Current interconnect requirements frequently require a connector to make 200 to 400 contacts with the contacts spaced apart by 30 to 50 mils. Using a pin-socket arrangement with this spacing, it is easy for one or more of the pins to become deflected and/or mate improperly in the socket, causing poor contact or no contact. Also, the insertion force, which is only two to four ounces per pin, aggregates to 50 to 100 pounds of insertion force in a high-pin count connector. Thus the problems caused by close connector spacing have become a dominant failure mode in electronic systems.
Alternatively, the interconnections between the mother and daugter board can be made in other ways. The connection can be made in a permanent manner using soldered or welded joints. While this provides a less costly initial assembly, it is difficult and expensive to later repair a system having permanent interconnections. Also, ribbon cables are frequently used to interconnect printed circuit boards. Each ribbon cable comprises a plurality of wires arranged side by side in a flat configuration. Each wire of the ribbon cables can be permanently soldered to a point on a printed circuit board, or connectors can be placed at one or both ends of the ribbon cable for insertion into a socket on the printed circuit boards.
Today, the principle technique for avoiding the prior art pin crunching connector mating device is to use connectors commonly referred to as the zero insertion force connectors. In this type of connector the pins and sockets are mated without any contact of the mating surfaces so that there is very little mating force. After the two halves have been mated, a latch or cam mechanism is operated to engage all of the contacts and complete the interconnection. Another advantage usually associated with zero-insertion force connectors is volume reduction over the prior art pin-socket arrangements. This feature is especially important in small-space environments, such as avionics packages for aircraft. These zero insertion force connectors have become very popular and many different types are available. Such a zero insertion force connector is disclosed and claimed in U.S. Pat. No. 4,517,625. This patent discloses and claims a circuit board with a plurality of electrical contacts mounted along an edge thereof. The housing into which the circuit board is placed has at least one zero insertion force socket including a plurality of contacts mounted therein. The circuit board is placed in the socket and a pair of jaws are moved to releasably engage the edge portion of the circuit board. With the motion of the jaws the electrical contacts of the circuit board are brought into contact with the electrical contacts on the housing.
By eliminating the pin-socket configuration, most zero insertion force connectors reduce the signal path length from the daughter board to the mother board, and also eliminate the possibility of discontinuities at the pin-socket connection. At the high frequencies associated with today's VHSIC and microwave technologies, these features reduce signal losses and delays. The present invention further improves upon these features.
The zero insertion force connector of the present invention is a novel departure from the prior art zero insertion force connectors. The present invention is an interconnect system, which takes into account the electrical transmission characteristics of the contact, rather than a simple zero insertion force connector. More specifically, the interconnect system of the present invention is integral with and fabricated at the same time as the traces on the printed circuit board. Thus the interconnect system eliminates the necessity for a separate connector as has been the common practice previously. The interconnect system comprises a rigiflex printed circuit board, an elastomer rod, and the well-known multi-layer glass epoxy printed circuit boards. Additional support members are also a part of the interconnect system.
In one embodiment, the daughter board portion of the interconnect system utilizes a rigid-flex printed circuit board having gold-plated contacts exposed in the flexible area. The flexible area is controlled by an elastomer rod and a retaining housing is also a part of the daughter board (or module). A gold-plated contact pattern is etched on the mother board (or back panel) and is backed by a structural member to provide rigidity. Gas-tight electrical contact between the contacts of the daughter board and the contacts of the mother board is achieved when screws are inserted through holes in the structural member and tightened.
The advantages of this novel interconnect system over the prior art connector designs are numerous. These advantages include cost and weight reduction and higher contact density, as well as better electrical performance. The present invention offers a higher number of contacts in a comparable space. That is, in one embodiment up to 420 contacts are available in a standard 3/4 Avionics Transit Rack (ATR) enclosure, (which has a cross-section of 7.63 inches wide by 7.51 inches high). The solderless connections of the present invention also provide third level interconnections as an integral part of the printed board. (First level interconnections are within the integrated circuit chips; second level interconnects are between the electronic components and the printed circuit board; third level interconnects are between printed circuit boards, including a mother board (or back plane)-daughter board configuration.) Also, the direct and short electrical interface of this third level interconnect ensures better electrical performance.
The present invention can be more easily understood, and the further advantages and uses thereof more readily apparent, when considered in view of the description of the preferred embodiments and the following figures in which:
FIG. 1 is a partial illustration of the interconnect system of the present invention;
FIG. 2 is a perspective view of the interconnect system of the present invention;
FIG. 3 is a more detailed view of the daughter board contacts shown in FIG. 1;
FIGS. 4 and 5 are more detailed views of the mother board contact pattern of FIG. 1;
FIGS. 6 and 7 are detailed views of the mother board contact pattern for a second embodiment of the present invention;
FIG. 8 is a detailed view of the daughter board contacts for a third embodiment of the present invention;
FIG. 9 is a detailed view of the daughter board contacts for a fourth embodiment of the present invention;
FIGS. 10A through 10D illustrate the daughter board contact patterns for various embodiments of the present invention;
FIG. 11 shows the mother board and daughter board assembly in electrical contact for yet another embodiment of the present invention;
FIG. 12 illustrates the daughter board assembly in an unfolded configuration; and
FIG. 13 is a cross-sectional view of the daughter board assembly; and
FIGS. 14-19 illustrate other embodiments of the present invention.
FIG. 1 is a simplified view of a zero insertion force interconnect system 10 of the present invention. The zero insertion force interconnect system 10 includes two substrates 3 and 4 adapted for mounting electrical components thereon. The substrates 3 and 4 are held in a spaced-apart relationship by a resilient rod 5. A plurality of conductive traces (one conductive trace is represented by reference character 6 in FIG. 1) extend between the substrates 3 and 4 and around the rod 5. When the substrates 3 and 4 are brought into contact with another planar member (not shown in FIG. 1), the conductive trace 6 mates with conductive traces on this other planar member so as to connect the components mounted on the substrates 3 and 4 with other electrical circuits. The remaining figures show more detailed embodiments of the present invention.
FIG. 2 is a perspective view of the zero insertion force interconnect system 10 of the present invention. The zero insertion force interconnect system 10 includes a daughter board assembly 12 and a mother board 14. The daughter board assembly 12 includes a plurality of gold-plated contacts 16 arranged in a predetermined pattern, and the mother board 14 includes a plurality of gold-plated contacts 18 arranged in a pattern to align with the gold-plated contacts 16 of the daughter board assembly 12. In the embodiment illustrated in FIG. 1 there are 420 gold-plated contacts 16 and 420 gold-plated contacts 18; there are 210 gold-plated contacts in a top row and 210 in a bottom row, separated by an insulating space. The gold-plated contacts 16 and 18 are spaced at 0.025 inches (25 mils). The daughter board assembly 12 comprises two printed circuit boards; one of these printed circuit boards is designated by the reference character 20 and is shown in FIG. 2. The second printed circuit board (reference character 22) is parallel to and beneath the printed circuit board 20 and only the edge can be seen in the FIG. 2 perspective view. A heat sink, a conductive spacer or heat conductive plate can be placed between the printed circuit boards 20 and 22 if it is necessary to conduct heat away from the daughter board assembly 12. The heat sink is not shown in FIG. 2. Otherwise, a simple spacer is used between the two printed circuit boards 20 and 22 to obtain the required rigidity. The daughter board assembly 12 is fitted into a housing 24 for securing the daughter board assembly 12 to the mother board 14. The housing is detachably mounted to the daughter board assembly 12 using screws designated generally by reference character 26. In the FIG. 2 embodiment there are three screws 26. The housing 24 and the daughter board assembly 12 mount to the mother board 14 using screws 28. The screws 28 extend through an extruded backing member 30 and holes 32 in the mother board 14, and finally engage threaded holes 34 in the housing 24. The FIG. 2 embodiment shows three screws 28. Proper alignment between the daughter board assembly 12 and the mother board 14 is provided by alignment pins 36 that slideably engage in alignment holes 38 on the mother board 14. To provide additional support and thermal conduction, card retainers 40 are provided at each end of the mother board for engaging the daughter board. Card retainers of this type are well known in the art; see for example U.S. Pat. No. 3,676,747. FIG. 2 also shows an exemplary electronic component 42 mounted to the printed circuit board 20. Electronic components can also be mounted to the lower printed circuit board 22 in an upside-down fashion, assuming appropriate design of any spacer or conductive member between the printed circuit boards 20 and 22; these are hidden from view in FIG. 2. Traces on the printed circuit boards 20 and 22 connect the electronic components together, and where necessary these traces are extended from the printed circuit boards 20 and 22 and overlaid with gold to form the gold-plated contacts 16. When the daughter board assembly 12 is mounted to the mother board 14, as discussed above, the gold-plated contacts 16 and 18 mate and touch to connect the components on the printed circuit boards 20 and 22 to the mother board 14 and thus to other components of the electronic system. In another embodiment, components can also be mounted on either or both sides of the mother board 14.
FIG. 3 is a close-up cross sectional view along line AA of FIG. 2. FIG. 3 also shows a spacer 23 and an elastomeric rod 50 that extends the length of the daughter board assembly 12. Extending from the printed circuit boards 20 and 22 are outer insulator layers 52 and 52', traces 54 and 54', and an inner insulator layer 56. The outer insulator layers 52 and 52' are removed, as shown, to expose a portion of the traces 54 and 54'. The traces 54 and 54' are copper traces etched in the printed circuit board and exposed in the area of the elastomeric rod 50. The traces 54 and 54' are gold plated for protection against corrosion and to enhance conductivity to form the gold-plated contacts 16 and 16'. As can be seen in this embodiment, the gold-plated contacts 16 and 16' are not continuous around the elastomeric rod 50, but instead form two separate contact points for mating with the mother board 14. As can be appreciated by those skilled in the art, the traces 54 and 54' are not required to terminate on the printed circuit boards 20 and 22, but may pass through to other adjacent circuit boards not shown in FIG. 3.
The gold-plated contacts 18 on the motherboard 14 must also have a split pattern to mate with the gold-plated contacts 16 and 16'. This pattern is shown generally in FIG. 4 and a few of the gold-plated contacts 18 are shown in a close-up fashion in FIG. 5. As can be seen clearly in FIG. 5, the gold-plated contacts 18 are split in half, with the top row mating with the top row of gold-plated contacts 16 and the bottom row of gold-plated contacts 18 mating with the lower row of gold-plated contacts 16'. The elastomeric rod 50 provides a slightly springy interaction between the daughter board assembly 12 and the mother board 14 to ensure contact between the gold-plated contacts 16 and 16' and the gold-plated contacts 18. To ensure good electrical contact it is also necessary that there be some wiping action between the gold-plated contacts 16 and 16' and the gold-plated contacts 18 during the initial mating. This wiping action is provided by the springy effect of the elastomeric rod 50 and the shape of edge of the housing 24.
FIGS. 6 and 7 show another pattern for the gold-plated contacts 18 of the mother board 14. FIG. 7 is a sectional close-up of several of the gold-plated contacts 18 of FIG. 6. In this embodiment the gold-plated contacts 16 and 16' on the daughter board assembly 12 and the gold-plated contacts 18 on the mother board 14 are continuous from top to bottom and thus only half as many contact points are provided, as compared with the embodiment of FIGS. 4 and 5. In the embodiment of FIGS. 6 and 7 only 210 contacts are shown although any number of contacts can be provided dependent upon the length of the printed circuit boards 20 and 22' and the required manufacturing tolerances for the fabrication of the gold-plated contacts 16, 16', and 18. For mating with the gold-plated contacts 18 of FIGS. 6 and 7, the gold-plated contacts 16 of the daughter board assembly 12 would be continuous (i.e., there would be no separation such as the separation shown in FIG. 3).
FIG. 8 illustrates another configuration for the gold-plated contacts 16 of the daughter board assembly 12. In the FIG. 8 embodiment there is a triple set of gold-plated contacts, designated by reference characters 16, 16', and 16". The gold-plated contact 16" is connected to components on the daughter board assembly 12 via a trace 58 located between the inner insulator layer 56 and an insulator layer 60. Thus, using the FIG. 8 embodiment with 25 mils spacing, it is possible to provide 630 zero insertion force contact points between the daughter board assembly 12 and the mother board 14. The gold-plated contacts 16 and 16' must mate with appropriately configured gold-plated contacts 18 on the mother board 14. The gold-plated contacts 18 would be similar to those illustrated in FIG. 4, except that the gold-plated contacts 18 would be split into thirds, rather than halves.
FIG. 9 illustrates a microstrip or stripline embodiment for the gold-plated contacts 16 of the daughter assembly board 12. Assembly of the housing 24, the rigid-flex circuit boards 20, the planar member 22, and the elastomeric rod 50 are identical to that illustrated in FIG. 3. The various elements traversing a circumferential section of the elastomeric rod 50 form a stripline conductor. It is obvious to those skilled in the art, however, that these elements could also be configured to form a microstrip conductor. Specifically, there is shown an insulating layer 70, an upper ground plane 72, an insulating layer 74, a conductive trace 76, an insulating layer 78, a lower ground plane 80 and an insulating layer 82. As can be seen, a portion of the insulating layer 70, the upper ground plane 72, and the insulating layer 74 is removed to expose the trace 76. The exposed trace is coated with gold, so as to form the gold-plated contact 16. The various layers illustrated in FIG. 9 continue the length of the daughter board assembly 12 to form a series of stripline interconnects between the daughter board assembly 12 and the mother board 14. If it is necessary to continue the stripline configuration on the mother board side of the interconnect, it would be necessary to configure the gold-plated contacts 18 in a stripline form similar to the gold-plated contacts 16 shown in FIG. 9. Thus the embodiment of FIG. 9 is suitable for use in high-speed digital or microwave applications where it is desired to provide a one or more closely spaced transmission line interconnections between the mother board and a daughter board.
As previously discussed and as shown in FIG. 1, gold-plated contacts 16 extend the length of the daughter board assembly 12. FIGS. 10A through 10D illustrate a single gold-plated contact 16 in the various configurations discussed above. FIG. 10A shows the single continuous gold-plated contact 16 suitable for mating with the mother board configuration illustrated in FIGS. 6 and 7. FIG. 10B shows the split gold-plated contacts 16 and 16' that are shown in FIGS. 1 and 2. FIG. 10C shows the triplicate gold-plated contacts: the upper gold-plated contact 16, the lower gold-plated contact 16', and the middle gold-plated contact 16". This embodiment is shown in side view form in FIG. 8. FIG. 10D shows a transmission line form of the gold-plated contact 16. The gold-plated contact 16 of FIG. 10D would be used in the stripline (or microstrip) configuration of FIG. 9 and could be suitably shaped to provide optimum RF coupling between the daughter board assembly 12 and the mother board 14.
FIG. 11 illustrates the mating area of another mother board/daughter board interconnection scheme. The FIG. 11 embodiment is also suitable for high speed digital or RF microwave applications. The reference character 100 is the line of demarcation between the daughter board assembly 12 above the dashed line 100, and the mother board 14 below the dashed line 100. The printed circuit boards 20 and 22 of the daughter board assembly 12 each comprise a stripline conductor having conductive ground planes insulated from conductive traces as is well known in the art. These traces extend from the printed circuit boards 20 or 22 to form a signal contact 106. The ground planes also extend from the printed circuit boards 20 or 22 to form ground plane contacts 108 and 110 on each side of the signal contact 106. In this configuration the signal conductor 106 is completely surrounded by ground planes to provide exceptional signal isolation characteristics. The mother board 14 is similarly constructed with a signal contact 112 surrounded on both sides by ground plane contacts 114 and 116. Insulating layers 120, 122, and 124, ground plane layers 130 and 132, and a circuit trace layer 140 complete the stripline configuration on the mother board 14. The signal contact 112 is connected to the circuit trace layer 140 by a via 141. Thus as can be seen in this embodiment the signal contacts 106 and 112 are surrounded not only above and below but also on each side by ground planes. This embodiment would therefore provide lower losses and crosstalk, and better performance than the simpler stripline interconnect scheme shown in FIG. 9. Further, the signal contacts 106 and 112 can be suitably shaped to enhance the high-speed and RF characteristics.
FIG. 12 illustrates the daughter board assembly 12 in a flat or unfolded configuration. The gold-plated contacts 16 in the upper portion thereof are continuous across the contacting area; the gold-plated contacts on the lower portion are split to form the gold-plated contacts 16 and 16' shown in FIG. 3. This configuration is useful for the assembly of parts to the daughter board assembly 12.
FIG. 13 is an exploded cross-sectional view of the daughter board assembly 12, which illustrates the components that are stacked to form the daughter board assembly 12. The rigid top and bottom layers 144 and 144' are formed of a rigid polyimide or epoxy material. Pre-preg layers 145 and 145' are adjacent to the top and bottom layers 144 and 144'. Continuing toward the center of the daughter board assembly 12, there is a cover layer 146 beneath the pre-preg layer 145 and a cover layer 146' above the pre-preg layer 145'. The cover layers 146 and 146' include adhesive on their center facing surfaces to adhere to a flexible copper-clad polyimide layer 147. The flexible copper-clad polyimide layer 147 has circuit traces within it, which are exposed in the area indicated generally by reference character 148. Once the circuit traces are exposed, the circuit traces are gold plated to form the gold plated contacts 16. Note that with the exception of the cover layer 146' and the flexible copper-clad polyimide layer 147, each of the layers stack to form the daughter board assembly 12 are split in the area 148. The layer segments to the left and right of the area 148 form the rigid area; the daughter board assembly 12 is flexible in the area 148. After the components 42 are mounted to the daughter board assembly 12, it is flexed to bring the two rigid areas together in the shape shown in FIG. 2. The flexible copper-clad polyimide layer 147 also includes a ground plane on the bottom surface thereof. After the various layers are stacked, the assembly is subjected to an elevated temperature and pressure to join the layers together. This technique for assembling printed circuit boards is well known in the art.
FIG. 14 illustrates another technique for mating the elastomeric rod 50 with the daughter board assembly 12. FIG. 14 illustrates a connector housing, having two members designated by reference characters 150 and 151. A lead frame also having two members designated by reference 152 and 154 serves as an electrical path between traces on the daughter board assembly 12 and the mother board 14 (not shown in FIG. 14). The FIG. 14 illustration also includes a lead retainer 156 for holding the lead frames 152 and 154 in proper position. The FIG. 14 assembly can be held together by screws (not shown in FIG. 14) extending vertically downward from the connector housing 150 to the lead retainer 156 or extending vertically upward from the connector housing 151 to the lead retainer 156. Although the daughter board assembly 12 is shown in FIG. 14 as a single board having contacts on both sides thereof, it is well known to one skilled in the art that the daughter board assembly 12 can be replaced by two parallel printed circuit boards having electrical traces on one or both sides.
FIG. 15 illustrates yet another embodiment of the present invention wherein the mother board 14 is configured to mate with a plurality of daughter board assemblies 12. The daughter board assemblies 12 can be mounted on one or both sides of the mother board 14 as shown, using the extruded backing member 30 as shown in FIG. 2. A suitably configured mother board 14 can also act as a heat sink for transferring heat away from the daughter board assemblies 12.
FIG. 16 illustrates yet another embodiment utilizing the inventive techniques associated with the present invention. Two printed circuit boards, designated by reference characters 180 are shown in FIG. 16 as connected by a ribbon cable 181. Rather than using the typical pin/socket interconnect scheme with the ribbon cable 181, the embodiment of FIG. 16 uses elastomeric rods 182 to urge exposed areas of the ribbon connector 181 against contacts on the printed circuit boards 180. To form these contact areas, the insulation is stripped from the ribbon cable 181 in selected areas and the exposed conductors are then gold-plated to form contacts, such as the gold-plated contacts 16 in FIG. 2. A mating contact configuration is etched onto the printed circuit boards 180 and the gold-plated contacts of the ribbon cable 181 are urged against the contacts of the printed circuit boards 180 by the elastomeric rods 182, and a support member, such as the extruded backing member 30 shown in FIG. 2.
FIG. 17 shows an embodiment similar to that of FIG. 16, with the printed circuit boards 180 having a spherical or cylindrical, rather than a planar, configuration. Component mounting is illustrated by the component 42. To take maximum advantage of this configuration, high-speed signals can be routed on the inner (smaller) printed circuit board 180 while constant or slowly-changing signals (e.g., power supply voltages) can be placed on the outer (larger) printed circuit board 180.
FIG. 18 illustrates another embodiment constructed according to the teachings of the present invention. The FIG. 18 embodiment includes an inner mother board 200 and an outer mother board 202 interconnected by daughter boards 12, which are constructed according to the teachings of the present invention. Components 42 can be mounted on one or both sides of the daughter boards 12, as shown. The daughter boards 12 would have the basic construction shown in FIG. 2 with the mating contacts on the inner surface of the outer mother board 202 or the outer surface of the inner mother board 200. Alternatively, the daughter boards 12 can be constructed with the elastomeric rod 50 and the gold-plated contacts 16 on two parallel edges thereof so that they can mate with matching contacts on both the inner surface of the outer mother board 202 and the outer surface of the inner mother board 200. Again, to take maximum advantage of this configuration, high speed signals can be routed on the outer mother board 202 while constant or slowly-changing signals can be routed on the inner mother board 200. The FIG. 18 embodiment is cylindrical in shape, with FIG. 18 actually being a cross-section through the cylinder. The cylindrical shape of FIG. 18 is merely exemplary, other shapes, such as square or rectangle, could also be accommodated with this embodiment.
FIG. 19 illustrates another embodiment constructed according to the teachings of the present invention. In this embodiment the daughter boards 12 are constructed according to the teachings of the present invention for mating with a spherical mother board 208. The mating pattern for the daughter board assemblies 12 is etched into the outside surface of the sphere 208. The signal paths can be located on the inner or outer surface of the sphere for interconnecting the various daughter board assemblies 12. The daughter board assemblies 12 can be mounted to the sphere using the extruded backing member 30 illustrated in FIG. 2 or using any other well-known techniques for printed circuit board mounting. The sphere 208 may be separable into two halves for accessing the interior surface thereof and for carrying signals out of the sphere 208 via a cable bundle 210. Alternatively, the daughter board 12 assemblies can simply be mounted to the surface of the sphere and printed circuit traces on the exterior surface can route the signals between the daughter board assemblies 12 and also serve as a terminal point for connection of the cable bundle 210.
As can now be appreciated, the present invention is amenable to numerous embodiments in which printed circuit board traces are extended from a flexible member (e.g., a daughter board) to form contact areas for mating with a rigid surface (e.g., a mother board). The number and spacing of such contacts can be varied and the contacts can be shielded by variously configured ground planes to optimize high-speed or RF performance. The incorporation of a heat conducting member as a supporting member in various embodiments enhances the usefulness of the present invention and contributes to its many unique geometries.
Although I have shown and described several embodiments in accordance with the present invention, it is understood that the present invention is not limited to these embodiments, but is susceptible of numerous changes and modifications as known to a person skilled in the art. I therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.
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|U.S. Classification||439/67, 361/749, 439/65|
|Jun 3, 1987||AS||Assignment|
Owner name: HARRIS CORPORATION, 1025 WEST NASA BLVD., MELBOURN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:COTTI BENEDICTO;REEL/FRAME:004731/0291
Effective date: 19870529
Owner name: HARRIS CORPORATION, A CORP. OF DE,FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:COTTI BENEDICTO;REEL/FRAME:004731/0291
Effective date: 19870529
|Dec 29, 1992||REMI||Maintenance fee reminder mailed|
|May 30, 1993||LAPS||Lapse for failure to pay maintenance fees|
|Aug 17, 1993||FP||Expired due to failure to pay maintenance fee|
Effective date: 19930530