US 4837724 A Abstract In a discrete cosine transformation (DCT) arrangement with an equivalent distribution between accuracy of intermediate results and the number of calculation operations to be performed, the group of N input samples is first subjected to a shuffle operation (903). Consequently, these input samples are applied to a combination circuit (90) in a sequence which is different from the sequence in which they are received. The combination circuit (90) supplies the sum and the difference of each two successive input samples. A selection circuit (91) continuously returns all sum samples except the last one to the input of the combination circuit. Each difference sample and the last sum sample is multiplied once in a multiplier (92) by one weighting factor from a group of weighting factors and the product samples obtained thereby are group-wise accumulated in an accumulator circuit (93), with each group supplying a transform coefficient.
Claims(7) 1. An arrangement for real-time calculation of discrete cosine transformation coefficients of a group of N signal samples of a time-discrete input signal, comprising:
combination means receiving the signal samples as well as a number of auxiliary samples for adding and subtracting predetermined combinations of said signal samples and said auxiliary samples for generating sum and difference samples; selection means receiving the sum and difference samples and supplying said auxiliary samples as well as transfer samples, the auxiliary samples being constituted by selected ones of the sum and difference samples and the transfer samples being comprised by the remaining sum and difference samples; multiplication means receiving the transfer samples and multiplying each by only one weighting factor selected from a plurality of predetermined weighting factors for generating product samples; and accumulator means receiving the product samples for accumulating given samples of said product samples for generating the coefficients. 2. An arrangement as claimed in claim 1, wherein the auxiliary samples are comprised by sum samples.
3. An arrangement as claimed in claim 1 further comprising shuffle means to which the N-signal samples are applied in a first sequence and which supplies these signal samples in a second sequence which corresponds to the combinations of samples to be added or to be subtracted.
4. An arrangement as claimed in claim 1 wherein the combination means comprises two memories for storing a first and a subsequent second sample, which samples are applied to an adder-subtractor circuit and are supplied by a selection circuit which receives signal samples and the auxiliary samples and which applies them selectively to the two memories.
5. An arrangement for real-time calculation of N inverse discrete cosine transformation signal samples of a time-discrete signal from a group of N discrete cosine transformation coefficients, comprising:
multiplication means receiving the coefficients and multiplying each by only one weighting factor selected from a plurality of predetermined weighting factors for generating product samples; accumulator means receiving the product samples for adding each time given samples of said product samples together for generating accumulation samples; combination means receiving the accumulation samples as well as a number of auxiliary samples for adding and subtracting predetermined combinations of said accumulation samples and auxiliary samples for generating sum and difference samples; and selection means receiving the sum and difference samples and supplying said auxiliary samples as well as transfer samples, the auxiliary samples being comprised by selected ones of the sum and difference samples and the transfer samples being comprised by the remaining sum and difference samples. 6. An arrangement as claimed in claim 5 further comprising shuffle means to which the N-coefficients are applied in a first sequence and which supplies these coefficients in a second sequence which corresponds to the combinations of coefficients to be added or to be subtracted.
7. An arrangement as claimed in claim 5 wherein the combination means comprises two memories for storing a first and a subsequent second sample, said first and second samples being applied to an adder-subtractor circuit and being supplied by a selection circuit which receives the accumulation samples and the auxiliary samples and which applies them selectively to the two memories.
Description (1) Field of the Invention The invention relates to an arrangement for real-time calculation of the discrete cosine transformation coefficients of a group of N inputs samples of a digital input signal. It is particularly intended for performing a transform coding of a digitalized video signal to reduce its bit rate. Such an arrangement will hereinafter be referred to as a DCT arrangement. The invention also relates to an arrangement for calculating the original N input samples from the coefficients thus obtained. Such an arrangement will be referred to as an IDCT arrangement. (2) Description of the Prior Art As is generally known, transform coding is a data reduction method in which a television picture is divided into blocks of N×N picture elements and in which each block is considered to be a sum of a series of (N×N) mutually orthogonal basic pictures B(i,k) where i,k=0, . . . , N-1, each with its own weighting factor y(i,k). Data reduction is possible because the information is concentrated only in a limited number of non-correlated basic pictures due to the correlation of the picture elements in a block, so that only the associated weight factors are important and the others can be ignored. To indicate mathematically how the weighting factors are calculated, the block of N×N picture elements will be represented by an N×N matrix X, the weighting factors will be arranged in an N×N matrix Y and an N×N transform matrix A will be defined which is related to the set of basic pictures B(i, k). More particularly, there applies that:
B(i,k)=A In this expression, A
Y=A In this expression, A For the calculation of the weighting factors in accordance with expression (2), both the original transform matrix A and its transposed version A
Y Only the transform matrix A needs to be available for this matrix multiplication. More particularly, the product matrix P=XA can be calculated first. Subsequently, P can be transposed and finally Y In order to recover the original block of picture elements X from the weighting factors thus obtained, these weighting factors are subjected to an inverse transformation which is defined as follows:
X=AYA In conformity with the foregoing this expression is equivalent to:
X=A(AY It is to be noted that a product matrix such as P=XA and Y The number of non-negligible weighting factors appearing from such a transformation is found to be closely related to the structure of the basic pictures chosen and hence to the transform matrix chosen. The most optimum transform matrix which is nowadays frequently used is the discrete cosine transform matrix whose elements a(i,k) are defined as follows: ##EQU1## Q is a scaling constant which is equal to 2/N if this matrix is used to calculate the weighting factors for the direct transformation and which is equal to 1 if it is used for the inverse transformation. When two N×N matrices are multiplied by each other in a conventional way, which in that case is referred to as the direct method, N The invention has for its object to provide an alternative embodiment of a DCT arrangement in which considerably less stringent requirements need to be imposed on the accuracy of the intermediate results, possibly in exchange for an acceptable increase of the number of mathematical operations to be performed as compared with the DCT arrangement which is described in Reference 5. According to the invention, a DCT arrangement comprises: combining means to which the N-picture elements of a row of a block of N×N picture elements are applied and a number of auxiliary samples, and which is adapted to add and subtract predetermined combinations of picture elements, and to add and subtract predetermined combinations of auxiliary samples, for the purpose of generating sum and difference samples; selection means receiving the sum and difference samples supplying said auxiliary samples as well as transfer samples, the auxiliary samples being constituted by selected ones of said sum- and difference samples and the transfer samples being constituted by the remaining sum and difference samples. multiplication means receiving the transfer samples and multiplying each by only one weighting factor selected from a plurality of predetermined weighting factors for generating product samples; and accumulator means receiving the product samples and being adapted to accumulate given samples for generating the coefficients. By using the invention, each incoming picture element is multiplied only once by some number, in this case the multiplication factor of the transform matrix, so that the accuracy of the intermediate results need to be no greater than the accuracy with which the coefficients are desired. However, this is accompanied by an increase of the number of mathematical operations to be performed (at least compared with the DCT arrangement described in Reference 5). In fact, in this DCT arrangement according to the invention, approximately b 22 multiplications and 34 additions (comprising 20 accumulation operations) are found to be necessary in the case of N=8, which numbers are, nevertheless, found to be very acceptable for practical uses. 1. Real-time orthogonal transformation of colour-television pictures; H. Bacchi, A. Moreau; Philips Technical Review, Vol. 38, No. 4/5, 1978/1979, pages 119-130. 2. Method of and arrangement for digitizing a colour video signal; J. H. Peters, U.S. Pat. No. 4,405,936. 3. Multiple Point, Discrete Cosine Processor; L. W. Randy, A. Mesa; U.S. Pat. No. 4,449,194. 4. A Fast Computational Algorithm For The Discrete Cosine Transform; W. H. Chen, C. H. Smith, S. C. Fralick; IEEE Transactions on Communications, Vol. COM-25, No. 9, September 1977, pages 1004-1009. 5. A New Algorithm To Compute The Discrete Cosine Transform, B. G. Lee; IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. ASSP-32, No. 6, December 1984, pages 1243-1245. 6. Method of and arrangement for digitizing a time-discrete video signal using a picture transform coding; J. H. Peters; U.S. Pat. No. 4,398,217. FIG. 1 diagrammatically shows a transform and encoding arrangement for video signals; FIG. 2 shows at which instants these signals are sampled. The Figure also shows the signal samples which together form a block; FIG. 4 shows an 8×8 DCT transform matrix; FIG. 5 shows a diagram representing a new DCT-algorithm; FIG. 6 shows the DCT arrangement according to the invention based on the algorithm of FIG. 5; FIG. 7 shows a further embodiment of the DCT arrangement of FIG. 6; FIG. 8 shows a selection circuit for use in the arrangement of FIG. 7; and FIG. 9 shows an IDC arrangement according to the invention. (1) The transform coding arrangement. FIG. 1 shows diagrammatically a transform and encoding arrangement for video signals. It comprises a video signal source 1 supplying a video signal x(t). This signal is applied to a sampling circuit 2 which takes samples x(qT) from this video signal under the control of sampling pulses S(qT). In this case there applies that q= . . . , -1, 0, 1, 2, . . . and that the sampling pulses occur at a frequency f An embodiment of the transform arrangement 5 is shown for the sake of completeness in FIG. 3. It is provided with a block-forming circuit 7 and a transform circuit 8. The block-forming circuit 7 partitions a picture into blocks of N×N picture elements (video signal samples), for example, in the manner as shown for N=8 in FIG. 2. To this end, it has an input 70 which receives the successively occurring digital video signal samples x(q). A cascade arrangement of N-1 (=7) delay lines 71(.) each having a capacity of R-8 video signal samples is connected to this input 70. R is the number of video signal samples of a television line. The input 70 of this block-forming circuit 7 and the outputs of each delay line 71 (.) are connected via respective AND-gate circuits 72(.) to inputs of an OR-gate circuit 73. Each AND-gate circuit 72(.) also receives 8 control pulses in such a manner that first 8 video signal samples are applied from the delay line 71(7) to the transform circuit, then 8 video signal samples from the delay line 71(6), then 8 video signal samples from the delay line 71 (5), and so forth. These control pulses are generated by a modulo-64 counter 74 to which the sampling pulses S(qT) are applied. A decoding network 75, having eight outputs 75 (.) which are connected to inputs of the AND-gate circuits 72(.), is connected to this counter 74. This decoding network supplies a logic "1" at the output 75(7) each time the counter has one of the computing positions 1, 2, 3, . . . 8. A logic "1" occurs at the output 75(6) each time the counter has one of the counting positions 9, 10, 11, . . . 16 and so forth. In this manner the video signals of a block occur successively and row by row at the output of the OR-gate circuit 73. The transform circuit 8 is constituted by a first transformer 9, a memory 10 and a second transformer 11. These transformers have the same structure and are each constituted by a DCT arrangement. In this case the transformer 9 supplies the product matrix P=XA (see expression (3)) which consists of the coefficients p (2) The DCT arrangement, general structure. In the transformer 9 or 11 formed as a DCT arrangement all N picture elements of a row in a block are multiplied by all N columns of the DCT transform matrix A whose elements are defined in expression (6) and which is shown in FIG. 4 for N=8. As is apparent from this Figure, this DCT matrix has a very specific structure due to the periodical character of the goniometric function. When the digital video signal samples of the i-th row of an 8×8 block are represented by x
C
TABLE 1______________________________________p In the above case N=8 so that q=16. Now it holds, for instance that a A diagram representing the algorithm worked out for N=8 in Table 1 is shown in FIG. 5. It appears from this Figure that for calculating the coefficients p An embodiment of the DCT arrangement whose implementation is based on the new DCT algorithm shown in FIG. 5 is shown in FIG. 6. It comprises a shuffle circuit 903 to which the digital video signal samples are applied in the sequence x In the embodiment shown, a memory circuit 95 as a buffer circuit is incorporated for practical reasons between the selection circuit 91 and the multiplier circuit 92. This has been done because the rate at which mathematical operations must be performed in the combination circuit 90 can be lower than the rate at which mathematical operations must be performed in the multiplier circuit 92. (3) The DCT arrangement, detailed structure. FIG. 7 shows a more detailed embodiment of the DCT arrangement. The operation of this arrangement is diagrammatically shown in Table 2. More particularly, the first column in Table 2 indicates the reference numbers of a number of memories present in FIG. 7 and the other columns represent the contents of these memories after a clock pulse has occurred. These clock pulses are enumerated 1 to 53, inclusive in the first row. In this Table, the indices i as used in the foregoing as well as in FIG. 5 have been omitted for the video signal samples and for the coefficients. It is to be noted that in this Table 2, a dash "-" means that the content of the relevant memory is unchanged. In the DCT arrangement which is shown in FIG. 7 the shuffle circuit 903 is constituted by two memories 903 (.) with addressable memory locations; for example, RAMs. Each of them receives the digital video signal samples x The selection circuits 905(.) are built up in the same manner and each have two inputs 9051(.) and 9052(.) The inputs 9052(.) receive the digital video signal sample which is stored in latch 904(.) and the inputs 9051(.) receive auxiliary samples which are applied via inputs 902(.) to the combination circuit. These selection circuits 905(.) also receive two control commands SEL The samples present in the latches 906(.)
TABLE 2 Cl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 904(1) X are applied to an adder-subtractor circuit 907 which is controlled by an adding command AC and a subtraction command SC. This circuit 907 subtracts each time the two samples present in the latches 906(1) and 906(2) so that the difference samples u The buffer circuit 95 is built up in the same manner as the shuffle circuit 903. It also comprises two RAM's 951(.) which are controlled by the read and write address commands R To calculate the desired transformation coefficients, these transfer samples are also applied to the multiplier circuit 92. This circuit 92 comprises two further latches 921 and 922 which are controlled by latch enable commands LE As is shown in Table 2, the transfer samples u The above-mentioned clock pulses occur at a rate which is, for example, six times as high as the sampling frequency f As already expressed in the opening paragraph, an inverse transformation is to be performed on the ultimately obtained weighting factors in order to recover the original picture elements. This inverse transformation requires an inverse discrete cosine transformation. It can be realized by means of the IDCT arrangement shown in FIG. 9. It differs from the DCT arrangement of FIG. 6 exclusively in the location of the circuit combinations 90, 91 and 92, 93. Patent Citations
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