|Publication number||US4855251 A|
|Application number||US 07/267,707|
|Publication date||Aug 8, 1989|
|Filing date||Nov 3, 1988|
|Priority date||Jun 26, 1986|
|Publication number||07267707, 267707, US 4855251 A, US 4855251A, US-A-4855251, US4855251 A, US4855251A|
|Inventors||Kiyoshi Iyogi, Koji Yamakawa, Nobuo Iwase|
|Original Assignee||Kabushiki Kaisha Toshiba|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Non-Patent Citations (4), Referenced by (10), Classifications (28), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 064,397, filed on June 22, 1988, now abandoned.
This invention relates to a method of manufacturing electronic parts, based on the transferred bump process.
Recent efforts aimed at miniaturizing a semiconductor chip used in, for example, an IC, LSI, etc., have been accompanied by efforts to reduce the size of its package. The package has a role of an electrode lead to extend from an aluminium electrode on the semiconductor chip, thereby to allow for its easy handling and to protect it from external pressure. The extending of a lead from the aluminium electrode of the semiconductor chip to the terminal of the package can be conveniently effected by use of the tape automated bonding (TAB) process.
The TAB process consists in forming a bump on the electrode and effecting connection between the bump and the electrode lead. It is necessary to use electroplating in order to mount an Au bump on the Al electrode of the semiconductor substrate. However, since it is difficult to directly adhere an Au bump to an Al electrode, the customary process is to deposit a multiple barrier metal mass composed of, for example, Cu, Cr and Ti on the Al electrode, before performing plating.
As a result, a bump-transferring process has been devised which comprises the steps of first forming a bump on a substrate, transferring the bump to a lead, and then to the desired electrode, and thermally pressing the bump to effect the connection with the electrode (Japanese Patent Disclosure Nos. 57-152147 and 60-92648). This proposed process dispenses with the aforementioned barrier metal, thereby simplifying the formation of the bump and the bump assembly, and enabling a plurality of electrodes to be simultaneously connected to terminals.
FIGS. 1A to 1E show the sequential steps of the bump-transferring process. As is shown in FIG. 1A, substrate 5 on which a bump is to be formed is constructed by laminating conductive layer 2, conductive oxide layer 3, and resist pattern 4, in that order, on base-substrate 1. Bump 6 is electroplated in the bump-forming opening of substrate 5. Conductive oxide layer 3 should preferably be prepared from a material which can be readily connected to gold bump 6 and easily released from bump 6 when it is transferred to the lead. In the second step, (FIG. 1B), electrode lead member 8, supported on insulating film 7, is placed on bump 6. Thereafter, heated bonding tool 9 is pressed on electrode lead member 8, thereby transferring bump 6 to electrode lead 8 (FIG. 1C). Later, as can be seen in FIG. 1D, bump 6 transferred to electrode lead 8 is positioned above al electrode (bonding pad) 12 exposed out of passivation layer 11 of semiconductor chip 10. Thereafter, previously heated bonding tool 9 is pressed on electrode lead 8, thereby connecting electrode lead 8 to Al electrode 12, with bump 6 interposed therebetween.
However, the above-mentioned bump-transferring process has drawbacks in that the bump tends to peel off from an oxide layer, to which it is adhered, during the step of electroplating the bump on the substrate and also during the subsequent bump-washing step, thus resulting in a decline in throughput.
This invention is intended to provide a method of manufacturing electronic parts, based on a bump-transferring process which prevents a bump from falling off during the electroplating and washing steps, and ensures a high bonding strength between the transferred bump and the electrode section of a semiconductor chip.
To attain the above-mentioned object, the present invention provides a bump in which the metal particles in that portion of a bump contacting a substrate are of a larger size than those which are not brought into contact with the substrate.
It is preferable, from the viewpoint of manufacturing, that the particles in that portion of a bump contacting a substrate have a diameter larger than 1 μm, that the bump have a thickness of 15˜25 μm, and that the portion of a bump which is composed of the particles having a larger diameter has a thickness of less than 2 μm. The bump can be prepared from gold, copper, etc.
In order to form a bump having the above-defined particle size distribution, it is advisable to set the initial electroplating current density at 2 to 5 times that which is applied thereafter. Either cyanide solution (KAu(CN)2 etc.) or non-cyanide solution (Na3 Au(SO4)2 etc.) can be used for the plating solution.
The present invention offers the advantages in that the particles in that portion of a bump which contacts a substrate are of a larger size than those which do not contact the substrate, thereby ensuring a stronger adhesive bond between the bump and substrate, and enabling the bump to be readily removed from the substrate when it is to be transferred to the electrode lead, and thus ensuring a high-strength bond between the bump and the electrode section of the semiconductor chip, due to the surface of the removed bump being free from irregularities.
FIGS. 1A to 1E show the sequential steps of manufacturing an electronic part, by use of the bump-transferring method; and
FIG. 2 is a sectional view of the bump embodying the present invention, which has been completely plated.
Cr conductive layer 2, having a thickness of 1000 Å, and ITO (Indium Tin Oxide; InSnO2) conductive oxide layer, having a thickness of 2000 Å, were thermally deposited on glass base-substrate 1, in that order. Later, resist pattern 4 acting as a mask, wherein a bump-forming region was perforated, was formed on ITO layer 3 by means of photoetching, thereby completing substrate 5. Thereafter, substrate 5 was overturned so as to form a uniform plating layer, and was dipped, in this state, in a gold-electroplating cyanide solution (65° C., stirred at any time). Electroplating was performed for 30 seconds, with the initial current density increased to 3 times the generally recommended level of 1 A/dm2. Electroplating then continued under the abovementioned recommended level. This resulted in gold bump 6 being formed with a thickness of 25 μm (FIG. 1A). When observation was made of the vertical section of bump 6, a crystal particle size distribution such as that indicated in FIG. 2 was observed; i.e. the crystals contacting ITO layer 3 had a particle size larger than 1 μm. The crystals lying thereon, namely, those which do not contact ITO layer 3, had a particle size of about 5000 Å.
As is indicated in FIG. 1B, copper electrode lead 8, supported by polyimide film 7 and plated with tin, was set above bump 6. Electrode lead 8 was pressed on bump 6 by means of bonding tool 9 heated to 280° C. for 2 seconds, under the pressure of 20 g per Pin (lead number). Later, bonding tool 9 was removed and electrode lead 8 was peeled off from substrate 5, thus enabling bump 6 to be transferred to electrode lead 8, as can be seen in FIG. 1C.
Later, as is shown in FIG. 1D, transferred bump 6 was set above Al electrode (bonding pad) 12 exposed out of passivation layer 11 of semiconductor chip 10, and bonding tool 9 was positioned above electrode lead 8. Using bond tool 9, bump 6 was thermally pressed onto Al electrode 12 for 2 seconds, at a temperature of 380° C., under the pressure of 80 g for 1 Pin. As is shown in FIG. 1E, electrode 8 was connected to Al electrode 12, with bump 6 interposed therebetween. The bonding strength between bump 6 and Al electrode 12 indicated 40 g/lead.
When a bump is formed by the above-mentioned process, the surface of ITO layer 3 is activated because the initial current density is high, and the metal particles impinge on ITO layer 3 at a high speed, thus presumed to increase bonding strength.
Electroplating was applied for 3 seconds to a substrate on which a bump was to be formed, with the initial current density increased to 5 times the generally recommended level of 1 A/dm2. Subsequently, electroplating was continued at this recommended level. Then, as is indicated in FIG. 2, a gold bump 6 was formed on the substrate 5, in such a manner that the portion of the bump contacting the substrate consisted of particles larger than those in other portions thereof. It was confirmed that use of the above method effectively prevented the bump formed thereby from peeling off from or falling off the substrate.
A bump was formed on a substrate substantially in the same manner as in Example 1, except that electroplating was performed with the generally recommended current level of 1 A/dm2 being sustained throughout the process. The bump thus formed was connected to the Al electrode section of a semiconductor chip. Observation of the vertical section of an electroplated gold bump showed that the crystal particles of the bump all had a diameter of about 5000 Å, thereby indicating that this method failed to produce a distribution of crystal particle diameters such as was obtained in Examples 1 and 2.
In this Control, the bump either peeled off from fell off the substrate during the electroplating step and the succeeding washing step. The bonding strength between the bump and Al electrode was found to be 10 g/lead.
It should be noted that the present invention is not limited to the above-mentioned examples. Any other method of forming a bump is applicable, provided that the bump is prepared in such a manner that those portions of a bump which contact the substrate are formed of larger crystal particles than the other portions thereof.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3621564 *||May 7, 1969||Nov 23, 1971||Nippon Electric Co||Process for manufacturing face-down-bonded semiconductor device|
|US4494688 *||Mar 11, 1982||Jan 22, 1985||Matsushita Electric Industrial Co., Ltd.||Method of connecting metal leads with electrodes of semiconductor device and metal lead therefore|
|FR2460347A1 *||Title not available|
|JP6092648B2||Title not available|
|JP57152147A||Title not available|
|JPH0692648A *||Title not available|
|JPS57152147A *||Title not available|
|1||H. Y. Chen, "Current Distribution During the Electrodeposition of Gold," J. Electrochem. Soc., vol. 117, No. 5, May 1970, pp. 609-614.|
|2||*||H. Y. Chen, Current Distribution During the Electrodeposition of Gold, J. Electrochem. Soc., vol. 117, No. 5, May 1970, pp. 609 614.|
|3||Hatada et al., "New Film Carrier Assembly Technology Transferred Bump Tab", Proc. IEEE 1986 Symposium, Sep. 1986, pp. 122-127.|
|4||*||Hatada et al., New Film Carrier Assembly Technology Transferred Bump Tab , Proc. IEEE 1986 Symposium, Sep. 1986, pp. 122 127.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5057453 *||May 29, 1990||Oct 15, 1991||Kabushiki Kaisha Toshiba||Method for making a semiconductor bump electrode with a skirt|
|US5171711 *||Oct 17, 1991||Dec 15, 1992||Mitsubishi Denki Kabushiki Kaisha||Method of manufacturing integrated circuit devices|
|US5485337 *||Jun 6, 1994||Jan 16, 1996||Sharp Kabushiki Kaisha||Thin film magnetic head structure and method of fabricating the same for accurately locating and connecting terminals to terminal connections|
|US6232211 *||Apr 16, 1997||May 15, 2001||Matsushita Electric Industrial Co., Ltd.||Two-step projecting bump for semiconductor chip and method for forming the same|
|US6551854 *||Mar 21, 2001||Apr 22, 2003||Kabushiki Kaisha Toshiba||Semiconductor device having bump electrodes and method of manufacturing the same|
|US7009294 *||Dec 31, 2003||Mar 7, 2006||Rohm Co., Ltd.||Production process for semiconductor device|
|US7282801||Sep 14, 2005||Oct 16, 2007||Samsung Electronics Co., Ltd.||Microelectronic device chip including hybrid Au bump, package of the same, LCD apparatus including microelectronic device chip and method of fabricating microelectronic device chip|
|US20040152236 *||Dec 31, 2003||Aug 5, 2004||Rohm Co., Ltd.||Production process for semiconductor device|
|US20060055037 *||Sep 14, 2005||Mar 16, 2006||Samsung Electronics Co., Ltd.||Microelectronic device chip including hybrid Au bump, package of the same, LCD apparatus including microelectronic device chip and method of fabricating microelectronic device chip|
|DE102005045661B4 *||Sep 14, 2005||Aug 9, 2007||Samsung Electronics Co., Ltd., Suwon||Mikroelektronischer Bauelementchip und Herstellungsverfahren, Packung und LCD-Vorrichtung|
|U.S. Classification||29/827, 228/180.21, 257/E21.508, 438/106, 438/616, 257/E23.021|
|International Classification||H01L21/60, H01L23/485|
|Cooperative Classification||H01L2224/11003, H01L2224/111, Y10T29/49121, H01L2224/13144, H01L24/11, H01L2924/01082, H01L2924/01078, H01L2924/01033, H01L2924/01006, H01L2924/01013, H01L2224/13099, H01L2924/01022, H01L24/13, H01L2924/01029, H01L2924/01079, H01L2924/0001, H01L2924/01024, H01L2924/01049|
|European Classification||H01L24/10, H01L24/11|
|Jun 5, 1989||AS||Assignment|
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:IYOGI, KIYOSHI;YAMAKAWA, KOJI;IWASE, NOBUO;REEL/FRAME:005094/0458
Effective date: 19870611
|Jan 25, 1993||FPAY||Fee payment|
Year of fee payment: 4
|Jan 28, 1997||FPAY||Fee payment|
Year of fee payment: 8
|Feb 27, 2001||REMI||Maintenance fee reminder mailed|
|Aug 5, 2001||LAPS||Lapse for failure to pay maintenance fees|
|Oct 9, 2001||FP||Expired due to failure to pay maintenance fee|
Effective date: 20010808