Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS4868133 A
Publication typeGrant
Application numberUS 07/324,858
Publication dateSep 19, 1989
Filing dateMar 16, 1989
Priority dateFeb 11, 1988
Fee statusPaid
Publication number07324858, 324858, US 4868133 A, US 4868133A, US-A-4868133, US4868133 A, US4868133A
InventorsWalter Huber
Original AssigneeDns Electronic Materials, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Radiant heating; rapid thermal processing
US 4868133 A
Abstract
The concentration of internal gettering sites within a semiconductor wafer is controlled by two-step thermal processing. In a concentration reduction phase, the wafer is rapidly heated to an elevated temperature in the range from about 900 to 1350 C., resulting in the partial or total dissolution of precipitable impurities within the wafer. In a concentration enhancement step, the wafers are subjected to a relatively low temperature anneal process where the density of potential internal gettering sites is increased. By properly controlling the processing temperatures and treatment times, the two steps may be performed in either order to obtain wafers having internal gettering site concentrations within a desired range.
Images(6)
Previous page
Next page
Claims(6)
What is claimed is:
1. A method for controlling the oxygen cluster concentration within a silicon substrate, said method comprising performing the following steps in the order set forth:
heating the substrate to an intermediate temperature in the range from about 600 C. to 750 C. for a time period sufficient to precipitate a concentration of oxygen clusters within the substrate;
radiantly heating the substrate to an elevated temperature in the range from about 1000 C. to 1250 C. at a rate of at least about 25 C. per second to dissolve oxygen clusters leaving a concentration in the range from about 105 to 5106 /cm2 within the substrate; and
cooling the substrate to a temperature below about 600 C.
2. A method as in claim 1, wherein the radiant heating is performed in an inert atmosphere.
3. A method as in claim 1, wherein the radiant heating rate is at least about 10 C. per second.
4. A method as in claim 1, wherein the substrate is held at the elevated temperature for a period of at least about 1 second.
5. A method as in claim 4, wherein the substrate is cooled at a rate of at least about 10 C. per second.
6. A method as in claim 1, wherein the substrate is held at the intermediate temperature for at least about 15 minutes.
Description

This is a division of application Ser. No. 154,759 filed Feb. 11, 1988.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the fabrication of semiconductor wafer substrates. More particularly, the invention relates to the fabrication of silicon wafer substrates under conditions which control the concentration of internal gettering sites.

Single-crystal silicon, the starting material for most semiconductor fabrication processes, is most commonly prepared by the Czochralski method wherein a single seed crystal is dipped into molten silicon and slowly withdrawn. By rotating the crystal, a cylindrical ingot having a desired diameter is produced. The molten silicon is held in a quartz crucible.

Although characterized by very high purity, Czochralski method silicon crystals have a certain level of impurities. Most importantly, oxygen derived from the quartz crucible is present in concentrations from about 10 to 20 ppma. Such concentrations are above solid solubility at temperatures typical for integrated circuit manufacture processes. Being in supersaturated solution, the oxygen atoms will tend to precipitate. The precipitation of oxygen provides trapping sites for impurities detrimental for the performance of integrated circuits. This technique for removing impurities away from the vicinity of the active wafer surface by oxygen precipitation is referred to as "internal gettering."

Heretofore, the benefits associated with gettering caused by internal oxygen precipitation clusters have been somewhat serendipitous. Although the initial concentration of dissolved oxygen in the silicon ingots may be controlled, the concentration of gettering sites which are generated on subsequent thermal treatment of individual wafers depends on a number of factors and will vary widely. Thus, while the optimum concentration of gettering sites for a particular application may be known, the actual concentration present in a wafer undergoing processing has been very difficult to adjust to a specific concentration.

It would therefore be desirable to provide methods for controlling the concentration of gettering sites present in semiconductor substrates. More particularly, it would be desirable to provide methods capable of controlling the concentration of oxygen precipitation sites within silicon substrates prepared by the Czochralski method and other conventional silicon preparation methods.

2. Description of the Background Art

Hawkins and Lavine (1987) Materials Research Society Mtg., Nov. 30-Dec. 5, demonstrate a putative heterogeneous nucleation mechanism for oxygen in silicon by subjecting a wafer first to a rapid thermal anneal followed by annealing at 950 C. for one hour and 1200 C. for 13 hours. No optimization of internal gettering site concentration is disclosed. Alvi et al. (1987) Electrochemical Society Mtg., Oct. 18-23, describe the effect of rapid thermal annealing on the dissolution of metallic precipitates in silicon wafers. Hahn et al. (1986) Material Research Society Symp. Proc. 59:287-292, describe the formation of thermal donors by the annealing of silicon wafers at 450 C., followed by rapid thermal annealing at 600 C. to 1000 C., followed further by two-step furnace annealing at 700 C. and 950 C. The paper does not consider the desirability of re-establishing a desired concentration of oxygen precipitates. Chang-Outu and Tobin (1986) J. Electrochem. Soc. 133:2147-2152, suggests that the precipitation of oxygen in wafer fabrication processes depends strongly on the initial concentration of dissolved oxygen in the silicon. An initial oxygen concentration in the range from about 14 to 16 ppma is taught to be optimum for subsequent gettering of impurities. Jastrzebski et al. (1984) J. Electrochem. Soc. 131:2944-2953 suggest a correlation between the amount of precipitated oxygen and the particular conditions of silicon wafer fabrication. Inoue et al. (1981) in "Semiconductor Silicon 1981", ed. Huff et al., Proc. Vol. 81-5, The Electrochemical Society, pp 282-293, teaches that the concentration of oxygen precipitates in a silicon wafer can be increased by low temperature annealing. Finally, U.S. Pat. No. 4,608,095, relates to external gettering by providing a layer of polysilicon on the rear surface of the wafer.

SUMMARY OF THE INVENTION

According to the present invention, methods are provided for controlling the concentration of internal gettering sites, such as oxygen clusters, within a semiconductor substrate. The methods rely on a two-step process where the concentration of gettering sites is first either substantially increased or substantially decreased. By increasing the gettering site concentration above the desired optimum level, the concentration can then be reduced to the desired optimum level by rapid heating at a particular temperature or range of temperatures for a preselected time period. Alternatively, by initially reducing the concentration of internal gettering sites below the desired optimum, the concentration may then be increased by thermal annealing at relatively moderate temperatures for a preselected time period. In this way, the final concentration of internal gettering sites is dependent neither on the initial impurity concentration nor the processing history of the semiconductor wafer crystal.

In the exemplary embodiment, silicon wafer substrates are first rapidly heated to an elevated temperature in the range from about 900 to 1300 C., preferably from about 1000 to 1250 C. The heating rate is usually at least about 10 C. per second, preferably being at least about 100 C. per second, and the wafer substrate will be maintained at the elevated temperature for a period of at least about 1 second, usually for a period of at least about 5 seconds, depending on the precise temperature to which the wafer has been heated. Such rapid heating of the silicon substrates has been found to substantially reduce the concentration of relatively small oxygen clusters (i.e., those capable of growing into gettering sites) in the silicon wafer substrates. Usually, the concentration of small oxygen clusters will be reduced sufficiently to achieve an internal gettering site concentration below about 106 /cm2, frequently being reduced to less than about 105 /cm2 and occasionally being reduced to less than about 104 /cm2.

After the initial reduction, the concentration of relatively small oxygen clusters may be increased to a desired optimum level by annealing the substrates at a relatively moderate temperature, typically in the range from about 550 to 850 C., more typically in the range from about 600 to 750 C., for a relatively long time period, typically in the range from about 15 to 360 minutes, usually being from one to four hours. The precise time and temperature of the annealing will be selected to provide the optimum gettering site concentration, usually in the range from about 105 to 5106 /cm2, more usually in the range from about 2105 to 106 /cm2.

After the wafers are treated by the process of the present invention, they are ready for conventional wafer fabrication processes where active regions are formed on the upper surface thereof. During such conventional processes, impurities within the semiconductor wafer will be attracted to the oxygen cluster gettering sites and away from the active surface of the wafer.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

The present invention provides a method for controlling the concentration of internal gettering sites within semiconductor substrates used in the fabrication of integrated circuits. Internal gettering sites evolve from the coalescing of certain impurities into clusters having a critical threshold mass. Such clusters attract other deleterious impurities during subsequent thermal processing of the semiconductor wafer. By drawing such deleterious impurities away from the active surface of the substrate, integrated circuit yield and performance can be greatly improved.

Without pretreatment of the wafers, the concentration of the internal gettering sites may vary widely, typically within a range from about 104 to 107 sites/cm2. Desirably, the concentration of such sites at the commencement of the normal wafer fabrication processes will be in the range from about 105 to 5106 sites/cm2, preferably in the range from about 2105 to 106 sites/cm2.

Control over the concentration of the internal gettering sites is achieved by pretreating the wafer in a two-step procedure including both a concentration reduction phase and a concentration enhancement phase for the impurity clusters. By initiating the concentration reduction phase first, the concentration of impurity clusters having the critical mass is reduced below the desired level. The desired level may then be achieved by performing the concentration enhancement phase under preselected conditions and for a time chosen to provide the precise concentration desired. Inversely, by initiating the concentration enhancement phase first, the concentration of impurity clusters having the critical mass may be increased above the desired level. The desired concentration may then be achieved by performing the concentration reduction phase under conditions and for a time chosen to provide the desired level.

The method of the present invention is used to control the concentration of internal gettering sites in single-crystal semiconductor wafers used in the fabrication of integrated circuits for the electronics industry. While silicon will normally be the wafer material of choice, other semiconductor materials, such as gallium arsenide, indium phosphide, gallium aluminum arsenide, germanium, silicon carbide, indium antimonide, and the like, may also find use. The semiconductor materials may possess any conventional crystal lattice orientation and resistivity, and will be of conventional dimensions as used in the wafer fabrication industry.

The semiconductor materials employed will contain impurities, including both precipitable impurities which will coalesce into clusters which act as the gettering sites and deleterious impurities, usually metallic impurities, which will be removed from the active surface of the semiconductor substrate by the gettering sites. Desirably, the deleterious impurities will be substantially removed from a one to 50 micron layer immediately beneath the active surface, more typically from a 10 to 30 micron layer immediately below the active surface.

The precipitable impurities will comprise mobile atoms capable of coalescing into clusters having an empirically-derived critical mass under the processing conditions specified herein. Usually, the precipitable impurities will be present in the semiconductor material as a result of the initial crystal growth process, although in some cases it may be necessary or desirable to intentionally introduce the impurities during the growth process. In silicon semiconductor crystals produced by the Czochralski process, the precipitable impurity will normally be oxygen atoms which are derived from the quartz crucible liner which holds the molten silicon from which the crystals are drawn. The oxygen will usually be present at a concentration near the solubility limit, typically in the range from about 10 to 20 ppma (parts per million atomic basis as measured by ASTM F121-83), usually being between about 12 to 18 ppma. Other impurities and defects, such as nitrogen, carbon, silicon native defects and the like, may be added during the crystal growth phase if it is desired to raise the concentration of the precipitable impurities.

When the silicon crystal is produced by the float-zone process, the precipitable impurities must be intentionally added. Precipitable impurities, such as nitrogen, oxygen, carbon, and the like, may be utilized. Conveniently, the precipitable impurity will be nitrogen introduced by crystal growth in a nitrogen-containing environment to a concentration in the range from about 0.1 to 10 ppma.

The semiconductor material produced by both the Czochralski process and the float-zone process will be in the form of large cylindrical ingots which will be sliced into individual wafers, typically having a thickness in the range from about 10 to 50 mils, more typically in the range from about 15 to 27 mils. the wafers are sliced using diamond slicing saws, and may be treated by the method of the present invention either immediately after slicing or subsequent to further preparation steps. Such further preparation steps include lapping to remove irregularities caused by the slicing and polishing to produce an optical quality surface. Additionally, the wafers may be coated with thin films, including oxides, nitrides, polysilicon layers, and the like. Any layers deposited prior to processing according to the present invention must be able to withstand the processing conditions described hereinafter.

The deleterious impurities which are attracted by the gettering sites in the wafers include primarily metallic species, such as iron, nickel, copper, titanium, and the like. The contaminants will collect at the gettering sites during the normal thermal processing of the wafers utilized to construct the integrated circuit devices.

The internal gettering sites will be clusters of the precipitable impurities, typically oxygen or nitrogen, having a critical mass or number of atoms, which is sufficiently large so that the sites will attract the impurities during the subsequent thermal processing of the wafer. The precise mass will vary depending both on the nature of the semiconductor material and on the nature of the precipitable impurity. Operationally, gettering sites may be defined as clusters capable of attracting the deleterious impurities under the thermal processing conditions employed in semiconductor fabrication, typically in a temperature range from about 400 to 1250 C., more typically in a range from about 800 to 1150 C. Untreated wafers will generally have a distribution of precipitable impurity cluster sizes, with those larger than the critical mass threshold size being capable of growing and attracting impurities and defects during the wafer fabrication processes. Without control, the concentration of such gettering sites may vary broadly in the range from about 104 to 107 sites/cm2. The desired range is from about 105 to 510.sup. 6 sites/cm2, usually from about 2105 to 106 sites/cm2, and may be achieved by the method of the present invention.

The internal gettering site concentration reduction phase comprises rapid heating of the semiconductor wafer from a temperature below about 100 C., usually being about room temperature, to a final temperature in the range from about 900 C. to 1300 C., more usually being from about 1000 C. to 1250 C., preferably being from about 1050 C. to 1200 C. The heat treatment time at the elevated temperature will vary as a function of the final temperature, with lower temperatures requiring generally longer treatment times. The treatment time must be sufficiently long to allow dissolution of the clusters of precipitable impurities initially present in the wafer so that the concentration of clusters having the critical growth mass will be below the desired level, typically being below about 106 sites/cm2, more typically being below about 105 sites/cm2, and occasionally being below about 104 sites/cm2. Conveniently, for Czochralski silicon wafers having internal oxygen impurities, the following time and temperature relationship has been found suitable.

              TABLE 1______________________________________Final Treatment Heat TreatmentTemperature     Time______________________________________1000 C.          >20    sec.1050 C. >10      sec.1100 C. >5       sec.1150 C. >2       sec.1200 C. >1       sec.1250 C. >1       sec.______________________________________

The time and temperature relationship set forth in Table 1 is based on silicon wafers having an average initial oxygen concentration in the range from about 10 ppma to about 20 ppma, more usually being in the range from about 12 ppma to 18 ppma (ASTM F121-83). In some cases, it may be desirable to empirically develop specific time and temperature relationships for particular types of wafers having known impurities, crystal lattice orientations, resistivities, and the like. The temperature and treatment time required to control the internal gettering site concentration to within the desired range may then be determined as a function of the measured initial oxygen concentration of the particular wafer. That is, by measuring the initial oxygen concentration of each wafer or batch of wafers being treated (conveniently by ASTM F121-83) the wafers may be precisely treated to gain the desired gettering site concentrations.

Rapid heating of the wafers comprises a heating rate of at least about 10 C./sec., preferably being at least about 100 C./sec. or greater. Such rapid heating may be accomplished by radiant heating, typically using rapid thermal processing equipment commercially available from suppliers such as Peak Systems, Inc., Fremont, Calif., Varian Associates, Palo Alto, Calif., and AG Associates, Sunnyvale, Calif. In particular, a Heat Pulse Model 210T available from AG Associates has been found suitable for practicing the concentration reduction phase of the method of the present invention. The rapid heating will be performed under an inert or non-oxidizing atmosphere, typically argon or nitrogen.

After completing the rapid thermal heating step, it is necessary to rapidly cool the wafers down to a temperature below about 600 C., typically back down to about room temperature. The cooling should be achieved at a rate of at least about -10 C./sec., preferably being at least about -50 C./sec. When employing the rapid thermal processing equipment described above, such cooling may be effected by simply turning off the radiant heat sources.

The concentration enhancement phase of the present invention comprises annealing the wafers by heating to a temperature in the range from about 550 to 850 C., usually in the range from about 600 to 750 C., for a retention time selected to enhance the formation of precipitable clusters so that the concentration of internal gettering sites is within the desired range set forth above. Typically, the treatment time will be in the range from about 15 minutes to 360 minutes or greater, more typically being from about one to four hours. Such low temperature treatment will typically be carried out in a conventional batch furnace under an inert or non-inert atmosphere. Alternatively, it would also be possible to perform the concentration enhancement phase using rapid thermal processing equipment, although usually it would not be preferred.

Normally, the temperature of the wafer will be ramped up from room temperature to the anneal temperature at a rate in the range from about 1 to 20 C. per minute, more usually in the range from about 2 to 10 C. per minute. Such rates, however, are not critical and faster ramping would be acceptable so long as the total treatment time within the desired temperature range results in the desired increase in concentration of internal gettering sites. Once the final anneal temperature is reached, the temperature will usually be maintained steady until the retention time is expired and it is desired to cool the wafer. There is no theoretical reason, however, why the temperature could not be varied during the low temperature anneal treatment so long as at the end the desired concentration of internal gettering sites is achieved.

As stated above, the order of the concentration reduction phase and the concentration enhancement phase is not critical, and it is possible to perform either processing step initially. Preferably, however, the concentration enhancement phase will be accomplished first in order to increase the concentration of internal gettering sites well above the desired level. It has been found that the concentration reduction phase is somewhat more reproducible than the enhancement phase. Thus, by performing the reduction phase last, a more precise concentration of internal gettering sites may be obtained.

After treatment according to the present invention, the semiconductor wafers are ready for conventional semiconductor fabrication operations in order to form the desired integrated circuits on the active surface of the wafer. The wafers may be utilized for any of the conventional microelectronic technologies, including thick-film hybrid, thin-film hybrid, bipolar monolithic, and metal oxide semiconductor (MOS) monolithic technologies. The internal gettering sites created during the method of the present invention will act to attract impurities and crystalline defects from the active surface of the wafer during the normal thermal exposure of the wafer during conventional processing steps. In this way, the impurities and defects are removed from the active surface in order to improve the device yield on the wafer.

The following examples are offered by way of illustration, not by way of limitation.

EXPERIMENTAL

1. Experimental Procedure

The effects of rapid thermal processing (RTP) on oxygen precipitation were demonstrated on p-type silicon wafers with extrinsic gettering capabilities which are provided by a polysilicon layer on the backside of the wafer. A low pressure chemical vapor deposition (LPCVD) reactor was employed for the polysilicon deposition, and operated in the 650 C. to 700 C. temperature range. This temperature range enhanced the formation of oxygen clusters in the bulk of the wafer and, consequently, oxygen precipitation in subsequent IC manufacture steps. A number of p-type silicon wafers having oxygen concentrations of 15.6 ppma (ASTM F-121-83), and a polysilicon layer on the backside, were rapidly annealed from 1100 to 1200 C. for times ranging from 10 to30 seconds.

P-type silicon wafers with oxygen contents ranging from 15 to 18 ppma and astandard chemically etched backside were heat treated in a conventional furnace at temperatures ranging from 700 to 800 C. for 1 to 4 hours. These conditions increased the density of oxygen clusters in the bulk of the wafers. After the low temperature anneal, the silicon wafers were subjected to a 30 second rapid thermal anneal with temperatures ranging from 1100 to 1200 C.

Another set of p-type silicon wafers with a standard backside were first rapidly heat treated at temperatures ranging from 1000 to 1200 C. For all temperatures, the anneal time was 30 seconds. After the rapid thermal treatment, the wafers were annealed in a conventional tube furnace at 700 to 800 C. The low temperature treatment times varied from 2 hours to 4 hours.

The rapid thermal treatments were carried out in a commercially available system manufactured by AG Associates (Heat Pulse Model 210T). In this system, the annealing chamber is heated by two banks of tungsten-halogen lamps. A quartz diffusion tube positioned between the two lamp banks contains the silicon wafer. During the short heat cycle, the tube was continuously purged with argon. The wafer temperature was monitored by a very low mass thermocouple mounted next to the wafer and controlled by a closed-loop temperature controller.

Prior to any heat treatment, the interstitial oxygen content of the siliconwafers was determined with an FTIR spectrophotometer (ASTM F-121-83). The interstitial oxygen content was again measured after the extended oxygen precipitation cycle described in Table 2. This heat cycle was employed after the rapid thermal and low temperature anneal so the effects of both thermal treatments on oxygen precipitation could be evaluated. The difference in oxygen concentration before and after this precipitation cycle, therefore, is a measure for the density of internal gettering sitesin the bulk of the silicon wafer, and is referred to as a drop in interstitial oxygen in this application. The oxygen precipitate density present in the bulk of the wafer after the heat cycle of Table 2 was determined from a cleaved cross section that was etched with a Secco etch solution for 2.5 minutes. Both characterization techniques are widely usedin the electronics industry.

              TABLE 2______________________________________Process Conditions for the Precipitation Cycle______________________________________Push:     6"/min., 900 C., oxygen ambientSoak:     900 C., oxygen ambient, 30 minutesRamp:     From 900 C. to 1025 C., oxygen ambientAnneal:   1025 C., nitrogen ambient, 8 hoursRamp:     From 1025 C. to 1000 C., nitrogen ambientPull:     6"/min., 1000 C., nitrogen ambient______________________________________

2. Experimental Results and Discussion

The change in interstitial oxygen and oxygen precipitate density in siliconwafers with a polysilicon layer on the backside was determined, as described above, and the average values are given in Table 3. From the tabulated results it can be seen that the internal gettering sites createdduring the polysilicon deposition can be either partially or completely dissolved after a short rapid thermal processing step. After a 1200 C. treatment, the oxygen precipitation kinetics in a silicon wafer with a polysilicon layer on the backside became indistinguishable from a wafer with a standard backside. The application of this invention, therefore, allows an independent control of the intrinsic and extrinsic gettering capabilities of silicon wafers.

              TABLE 3______________________________________Silicon Wafers with Extrinsic GetteringCapabilities of a Polysilicon Layer                       Drop in  Rapid       Initial  Interstitial  Thermal     Oxygen   Oxygen  Precipitate  Treatment   Content, Content,                               DensityWafer  Conditions  ppma     ppma    cm-2______________________________________A      No          15.9     5.4     5.3  106B      1100 C., 30 sec.              15.6     1.9     1.7  106C      1200 C., 10 sec.              15.6     0.3D      1200 C., 30 sec.              15.6     0.4     3.2  104E      1200 C., 30 sec.              16.2     0.4     4.8  104(Control)______________________________________

Table 4 summarizes the average of the results obtained on standard silicon wafers that first were pre-annealed at low temperatures and then rapidly heat treated. The data show that the amount of precipitated oxygen can be controlled by choosing the proper pre-anneal and rapid thermal anneal conditions. The effect of rapid thermal processing diminishes for higher pre-anneal temperatures.

              TABLE 4______________________________________Silicon Wafers with a LowTemperature Anneal Prior to the RTP Treatment                                Drop in  Low        Rapid       Initial                                Interstitial  Temperature             Thermal     Oxygen Oxygen  Anneal     Treatment   Content,                                Content,Wafer  Conditions Conditions  ppma   ppma______________________________________A      700 C., 1 hr.             --          15.1   3.2B      700 C., 1 hr.             --          16.5   6.3C      700 C., 1 hr.             --          17.9   11.9D      700 C., 1 hr.             1100 C., 30 sec.                         15.3   1.1E      700 C., 1 hr.             1100 C., 30 sec.                         17.7   10.8F      700 C., 1 hr.             1200 C., 30 sec.                         15.2   0.5G      700 C., 1 hr.             1200 C., 30 sec.                         16.6   1.0H      700 C., 1 hr.             1200 C., 30 sec.                         17.7   4.1I      700 C., 4 hr.             --          15.3   7.0J      700 C., 4 hr.             1100 C., 30 sec.                         15.3   5.7K      700 C., 4 hr.             1200 C., 30 sec.                         15.3   1.9L      800 C., 1 hr.             --          17.6   8.6M      800 C., 1 hr.             1100 C., 30 sec.                         18.0   8.6N      800 C., 1 hr.             1200 C., 30 sec.                         18.1   9.3O      --         1100 C., 30 sec.                         14.9   0.2(Control)P      --         1200 C., 30 sec.                         15.6   0.2(Control)______________________________________

For silicon wafers rapidly annealed prior to a low temperature treatment, the drop in interstitial oxygen and precipitate density was recorded as described above and the averages of the results are summarized in Table 5.The presented data demonstrate that a short rapid thermal treatment prior to a low temperature anneal also considerably affects the oxygen precipitation. The amount of precipitated oxygen in a silicon wafer decreases as the rapid thermal anneal temperatures increase.

                                  TABLE 5__________________________________________________________________________As-Grown Silicon Wafers with an RTPTreatment Prior to a Low Temperature Anneal                       Drop inRapid            Initial                       InterstitialThermal  Low     Oxygen                       OxygenTreatment         Temperature                 Content,                       Content,                              PrecipitateWaferConditions         Anneal  ppma  ppma   Density, cm-2__________________________________________________________________________A    --       700 C., 2 hrs.                 14.6  1.5B    --       700 C., 2 hrs.                 15.2  5.0    5.5  106C    --       700 C., 2 hrs.                 17.1  11.2D    --       700 C., 2 hrs.                 15.1  7.3E    1000 C., 30 sec.         700 C., 2 hrs.                 14.9  1.9    8.5  105F    1000 C., 30 sec.         700 C., 2 hrs.                 15.0  4.8    2.2  106G    1000 C., 30 sec.         700 C., 2 hrs.                 17.2  9.8H    1050 C., 30 sec.         700 C., 2 hrs.                 15.1  1.5I    1050 C., 30 sec.         700 C., 4 hrs.                 15.4  4.0    1.8  106J    1050 C., 30 sec.         700 C., 2 hrs.                 17.3  3.6K    1100 C., 30 sec.         700 C., 2 hrs.                 15.0  0.4    6.4  104L    1100 C., 30 sec.         700 C., 4 hrs.                 15.0  1.1    7.5  105M    1100 C., 30 sec.         700 C., 2 hrs.                 17.0  1.1N    1200 C., 30 sec.         700 C., 2 hrs.                 14.9  0.5    1.4  105O    1200 C., 30 sec.         700 C., 4 hrs.                 14.9  1.4    6.4  105P    1200 C., 30 sec.         700 C., 2 hrs.                 16.9  0.9Q    --       800 C., 2 hrs.                 17.3  11.3R    1000 C., 30 sec.         800 C., 2 hrs.                 17.2  9.0S    1050 C., 30 sec.         800 C., 2 hrs.                 17.0  1.0T    1200 C., 30 sec.         800 C., 2 hrs.                 16.6  0.4U    1200 C., 30 sec.         --      15.7  0.5V    --       --      15.2  0.4__________________________________________________________________________

The data of Tables 4 and 5 demonstrate that the density of internal gettering sites in the bulk of a silicon wafer can be individually adjusted to a desired level independent of the initial oxygen content.

Although the foregoing invention has been described in some detail by way of illustration and example for purposes of clarity of understanding, it will be obvious that certain changes and modifications may be practiced within the scope of the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4314595 *Jan 8, 1980Feb 9, 1982Vlsi Technology Research AssociationMethod of forming nondefective zone in silicon single crystal wafer by two stage-heat treatment
US4376657 *Dec 5, 1980Mar 15, 1983Vlsi Technology Research AssociationInterior microdefects as scavengers by heating in a non-oxidizing atmos-phere
US4432809 *Dec 31, 1981Feb 21, 1984International Business Machines CorporationMethod for reducing oxygen precipitation in silicon wafers
US4544418 *Apr 16, 1984Oct 1, 1985Gibbons James FProcess for high temperature surface reactions in semiconductor material
US4548654 *Jun 3, 1983Oct 22, 1985Motorola, Inc.Surface denuding of silicon wafer
US4566913 *Jul 30, 1984Jan 28, 1986International Business Machines CorporationRapid thermal annealing of silicon dioxide for reduced electron trapping
US4608095 *Apr 4, 1985Aug 26, 1986Monsanto CompanyGettering
US4622082 *Jun 25, 1984Nov 11, 1986Monsanto CompanyOxidation, reduction, nucleation
US4637123 *Jun 10, 1985Jan 20, 1987International Business Machines CorporationMethod of standardizing and stabilizing semiconductor wafers
US4661166 *Sep 20, 1984Apr 28, 1987Mitsubishi Denki Kabushiki KaishaPrecipitation of oxygen on silicon single crystal, annealing to form oxide film
US4732874 *Oct 15, 1986Mar 22, 1988Delco Electronics CorporationRemoving metal precipitates from semiconductor devices
US4743569 *Apr 20, 1987May 10, 1988Texas Instruments IncorporatedDoping, short rapid heating; then longer heating at lower temperature; reduced defects
EP0060676A2 *Mar 10, 1982Sep 22, 1982Fujitsu LimitedA method for the production of a semiconductor device comprising annealing a silicon wafer
JPS5821829A * Title not available
JPS6120337A * Title not available
JPS57201032A * Title not available
JPS58103123A * Title not available
JPS58204541A * Title not available
Non-Patent Citations
Reference
1 *Alvi et al., (1987), Electrochemical Soc. Mtg., Oct. 18 23.
2Alvi et al., (1987), Electrochemical Soc. Mtg., Oct. 18-23.
3 *Chang Outu and Tobin, (1986), J. Electrochem. Soc., 133:2147 2152.
4Chang-Outu and Tobin, (1986), J. Electrochem. Soc., 133:2147-2152.
5Craven et al., "Internal Gettering in Silicon", Solid State Techn., Jul. 1981, pp. 55-61.
6 *Craven et al., Internal Gettering in Silicon , Solid State Techn., Jul. 1981, pp. 55 61.
7Ha, "Precipitation of Oxygen in Silicon . . . ", J. Appl. Phys., vol. 52, No. 6, Jun. 1981, pp. 3974-3984.
8 *Ha, Precipitation of Oxygen in Silicon . . . , J. Appl. Phys., vol. 52, No. 6, Jun. 1981, pp. 3974 3984.
9Hahn et al., "Effects of Thermal Donor Generation . . . Oxygen Precipitation", Mat. Res. Soc. Symp. Proc., vol. 59, 1986, pp. 287-292.
10 *Hahn et al., (1986), Material Research Society Symp. Proc., 59:287 292.
11Hahn et al., (1986), Material Research Society Symp. Proc., 59:287-292.
12 *Hahn et al., Effects of Thermal Donor Generation . . . Oxygen Precipitation , Mat. Res. Soc. Symp. Proc., vol. 59, 1986, pp. 287 292.
13 *Hawkins and Lavine, (1987), Materials Research Society Mtg., Nov. 30 Dec. 5.
14Hawkins and Lavine, (1987), Materials Research Society Mtg., Nov. 30-Dec. 5.
15Inoue et al., (1981), in "Semiconductor Silicon 1981", ed. Huff et al., Proc., vol. 81-5, The Electrochemical Society, pp. 282-293.
16 *Inoue et al., (1981), in Semiconductor Silicon 1981 , ed. Huff et al., Proc., vol. 81 5, The Electrochemical Society, pp. 282 293.
17 *Jastrzebski et al., (1984), J. Electrochem. Soc., 131:2944 2953.
18Jastrzebski et al., (1984), J. Electrochem. Soc., 131:2944-2953.
19Pennycock et al., "Transient Enhanced Diffusion and Gettering . . . ", Mat. Res. Soc. Symp. Proc., vol. 36, 1985, pp. 151-156.
20 *Pennycock et al., Transient Enhanced Diffusion and Gettering . . . , Mat. Res. Soc. Symp. Proc., vol. 36, 1985, pp. 151 156.
21Ueda et al., "Identification of Intrinsic Gettering . . . ", J. Appl. Phys., vol. 60, No. 2, Jul. 15, 1986, pp. 622-626.
22 *Ueda et al., Identification of Intrinsic Gettering . . . , J. Appl. Phys., vol. 60, No. 2, Jul. 15, 1986, pp. 622 626.
23Wijaranakula et al., "Internal Gettering . . . in Epitaxial Silicon Wafers," J. Mater. Res., vol. 1, No. 5, Sep./Oct. 1986, pp. 693-697.
24 *Wijaranakula et al., Internal Gettering . . . in Epitaxial Silicon Wafers, J. Mater. Res., vol. 1, No. 5, Sep./Oct. 1986, pp. 693 697.
25Wolf et al., "Silicon Processing for the VLSI Era", Lattice Press, Sunset Beach, Calif., 1986, pp. 66-70.
26 *Wolf et al., Silicon Processing for the VLSI Era , Lattice Press, Sunset Beach, Calif., 1986, pp. 66 70.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5061642 *Jul 25, 1990Oct 29, 1991Fujitsu LimitedMethod of manufacturing semiconductor on insulator
US5066359 *Sep 4, 1990Nov 19, 1991Motorola, Inc.Forming oxygen, carbon or nitrogen containing precipitates, immobilization of heavy metal contaminants
US5096839 *Apr 30, 1991Mar 17, 1992Kabushiki Kaisha ToshibaTwo step heat treatment
US5209811 *Dec 18, 1991May 11, 1993Shin-Etsu Handotai Company Limited Of JapanMethod for heat-treating gallium arsenide monocrystals
US5228927 *Mar 29, 1991Jul 20, 1993Shin-Etsu Handotai Company LimitedMethod for heat-treating gallium arsenide monocrystals
US5279973 *Oct 15, 1991Jan 18, 1994Kabushiki Kaisha ToshibaIn mixture of oxygen and an inert gas
US5286658 *Mar 5, 1992Feb 15, 1994Fujitsu LimitedProcess for producing semiconductor device
US5352615 *Jan 24, 1994Oct 4, 1994Motorola, Inc.Denuding a semiconductor substrate
US5401669 *May 17, 1993Mar 28, 1995Memc Electronic Materials, SpaProcess for the preparation of silicon wafers having controlled distribution of oxygen precipitate nucleation centers
US5403406 *Nov 11, 1991Apr 4, 1995Memc Electronic Materials, SpaContaining oxygen precipitate nucleation centers; integrated circuits, semiconductors; trapping effect
US5418172 *Jun 29, 1993May 23, 1995Memc Electronic Materials S.P.A.Method for detecting sources of contamination in silicon using a contamination monitor wafer
US5436498 *Feb 4, 1994Jul 25, 1995Motorola, Inc.A semiconductor substrate comprising a specific region, at this position by feeding a reactive element scavenging the metal impurities; noncontamination
US5506154 *Sep 11, 1991Apr 9, 1996Komatsu Electronic Metals Co., Ltd.Process for preheat treatment of semiconductor wafers
US5944889 *Nov 26, 1997Aug 31, 1999Samsung Electronics Co., Ltd.Methods of heat-treating semiconductor wafers
US6013556 *Sep 5, 1997Jan 11, 2000Lucent Technologies Inc.Vapor deposition to form integrated circuit wafers, diffusion
US6136677 *Sep 25, 1997Oct 24, 2000Siemens AktiengesellschaftForming a transition region separator between the logic area and the memory area; sequential steps forming silicide junctions in the logic area and implanted junctions in the memory area
US6180220Feb 25, 1998Jan 30, 2001Memc Electronic Materials, Inc.Ideal Oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6190631Apr 9, 1998Feb 20, 2001Memc Electronic Materials, Inc.Low defect density, ideal oxygen precipitating silicon
US6191010 *Aug 27, 1999Feb 20, 2001Memc Electronic Materials, Inc.Process for preparing an ideal oxygen precipitating silicon wafer
US6204152Jun 30, 1999Mar 20, 2001Memc Electronic Materials, SpaIdeal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6204188 *Nov 10, 1997Mar 20, 2001Shin-Etsu Handotai Co., Ltd.Heat treatment method for a silicon wafer and a silicon wafer heat-treated by the method
US6236104Aug 31, 1999May 22, 2001Memc Electronic Materials, Inc.Silicon on insulator structure from low defect density single crystal silicon
US6284384Feb 16, 1999Sep 4, 2001Memc Electronic Materials, Inc.For electronics
US6306733Jul 27, 2000Oct 23, 2001Memc Electronic Materials, SpaIdeal oxygen precipitating epitaxial silicon wafers and oxygen out-diffusion-less process therefor
US6316335 *Oct 13, 1999Nov 13, 2001Matsushita Electric Industrial Co., Ltd.Method for fabricating semiconductor device
US6336968Aug 23, 1999Jan 8, 2002Memc Electronic Materials, Inc.Non-oxygen precipitating czochralski silicon wafers
US6339016Jun 30, 2000Jan 15, 2002Memc Electronic Materials, Inc.Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
US6342436 *Jan 4, 1999Jan 29, 2002Sony CorporationGeneration of bright points after epitaxial growth is reduced; implanting carbon to perform carbon gettering; growing an epitaxial layer;
US6342725Dec 15, 2000Jan 29, 2002Memc Electronic Materials, Inc.Silicon on insulator structure having a low defect density handler wafer and process for the preparation thereof
US6361619Aug 27, 1999Mar 26, 2002Memc Electronic Materials, Inc.Thermally annealed wafers having improved internal gettering
US6416836Oct 13, 1999Jul 9, 2002Memc Electronic Materials, Inc.Thermally annealed, low defect density single crystal silicon
US6432197Aug 14, 2001Aug 13, 2002Memc Electronic Materials, Inc.Process for the preparation of non-oxygen precipitating Czochralski silicon wafers
US6537368Aug 13, 2001Mar 25, 2003Memc Electronic Materials SpaIdeal oxygen precipitating epitaxial silicon wafers and oxygen out-diffusion-less process therefor
US6537655May 16, 2001Mar 25, 2003Memc Electronic Materials, Inc.Epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof
US6555194Nov 2, 2000Apr 29, 2003Memc Electronic Materials, Inc.Process for producing low defect density, ideal oxygen precipitating silicon
US6579779Nov 2, 2000Jun 17, 2003Memc Electronic Materials, Inc.Process for the preparation of an ideal oxygen precipitating silicon wafer having an asymmetrical vacancy concentration profile capable of forming an enhanced denuded zone
US6586068Nov 2, 2000Jul 1, 2003Memc Electronic Materials, Inc.Ideal oxygen precipitating silicon wafer having an asymmetrical vacancy concentration profile and a process for the preparation thereof
US6599815Jun 30, 2000Jul 29, 2003Memc Electronic Materials, Inc.Method and apparatus for forming a silicon wafer with a denuded zone
US6635587Sep 14, 2000Oct 21, 2003Memc Electronic Materials, Inc.Method for producing czochralski silicon free of agglomerated self-interstitial defects
US6666915Mar 19, 2003Dec 23, 2003Memc Electronic Materials, Inc.Method for the preparation of an epitaxial silicon wafer with intrinsic gettering
US6686260Feb 4, 2002Feb 3, 2004Memc Electronics Materials, Inc.Process for producing thermally annealed wafers having improved internal gettering
US6709511Aug 13, 2002Mar 23, 2004Memc Electronic Materials, Inc.Process for suppressing oxygen precipitation in vacancy dominated silicon
US6713370Jun 13, 2003Mar 30, 2004Memc Electronic Materials, Inc.Process for the preparation of an ideal oxygen precipitating silicon wafer capable of forming an enhanced denuded zone
US6743289Feb 11, 2002Jun 1, 2004Memc Electronic Materials, Inc.Thermal annealing process for producing low defect density single crystal silicon
US6828690Aug 4, 1999Dec 7, 2004Memc Electronic Materials, Inc.Non-uniform minority carrier lifetime distributions in high performance silicon power devices
US6849119May 6, 2003Feb 1, 2005Memc Electronic Materials, Inc.Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6849901Jan 3, 2002Feb 1, 2005Memc Electronic Materials, Inc.Device layer of a silicon-on-insulator structure having vacancy dominated and substantially free of agglomerated vacancy-type defects
US6896728Feb 25, 2003May 24, 2005Memc Electronic Materials, Inc.Process for producing low defect density, ideal oxygen precipitating silicon
US6955718Jul 8, 2003Oct 18, 2005Memc Electronic Materials, Inc.Process for preparing a stabilized ideal oxygen precipitating silicon wafer
US6958092Mar 25, 2003Oct 25, 2005Memc Electronic Materials, Inc.Epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof
US7135351Mar 17, 2005Nov 14, 2006Memc Electronic Materials, Inc.Method for controlling of thermal donor formation in high resistivity CZ silicon
US7144829 *Apr 13, 2004Dec 5, 2006Matsushita Electric Industrial Co., Ltd.Method for fabricating semiconductor device and semiconductor substrate
US7229693Feb 16, 2005Jun 12, 2007Memc Electronic Materials, Inc.Low defect density, ideal oxygen precipitating silicon
US7242037Aug 5, 2004Jul 10, 2007Memc Electronic Materials, Inc.Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices
US7442253May 24, 2007Oct 28, 2008Memc Electronic Materials, Inc.Process for forming low defect density, ideal oxygen precipitating silicon
US7485928Nov 9, 2005Feb 3, 2009Memc Electronic Materials, Inc.Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US7618879Jun 14, 2007Nov 17, 2009Memc Electronics Materials, Inc.Non-uniform minority carrier lifetime distributions in high performance silicon power devices
US7732352 *Jun 20, 2007Jun 8, 2010Hynix Semiconductor Inc.Silicon wafers and method of fabricating the same
US8026145Dec 31, 2008Sep 27, 2011Memc Electronic Materials, Inc.Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US8466043 *Mar 16, 2012Jun 18, 2013Zhejiang UniversityProcess of internal gettering for Czochralski silicon wafer
US20130045586 *Mar 16, 2012Feb 21, 2013Zhejiang UniversityProcess Of Internal Gettering For Czochralski Silicon Wafer
DE10227141B4 *Jun 18, 2002Nov 29, 2012Samsung Electronics Co., Ltd.Verfahren zur Herstellung eines Siliziumwafers mit einer denudierten Zone und damit hergestellter Siliziumwafer
EP0844654A2 *Nov 18, 1997May 27, 1998Shin-Etsu Handotai Company LimitedHeat treatment method for a silicon wafer and a silicon wafer heat-treated by the method
EP0973190A2 *Jul 6, 1999Jan 19, 2000Shin-Etsu Handotai Company LimitedSilicon wafer and method for producing it
EP1002335A1 *Feb 25, 1998May 24, 2000MEMC Electronic Materials, Inc.Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
EP1300879A2 *Feb 25, 1998Apr 9, 2003MEMC Electronic Materials, Inc.Ideal oxygen precipating silicon wafers and oxygen out-diffusion-less process therefor
EP1914796A2 *Aug 25, 1999Apr 23, 2008MEMC Electronic Materials, Inc.Process for making non-oxygen precititating Czochralski silicon wafers
EP2028682A1 *Feb 25, 1998Feb 25, 2009MEMC Electronic Materials, Inc.Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process thereof
EP2261958A2 *Aug 25, 1999Dec 15, 2010MEMC Electronic Materials, Inc.Process for making non-oxygen precipitating czochralski silicon wafers
WO1999016119A1 *Sep 2, 1998Apr 1, 1999Memc Electronic MaterialsProcess for the preparation of silicon wafers having a controlled distribution of oxygen precipitate nucleation centers
WO2000013226A1 *Aug 27, 1999Mar 9, 2000Memc Electronic MaterialsProcess for preparing an ideal oxygen precipitating silicon wafer
WO2000014776A2 *Aug 25, 1999Mar 16, 2000Memc Electronic MaterialsNon-oxygen precipitating czochralski silicon wafers
WO2002003445A1 *May 14, 2001Jan 10, 2002Memc Electronic MaterialsMethod and apparatus for forming a silicon wafer with a denuded zone
Classifications
U.S. Classification438/471, 257/E21.318, 438/795, 148/DIG.60, 257/E21.321, 148/DIG.24
International ClassificationH01L21/322
Cooperative ClassificationY10S148/06, Y10S148/024, H01L21/3221, H01L21/3225
European ClassificationH01L21/322B, H01L21/322B8
Legal Events
DateCodeEventDescription
Mar 17, 2014ASAssignment
Owner name: MEMC PASADENA, INC., TEXAS
Free format text: RELEASE OF SECURITY INTEREST TO REEL/FRAME: 012280/0161;ASSIGNOR:CITICORP USA, INC.;REEL/FRAME:032458/0794
Effective date: 20140313
Owner name: MEMC INTERNATIONAL, INC. (NOW KNOWN AS SUNEDISON I
Owner name: MEMC SOUTHWEST INC., MISSOURI
Owner name: PLASMASIL, L.L.C., MISSOURI
Owner name: MEMC ELECTRONIC MATERIALS, INC. (NOW KNOWN AS SUNE
Owner name: SIBOND, L.L.C., MISSOURI
Aug 11, 2005ASAssignment
Owner name: MEMC ELECTRONIC MATERIALS, INC., MISSOURI
Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:CITICORP USA, INC.;REEL/FRAME:016641/0045
Effective date: 20050602
Mar 19, 2003ASAssignment
Owner name: CITICORP USA, INC., DELAWARE
Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC ELECTRONIC MATERIALS, INC.;MEMC PASADENA, INC.;PLASMASIL, L.L.C.;AND OTHERS;REEL/FRAME:013964/0378;SIGNING DATES FROM 20020303 TO 20030303
Owner name: CITICORP USA, INC. 2 PENNS WAY SUITE 200NEW CASTLE
Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC ELECTRONIC MATERIALS, INC. /AR;REEL/FRAME:013964/0378;SIGNING DATES FROM 20020303 TO 20030303
Dec 28, 2001ASAssignment
Owner name: CITICORP USA, INC., DELAWARE
Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC PASADENA, INC.;PLASMASIL, L.L.C.;SIBOND, L.L.C.;AND OTHERS;REEL/FRAME:012365/0345
Effective date: 20011221
Owner name: CITICORP USA, INC. ATTENTION OF DAVID GRABAR 2 PEN
Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC PASADENA, INC. /AR;REEL/FRAME:012365/0345
Dec 27, 2001ASAssignment
Owner name: E. ON AG, GERMANY
Free format text: SECURITY INTEREST;ASSIGNOR:MEMC ELECTRONIC MATERIALS, INC.;REEL/FRAME:012407/0806
Effective date: 20011025
Owner name: E. ON AG E.ON PLATZ 1 DUSSELDORF GERMANY D-404
Owner name: E. ON AG E.ON PLATZ 1DUSSELDORF, (1)D-404 /AE
Free format text: SECURITY INTEREST;ASSIGNOR:MEMC ELECTRONIC MATERIALS, INC. /AR;REEL/FRAME:012407/0806
Nov 21, 2001ASAssignment
Owner name: CITICORP USA, INC., DELAWARE
Free format text: SECURITY INTEREST;ASSIGNORS:MEMC PASADENA, INC.;PLASMASIL, L.L.C.;SIBOND, L.L.C.;AND OTHERS;REEL/FRAME:012273/0145
Effective date: 20011113
Owner name: MEMC ELECTRONIC MATERIALS, INC., MISSOURI
Free format text: TERMINATION OF SECURITY INTEREST;ASSIGNOR:E.ON AG;REEL/FRAME:012263/0944
Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC PASADENA, INC.;PLASMASIL, L.L.C.;SIBOND, L.L.C.;AND OTHERS;REEL/FRAME:012280/0161
Owner name: CITICORP USA, INC. ATTENTION OF DAVID GRABAR 2 PEN
Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC PASADENA, INC. /AR;REEL/FRAME:012280/0161
Owner name: MEMC ELECTRONIC MATERIALS, INC. 501 PEARL DRIVE ST
Owner name: MEMC ELECTRONIC MATERIALS, INC. 501 PEARL DRIVEST.
Free format text: TERMINATION OF SECURITY INTEREST;ASSIGNOR:E.ON AG /AR;REEL/FRAME:012263/0944
Free format text: SECURITY INTEREST;ASSIGNORS:MEMC PASADENA, INC. /AR;REEL/FRAME:012273/0145
Mar 15, 2001FPAYFee payment
Year of fee payment: 12
Feb 10, 1997FPAYFee payment
Year of fee payment: 8
Jan 19, 1993FPAYFee payment
Year of fee payment: 4