|Publication number||US4879551 A|
|Application number||US 06/727,468|
|Publication date||Nov 7, 1989|
|Filing date||Apr 26, 1985|
|Priority date||Apr 26, 1985|
|Also published as||CA1266716A, CA1266716A1, DE3682699D1, EP0199601A2, EP0199601A3, EP0199601B1|
|Publication number||06727468, 727468, US 4879551 A, US 4879551A, US-A-4879551, US4879551 A, US4879551A|
|Inventors||Christos J. Georgiou, Yeong-Chang L. Lien, Kiyoshi Maruyama|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (62), Classifications (7), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Technical Field
The invention relates generally to cross-point arrays. In particular, the invention relates to the concurrent marking of the cross-points.
2. Background Art
Switching arrays or cross-point switches have long been used in the telephone industry for the switching of voice lines. More recently, crosspoint switches have found increasing use in computer systems for the selective connection of data lines from one device to another. A simple cross-point switch array 10, as shown in FIG. 1, selectively connects any one of four input lines 12 to any of four output lines 14. .he cross-point switch array 10 of FIG. 1 is called a two-sided switch because the input lines 12 have a different characteristic than the output lines 14, namely the directionality of data flow, and are located on two different sides of the cross-point switch array 10. At each intersection of an input line 12 and an output line 14 there is a cross-point 16 consisting of a switch 18 connected to those two input and output lines 12 and 14. In the illustrated switch 18, the conductivity of the switch 18 and hence the state of the cross-point 16 is determined by a control input 20. Thus the selection of the connection between the input line 12 and the output line 14 is determined by the signals on all the control inputs 20 of the cross-point array 10. The advantage of the cross-point array 10 is that the interconnections between the input lines 12 and the output lines 14 can be independently controlled. Any connection is possible. In many applications, a given input line 12 is only connected to one output line 14 at any given time. In this application, the cross-point array 10 has a data bandwidth that is the product of the bandwidth either of the lines 12 and 14 or of the cross-point 16 multiplied by the number of input lines 12 or of output lines 14. That is, each of the input lines 12 can simultaneously use the cross-point array 10 as long as the intended output line 14 is available. In another mode of operation, a single input line 12 can be simultaneously connected to more than one output line 14. This is called the broadcast mode.
Various types of cross-point switch arrays are well known in the art. In older telephone systems, the individual switches 18 were mechanical relays. More modern cross-point switches use semiconductor integrated circuits for the entire cross-point switch array 10 with the individual switches 18 being MOS transistors, the gate inputs of which are controlled by the control inputs 20. By the use of integrated circuits, the design and fabrication of the cross-point array itself has become relatively easy and inexpensive. As a further result, the size of cross-point array 10 has been greatly increased. A design for a cross-point array 10 with 1024 input lines 12 and the same number of output lines 14 now seems reasonable. However, in such a cross-point switch, the number of switches 18 reaches 1,048,576. The switches 18 are relatively simple to build but the control of such a large number of cross-points 16 presents some difficult problems. one of the difficulties is that the control of so many cross-points can impose an effective data rate limitation for the cross-point array 10. Before data can be transmitted through the crosspoint switch, the controller must set the appropriate cross-point 16. A single controller can only process one connection request at a time, such as in the system disclosed by Begeman et al in U.S. Pat. No. 4,345,251. Georgiou, one of the present inventors, has described the use of multiple controllers in U.S. patent application Ser. No. 544,653, filed Oct. 24, 1983 Pat. No. 4,630,045, incorporated herein by reference. Although the design disclosed therein is effective at increasing the speed of the cross-point controller, nonetheless, any controller takes time to respond to a request for connection. If the input line is waiting for the connection to be made in order to transmit data, then the effective data rate of the switch is reduced. This delay becomes a particular problem when the transmitted messages are relatively short so that a large number of connections need to be made.
Accordingly, it is an object of this invention to provide for the control of the cross-points of a cross-point array that does not interrupt the data flow.
Another object of this invention is to provide a high bandwidth cross-point switch.
The invention can be summarized as a cross-point switch array in which the switch at each crosspoint is controlled by a first latch. Associated with each first latch is a second latch, the state of which is determined by the cross-point controller. The contents of all second latches are concurrently transferred to the associated first latches by a single control line. Thus, the second latches can be set up for the next transmission cycle by the controller while data is continuing to flow through the cross-point switch, as determined by the first latch. The concurrent signal marks the end of a prior transmission period and the beginning of the next transmission period.
FIG. 1 is an illustration of a well-known cross-point switch array.
FIG. 2 is an illustration of the organization of the cross-point switch system of the present invention.
FIG. 3 is another and more realistic representation of the cross-point switch system of the present invention.
FIG. 4 is an illustration of the switch matrix of the system of FIG. 3.
FIG. 5 is an illustration of the control element of the switch matrix of FIG. 4.
FIG. 6 is a connection diagram of the first latch for an alternative clocked embodiment of the invention.
FIG. 7 is a logic gate representation for another embodiment of the control element.
FIG. 8 is a transistor representation for an alternative dynamic embodiment of the control element.
FIG. 9 is a timing diagram for the embodiment of FIG. 2.
The invention can be visualized, as shown in FIG. 2, as an array of memory control elements in parallel with the usual cross-point switch array. The switching plane is the cross-point array 10, of the type previously described. The individual control lines for all the individual switches 18 are connected to respective memory elements 22 arranged in another middle plane 24. The memory elements 22 store a `1` when the switch 18 that it controls is conducting or store a `0` when the controlled switch 18 is non-conducting. Each of the memory elements 22 will keep the associated switch 18 turned on for the duration of a data transmission period. Makaemuchi et al in U.S. Pat. No. 4,068,215 discloses separate latches controlling every cross-point in an array. Wahlstrom in U.S. Pat. No. 3,473,160 discloses a shift register controlling the separate elements in a cellular logic array.
The memory elements 22 are set to values indicated by associated latches 26 in another upper plane 28. The values contained in these latches 26 are individually controlled by a controller 30. In the preferred embodiment, the controller 30 sets the latches 26 one by one. Several or all of the latches 26 can be set to new values by the controller 30 before the controller 30 activates a memory latch control line 32 connected to all the memory elements 22. The activation of the memory latch control line 32 causes the contents of all the latches 26 to be concurrently transferred to the associated memory elements 22.
By the use of the structure illustrated in FIG. 2, the controller 30 can be setting the latches 26 for the configuration of the cross-point switch 10 in the next period of data transmission while data continues to be transmitted over the cross-point array 10 in the current transmission period according to the current states of the memory elements 22. A single signal on the memory latch control line 32 produces the required reconfiguration of the cross-point array 10.
Magos in U.S. Pat. No. 4,134,132 discloses a two-dimensional multi-shade video display in which each point of the two-dimensional raster has an analog storage element. The video signal is deserialized into a one-dimensional array of analog storage elements. The contents of the one-dimensional array are supplied in parallel to the storage elements in a selected row of the two-dimensional raster.
The multi-plane structure of FIG. 2, although conceptually simple, is difficult to implement in semiconductor technology and also neglects much important detail in a switching system.
A more realistic structure is shown in FIG. 3. Each of the input lines 12 are connected to a switch matrix 34 through a switch adaptor 36. The switch adaptors 36 are used to separate control information from data in the signal train received on the input lines 12. The data is routed through the switch matrix 34 while the control information is sent to a switch controller 38.
The switch controller 38 controls the switch matrix 34 by five sets of signals. The multi-bit XX and YY signals are addresses for the desired cross-point in the switch matrix 34. For instance, the XX address could be the numerical designation of the input line 12 associated with the cross-point while the YY address could be the numerical designation of the associated output line 14. The remaining signals are the data signal DATA, the load latch signal LL and the load mark signal LM, to be described later.
Further details of the switching matrix are shown in FIG. 4. An decoder 40 receives the XX address and, based upon its value, selects one of four rows in, an array of control elements 42 by an active X signal on a respective row line 43. Similarly, a Y decoder 44 receives the YY address and selects one of four columns in the array of control elements 42 by an active Y signal on a respective column line 45. The data signal DATA, the load latch signal LL and the load mark signal LM are identically connected to all the control elements 42.
The control element 42 is shown in more detail in FIG. 5. The X and Y signals on the row line 43 from the X decoder 40 and on the column line 45 from the Y decoder 44, respectively, depending on in which row and column of the array the control element 42 is located, are used as inputs to an AND gate 46. Thus, only when the XX and the YY signals indicate that this particular control element 42 is selected, resulting in high X and Y signals, does the output of the AND gate 46 assume a high value. The AND gate output is used as an enable input EN into a first latch 48. The data input D of the first latch 48 is connected to the data signal DATA. The load latch signal LL is connected to the clock input of the first latch 48. Whenever the output of the AND gate 46 is high, indicating that this control element 42 is being addressed, the value of the data signal DATA is latched into the first latch 48 on the upward transition of the load latch signal LL.
In order to load a setting into the first latch 48, the controller 38 sets the data signal DATA to the desired value and sets the XX and YY address signals that selects the particular control element 42 by high X and Y signals. Then the load latch signal LL clocks in the data signal DATA only into the selected control element 42.
The output Q of the first latch 48 is connected to the data input D of a second latch 50. The latch control or clock input of the second latch 50 is controlled by the load mark signal LM. Whenever the load mark signal LM transitions high, the value in the first latch 48 is latched into the second latch 50. There is no address selection for the latching of the second latch 50 so that all control elements 42 simultaneously undergo this same latching although for the different values held in the respective first latches 48. The output Q of the second latch is connected to the control input 20 of the individual switch 18 that is associated with that particular control element 42. Thus the value in the second latch 50 controls whether the individual switch 18 is conducting or non-conducting, that is, whether the cross-point 16 is connected or disconnected. The first latch 48 corresponds to the latches 26 in the upper plane 28, shown in FIG. 2, while the second latch 50 corresponds to the memories 22 in the middle plane 24.
The control element 42 in FIG. 5 is for an unclocked system that relies upon the load latch signal LL for the exact latching time. A clocked configuration for the first latch 48 is shown in FIG. 6 in which a system clock CLOCK is connected to the clock input of the first latch 48. The output of an AND gate 47 receiving the X and Y signals and the load latch signal LL, is connected to the enable input EN of the first latch 48. Prior to the upward transition of the clock signal CLOCK, the load latch signal LL is set and the X and Y signals select the particular first latch 48. Then when the clock signal CLOCK makes its upward transition, the data signal DATA is latched into the first latch 48. A similar configuration can be used for the second latch 50 with the clock signal CLOCK connected to the clock input and the load mark signal LM connected to the enable input.
A logic gate level implementation of the first and second latches 48 and 50 is shown in FIG. 7 that corresponds to the unclocked control element 42 of FIG. 5. The inputs and outputs remain the same. An inverter 51 provides a complementary version of the data signal DATA. Two NAND gates 52 and 54 combine, the select signal from the AND gate 46 with the true and complemented versions respectively of the data signal DATA. The outputs of the NAND gates 52 and 54 are fed respectively to two more NAND gates 56 and 58 connected in a cross-coupled configuration. Whenever the AND gate 47 is selected by the X and Y signals and enabled by the load latch signal LL, the cross-coupled NAND gates 56 and 58 are latched to the value of the data signal DATA. The outputs -Q and Q of these two cross-coupled NAND gates 56 and 58 are the outputs of the first latch 48 and are led to respective NAND gates 60 and 62 in the second latch 50. Both of the NAND gates 60 and 62 also receive the load mark signal LM which acts to gate in the outputs -Q and Q of the first latch 48. The outputs of the NAND gates 60 and 62 are led to two more cross-coupled NAND gates 64 and 66, acting as a latch. The output of the NAND gate 66, corresponding to the true output Q of the first latch 48, is connected to the control line 20 controlling the individual switch 18.
Yet another implementation for the control element 42 is shown at the transistor level at FIG. 8. This is a dynamic system requiring coordination of the control signals, as shown in the timing diagram of FIG. 9. If the represented control element 42 is selected by the XX and YY address signals, the high load latch signal LL causes an AND gate 70 receiving the X, Y and LL signals to go high, thus rendering conductive a transistor 72. The conductive transistor 72 then passes the data signal DATA to an internal line 74 controlling the gate of a first latch transistor 76. A first load transistor 78 is connected in series with the first latch transistor 78 between the power supply and ground. A high signal on the internal line 74 produces a low signal on a first latch output line 80 connected between the first latch transistor 76 and the first load transistor 78. Similarly, a low signal on the internal line 74 produces a high signal on the first latch output line 80. The internal line 74 and the gate of the first latch transistor 76 have a substantial capacitance. Therefore, this capacitance will hold whatever data signal DATA has been impressed thereupon even after the load latch transistor 72 has been turned off. Nonetheless, this capacitance is leaky and cannot be used for a storage time longer than a time Δt. In a similar manner, several first latches 48 can be loaded with different data signals DATA by the sequencing of the address signals XX and YY within the maximum time Δt.
Subsequently, the load mark signal LM is applied to the gate of a load mark transistor 82 that then passes the signal latched on the first latch output line 80 to a second latch transistor 84 and a second load transistor 86, similar to the first latch and load transistors 76 and 78. The control input 20 of the cross-point switch 18 is connected between the second latch transistor 2 and the second load transistor 86 and carries a signal CROSS-POINT. The upward transition of the load mark signal LM marks all cross-points concurrently and the marking is maintained even after the removal of the load mark signal LM. However, because of the dynamic nature of the second latch 50, no more than the maximum storage time Δt should pass between successive markings of all cross-points.
It is believed that the invention is particularly useful in the situation in which occasionally one device broadcasts short messages to several other devices. The regular data flow can continue through the cross-point array while the controller is setting up the future connections for the broadcast. Then, upon issuance of the load mark signal LM, all the required connections are immediately made. Thus the regular data flow is not interrupted by the necessity to set multiple cross-points for the broadcast.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US2707591 *||May 7, 1952||May 3, 1955||Hughes Aircraft Co||Multiple-stable-state storage devices|
|US4068215 *||Jun 15, 1976||Jan 10, 1978||Hitachi, Ltd.||Cross-point switch matrix and multistage switching network using the same|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5361373 *||Dec 11, 1992||Nov 1, 1994||Gilson Kent L||Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor|
|US5751710 *||Jun 11, 1996||May 12, 1998||Cisco Technology, Inc.||Technique for connecting cards of a distributed network switch|
|US5793978 *||Dec 29, 1994||Aug 11, 1998||Cisco Technology, Inc.||System for routing packets by separating packets in to broadcast packets and non-broadcast packets and allocating a selected communication bandwidth to the broadcast packets|
|US5867666 *||Aug 5, 1997||Feb 2, 1999||Cisco Systems, Inc.||Virtual interfaces with dynamic binding|
|US6035105 *||Jan 2, 1996||Mar 7, 2000||Cisco Technology, Inc.||Multiple VLAN architecture system|
|US6078590 *||Jul 14, 1997||Jun 20, 2000||Cisco Technology, Inc.||Hierarchical routing knowledge for multicast packet routing|
|US6091725 *||Dec 29, 1995||Jul 18, 2000||Cisco Systems, Inc.||Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network|
|US6097718 *||Jan 2, 1996||Aug 1, 2000||Cisco Technology, Inc.||Snapshot routing with route aging|
|US6101115 *||Aug 7, 1998||Aug 8, 2000||Cisco Technology, Inc.||CAM match line precharge|
|US6111877 *||Dec 31, 1997||Aug 29, 2000||Cisco Technology, Inc.||Load sharing across flows|
|US6122272 *||May 23, 1997||Sep 19, 2000||Cisco Technology, Inc.||Call size feedback on PNNI operation|
|US6157641 *||Aug 22, 1997||Dec 5, 2000||Cisco Technology, Inc.||Multiprotocol packet recognition and switching|
|US6160420||Nov 12, 1996||Dec 12, 2000||Actel Corporation||Programmable interconnect architecture|
|US6182147||Jul 31, 1998||Jan 30, 2001||Cisco Technology, Inc.||Multicast group routing using unidirectional links|
|US6182224||Jan 2, 1996||Jan 30, 2001||Cisco Systems, Inc.||Enhanced network services using a subnetwork of communicating processors|
|US6212182||Jun 27, 1996||Apr 3, 2001||Cisco Technology, Inc.||Combined unicast and multicast scheduling|
|US6212183||Aug 22, 1997||Apr 3, 2001||Cisco Technology, Inc.||Multiple parallel packet routing lookup|
|US6219699||Mar 26, 1999||Apr 17, 2001||Cisco Technologies, Inc.||Multiple VLAN Architecture system|
|US6240084||Oct 10, 1996||May 29, 2001||Cisco Systems, Inc.||Telephony-enabled network processing device with separate TDM bus and host system backplane bus|
|US6243667||May 28, 1996||Jun 5, 2001||Cisco Systems, Inc.||Network flow switching and flow data export|
|US6304546||Dec 19, 1996||Oct 16, 2001||Cisco Technology, Inc.||End-to-end bidirectional keep-alive using virtual circuits|
|US6308148||Dec 20, 1996||Oct 23, 2001||Cisco Technology, Inc.||Network flow data export|
|US6308219||Jul 31, 1998||Oct 23, 2001||Cisco Technology, Inc.||Routing table lookup implemented using M-trie having nodes duplicated in multiple memory banks|
|US6327251||May 3, 2000||Dec 4, 2001||Cisco Technology, Inc.||Snapshot routing|
|US6330599||Oct 16, 1998||Dec 11, 2001||Cisco Technology, Inc.||Virtual interfaces with dynamic binding|
|US6343072||Dec 31, 1997||Jan 29, 2002||Cisco Technology, Inc.||Single-chip architecture for shared-memory router|
|US6356530||May 23, 1997||Mar 12, 2002||Cisco Technology, Inc.||Next hop selection in ATM networks|
|US6370121||Jun 29, 1998||Apr 9, 2002||Cisco Technology, Inc.||Method and system for shortcut trunking of LAN bridges|
|US6377577||Jun 30, 1998||Apr 23, 2002||Cisco Technology, Inc.||Access control list processing in hardware|
|US6389506||Aug 7, 1998||May 14, 2002||Cisco Technology, Inc.||Block mask ternary cam|
|US6434120||Aug 25, 1998||Aug 13, 2002||Cisco Technology, Inc.||Autosensing LMI protocols in frame relay networks|
|US6512766||Aug 22, 1997||Jan 28, 2003||Cisco Systems, Inc.||Enhanced internet packet routing lookup|
|US6538988||Jan 18, 2001||Mar 25, 2003||Cisco Technology, Inc.||End-to-end bidirectional keep-alive using virtual circuits|
|US6603765||Jul 21, 2000||Aug 5, 2003||Cisco Technology, Inc.||Load sharing across flows|
|US6603772||Mar 31, 1999||Aug 5, 2003||Cisco Technology, Inc.||Multicast routing with multicast virtual output queues and shortest queue first allocation|
|US6611528||Oct 10, 2000||Aug 26, 2003||Cisco Technology, Inc.||Hierarchical routing knowledge for multicast packet routing|
|US6640243||Dec 14, 2000||Oct 28, 2003||Cisco Technology, Inc.||Enhanced network services using a subnetwork of communicating processors|
|US6757791||Mar 30, 1999||Jun 29, 2004||Cisco Technology, Inc.||Method and apparatus for reordering packet data units in storage queues for reading and writing memory|
|US6760331||Mar 31, 1999||Jul 6, 2004||Cisco Technology, Inc.||Multicast routing with nearest queue first allocation and dynamic and static vector quantization|
|US6771642||Jan 8, 1999||Aug 3, 2004||Cisco Technology, Inc.||Method and apparatus for scheduling packets in a packet switch|
|US6798776||Jan 14, 2000||Sep 28, 2004||Cisco Technology, Inc.||Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network|
|US6831923||Apr 17, 2000||Dec 14, 2004||Cisco Technology, Inc.||Pipelined multiple issue packet switch|
|US6853638||Apr 1, 1998||Feb 8, 2005||Cisco Technology, Inc.||Route/service processor scalability via flow-based distribution of traffic|
|US6889181||Jul 2, 1997||May 3, 2005||Cisco Technology, Inc.||Network flow switching and flow data export|
|US6904037||Nov 5, 1996||Jun 7, 2005||Cisco Technology, Inc.||Asymmetric implementation of DSVD for voice/data internet access|
|US6917966||Sep 19, 2003||Jul 12, 2005||Cisco Technology, Inc.||Enhanced network services using a subnetwork of communicating processors|
|US6920112||Jun 29, 1998||Jul 19, 2005||Cisco Technology, Inc.||Sampling packets for network monitoring|
|US7065762||Mar 22, 1999||Jun 20, 2006||Cisco Technology, Inc.||Method, apparatus and computer program product for borrowed-virtual-time scheduling|
|US7076543||Feb 13, 2002||Jul 11, 2006||Cisco Technology, Inc.||Method and apparatus for collecting, aggregating and monitoring network management information|
|US7103007||Jun 27, 2002||Sep 5, 2006||Cisco Technology, Inc.||Autosensing LMI protocols in frame relay networks|
|US7116669||May 9, 2001||Oct 3, 2006||Cisco Technology, Inc.||Format for automatic generation of unique ATM addresses used for PNNI|
|US7246148||May 19, 2005||Jul 17, 2007||Cisco Technology, Inc.||Enhanced network services using a subnetwork of communicating processors|
|US7260518||Aug 23, 2004||Aug 21, 2007||Cisco Technology, Inc.||Network flow switching and flow data report|
|US7286525||Jun 21, 2002||Oct 23, 2007||Cisco Technology, Inc.||Synchronous pipelined switch using serial transmission|
|US7318094||May 16, 2006||Jan 8, 2008||Cisco Technology, Inc.||Apparatus, system and device for collecting, aggregating and monitoring network management information|
|US7443858||Dec 2, 2003||Oct 28, 2008||Cisco Technology, Inc.||Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network|
|US7475156||Mar 21, 2001||Jan 6, 2009||Cisco Technology, Inc.||Network flow switching and flow data export|
|US7570583||Feb 15, 2005||Aug 4, 2009||Cisco Technology, Inc.||Extending SONET/SDH automatic protection switching|
|US8401027||Sep 25, 2008||Mar 19, 2013||Cisco Technology, Inc.|
|US8514637||Jul 13, 2009||Aug 20, 2013||Seagate Technology Llc||Systems and methods of cell selection in three-dimensional cross-point array memory devices|
|US20110007538 *||Jul 13, 2009||Jan 13, 2011||Seagate Technology Llc||Systems and methods of cell selection in cross-point array memory devices|
|WO2007002598A3 *||Jun 23, 2006||Apr 19, 2007||Celleration Inc||Removable applicator nozzle for ultrasound wound therapy device|
|U.S. Classification||340/2.29, 327/404, 326/44|
|International Classification||H04Q3/52, H03K17/693|
|Apr 26, 1985||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:GEORGIOU, CHRISTOS J.;LIEN, YEONG-CHANG LUKE;MARUYAMA, KIYOSHI;REEL/FRAME:004399/0123
Effective date: 19850426
|Mar 25, 1993||FPAY||Fee payment|
Year of fee payment: 4
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|Jan 8, 2001||FPAY||Fee payment|
Year of fee payment: 12