|Publication number||US4893030 A|
|Application number||US 07/233,847|
|Publication date||Jan 9, 1990|
|Filing date||Aug 16, 1988|
|Priority date||Dec 4, 1986|
|Publication number||07233847, 233847, US 4893030 A, US 4893030A, US-A-4893030, US4893030 A, US4893030A|
|Inventors||Gerald W. Shearer, Karl M. J. Lofgren, Kenneth W. Ouyang|
|Original Assignee||Western Digital Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Non-Patent Citations (2), Referenced by (46), Classifications (10), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of copending application Ser. No. 937,983 filed on Dec. 4, 1986, now abandoned.
1. Field of the Invention
The present invention relates generally to the problem of manufacturing integrated circuits having consistent operating characteristics from one manufacturing batch to the next. More specifically, it relates to the problem of manufacturing precise currents in individual ones of a plurality of bulk fabricated integrated circuits.
2. Description of the Prior Art
Complex electronic circuits may be manufactured in bulk volume at low cost using known integrated circuit fabrication techniques. In these techniques, n-type and p-type conductivity regions are formed one next to the other in a semiconductor substrate such as the substrate 100 shown in FIG. 1. Any alternating arrangement of three or more such regions (PNP or NPN) may be used to create various transistor devices. The P and N regions are typically created by diffusing various impurities (doping agents) through a top surface of the substrate. Top surface dimensions (width and length) of the regions can be controlled to precise tolerances using known photolithographic methods. In cost-effective production techniques it is difficult to keep the depth of the regions within precise tolerances due to process variations (i.e., changes in furnace temperature and impurity concentration levels). This means that transistors from one process batch cannot be guaranteed to be identical to those of another batch.
Within a single batch, wafer, or IC (integrated circuit) chip however, the depth of similar regions will remain generally consistent because integrally formed regions are fabricated under almost identical process conditions. Identical or nearly-identical transistors, resistors, etc. can be formed on individual IC chips. The identical nature of such devices may be exploited to form precision voltage dividers and current splitters. Voltage and/or current magnitudes produced by such precision dividers (or splitters) are precise only in a relative sense. They remain consistently determinable from one manufacturing batch to the next, relative to other voltage or current levels developed internally on the IC chip but not to absolute levels developed outside the chip. Disparities among the absolute output magnitudes of voltages and currents generated by IC's from different fabrication batches create an undesirable situation in which it is difficult to obtain consistent operating characteristics from bulk-produced IC systems.
In FIG. 1, three active devices (transistors) labeled Q1, Q2, and Q3 are shown in sectional perspective with a top layer 110, comprised of metal contacts and insulated gates, exploded away from the top surface of the substrate 100 to reveal a plurality of P and N regions forming the active devices, Q1, Q2, and Q3. The first and second devices, Q1 and Q2, comprise a sequence of nearly-identical NPN regions. The third device, Q3, is fabricated of a dissimilar sequence of PNP regions. Active devices such as NPN bipolar transistors, n-channel FETs (field effect transistors), and the like can be manufactured using the NPN sequences of Q1 and Q2. Complementary (dissimilar) active devices such as PNP bipolar transistors, p-channel FET's and the like may be fabricated from the PNP sequence of regions forming Q3. In FIG. 1, the first and second active devices, Q1 and Q2, are shown to be formed as metal-oxide-semiconductor field-effect-transistors (MOSFETs) having respective source, gate and drain terminal portions S1, G1, D1, S2, G2, and D2. The terminal portions are contained within the exploded upper layer 110. It is to be assumed that the dissimilar device, Q3, has a respective source terminal S3, gate terminal G3 and drain terminal D3 associated with its PNP regions (not shown in FIG. 1).
The n-type regions of the nearly-identical (twin) first and second devices, Q1 and Q2, are formed with an identical diffusion depth Df1. Each of the twin devices has associated therewith a channel length L (distance between source and drain regions) and a channel width W. The width/length dimensions may be formed within precise tolerances as previously mentioned, using known photolithographic techniques. When the respective widths, W1 and W2, and the respective lengths, L1 and L2, of two twin devices such as Q1 and Q2 are identical, the twin devices will be referred to herein as identical twins. Identical twins possess identical electrical characteristics. That is, if identical output voltages, VDS1 and VDS2 are developed across the drain and source terminals of two identical-twin devices and equal gate voltages VGS1, VGS2 are applied at their gate terminals, then substantially identical currents, IDS1 and IDS2 will flow through the output terminals (drain and source terminals) of such devices. This happens because the operating temperatures and fabrication process variables affecting the operating characteristics of two such devices on the same chip are substantially equal. If all factors except the channel widths and channel lengths of two twin devices remain identical, the output currents of the two twin devices will be proportional replicas of one another where the proportionality factor (scaling multipler) is determined by the top view dimensions of the respective devices.
The p-type regions of the third device, Q3 (PNP) diffuse to a depth Df3, below the substrate surface, that in general is effectively different from the depth Df1 of the NPN regions such that it becomes difficult to ascertain any precise relationship between the operating characteristics of Q3 and those of the twin devices, Q1 and Q2. This presents a problem when complementary devices such as the n-channel FET, Q2 and p-channel FET, Q3 are to be used in conjunction (e.g., CMOS circuits) to drive an output element that requires precise drive currents.
FIG. 2 is a graph of typical device operating characteristics showing the relationship between an output current ID of a generic active device Q (FIG. 4) and output and bias voltages, VD and VB, across the device. The magnitude of the output current ID is a function of not only the applied voltages, VD and VB, but also of other factors such as the operating temperature, fabrication process variables, and the dimensions of various p-type and n-type regions.
FIG. 3 shows a number of schematic symbols typically used to represent dissimilar active devices. Devices such as an n-channel FET and an NPN bipolar transistor may be formed from regions having an NPN arrangement. Devices such as a p-channel FET and a PNP bipolar transistor may be fabricated at substrate areas having a PNP sequence of regions. Such active devices are represented by the generic circular symbol shown in FIG. 4.
FIG. 4 is a schematic diagram showing one of many possible applications wherein the absolute magnitude of an output current ID from an active device Q may be of importance. The active device Q is illustrated generically as having a current-controlling gate terminal G, a first output terminal O1 and a second output terminal O2. A bias level VB is applied to the gate terminal G for a time duration t through a switch SW. The output terminals, O1 and O2, are placed in series between a voltage source Vcc and a charge accumulating (integrating) capacitor C. When the switch SW is closed for the time duration t, an output current ID of a specific magnitude is pumped into the integrating capacitor C from the active device Q. An integrated voltage VC develops across the capacitor C as a result of the total charge stored therein. The voltage change VC resulting from the charge pumped into the capacitor by the output current ID is proportional to a product of the absolute value of the output current magnitude ID and the application time duration t. It may be expressed formally as:
where C is the value of the capacitor expressed in farads. The voltage VC across the charge integrating capacitor C is often used to trigger timing circuits in electronic systems. For applications where the timing must be very precise, it is desirable that the magnitude of the device output current ID be predictable within precise tolerances. It is difficult however to assure that the output current ID of each current controlling device Q in every one of a large number of integrated circuit chips (IC's) will be within a desirable set of tolerances. Magnitude determinitive factors such as the operating temperature of each individual IC and fabrication process variables affecting the operating characteristics of each active device on a chip have to be accounted for.
It is an object of the present invention to maintain an output current of an active device on an integrated circuit within a precise set of tolerances. It is another object of the present invention to provide a cost effective means for assuring the precision of an output current produced by an active device when the device is part of an integrated circuit chip (IC) which is manufactured in bulk volume.
The above objectives are realized in accordance with the present invention by providing a biasing circuit which includes an exemplary active device on an integrated circuit that is connected in series with a current reference element. The exemplary device has a gate terminal to which a current-controlling bias may be applied and a pair of output terminals from which a gate-controlled output current flows. At least one operating device that is nearly-identical to the exemplary device is provided on the integrated circuit in a manner such that the operating characteristics of the two devices are nearly-identical irrespective of operating temperature and fabrication process variables. The exemplary device and current reference element are arranged such that the magnitude of an output current flow through the exemplary device is precisely determinable from (e.g. substantially equal to) the current flow through the current reference element. The output voltage across the exemplary device is forced to a desired voltage by means of a gate controller. The gate controller senses the output voltage of the exemplary device, compares the sensed output voltage to the desired voltage and applies a biasing level to the gate of the exemplary device to drive the output voltage of the exemplary device toward the desired voltage. The biasing level applied to the gate of the exemplary device is duplicated at the gate of the nearly-identical operating device. The output current of the operating device will be precisely determinable from the current flow through the current reference element when the output voltage across the operating device is equal to the output voltage of the exemplary device (which in turn is equal to or almost equal to the desired voltage).
Cost effective tolerance control is realized by fabricating the current reference element separately from the active devices of the IC.
FIG. 1 is a perspective view of portions of an integrated circuit with a top layer exploded away.
FIG. 2 is a graph showing a typical relationship between the output current of an active device and the applied bias and output voltages of such a device.
FIG. 3 illustrates schematic symbols used to represent various active devices.
FIG. 4 is a schematic diagram of a typical timing circuit.
FIG. 5 is a schematic diagram of a phase locking system to which the present invention may be applied.
FIG. 6 illustrates a first biasing circuit in accordance with the present invention.
FIG. 7 is a schematic diagram of an integrated circuit chip into which a second embodiment of the present invention is incorporated.
FIG. 8 is a schematic diagram of a third embodiment.
FIG. 9 is a schematic diagram of a fourth embodiment.
FIG. 10 is a diagram of a self-reflecting amplifier.
The present invention provides a cost-effective technique for controlling the magnitude of an output current that is produced as an output of an active device in an integrated circuit. The benefits derived from the ability to precisely control the magnitude of the output current of one or more active devices on an integrated circuit chip are too numerous to be discussed generally herein. FIG. 5 is a schematic diagram of a specific phase-locking system 500 for which the present invention was developed. The phase-locking system 500 generates a CLOCK signal which is intended to be phase matched with an incoming asynchronous DATA signal. The DATA signal could be derived for example, from a rotating floppy disc of a computer. In the phase-locking system 500, the DATA signal is applied to a clock input of a first flip flop 510. The phase-locking system 500 includes a voltage controlled oscillator (VCO) 550 which outputs a CLOCK signal having a predetermined frequency. The CLOCK signal is applied to a second flip-flop 520. Rising edges of the CLOCK signal cause a frequency-decrementing output, FDN of the second flip-flop 520 to go high for a short period of time t3 -t2 . Rising edges of the DATA signal cause a frequency-incrementing output FUP of the first flip-flop 510 to go high for a short duration t3 -t1. The frequency incrementing/decrementing signals, FUP and FDN, pass through a set of time delay gates, 515 and 525, to reset the outputs of the flip-flops 510, 520 at a mutual time t3. If a rising edge of the DATA signal arrives at the first flip-flop 510 before a corresponding edge of the CLOCK signal arrives at the second flip-flop 520, the duration t3 -t1 of the FUP signal will be greater than the duration t3 -t2 of the FDN signal. Conversely, if the CLOCK signal edge arrives before a corresponding edge of the DATA signal, the duration t3 -t2 of the FDN signal will be greater. The FUP signal activates a p-channel FET 530 which supplies a first current (source current) I1 to an error integrating capacitor CI. The FDN signal activates an n-channel FET 540 which withdraws a second current (sink current) I2 from the error integrating capacitor CI. The integrating capacitor CI is coupled to an input of the VCO 550 to apply an input voltage Vin thereat. The input voltage Vin of the VCO 550 is altered in accordance with the formula:
ΔVin =I1.(t3 -t1)-I2.(t3 -t2)
When the CLOCK signal is precisely in phase with the DATA signal, the input voltage Vin of the VCO 550 should preferably remain constant. An accumulating error will be introduced into the locking operation of the phase-locking system 500 if the source and sink currents, I1 and I2, are not precisely the same in magnitude when t1 =t2.
As discussed earlier, the absolute magnitudes of the respective output currents, I1 and I2, of the p-channel FET 530 and its complementary n-channel FET 540 can be affected by numerous factors including the bias voltages applied at the gate terminals of each device, the output voltages developed across the output terminals of the devices, the temperature at which the circuit is operated, and fabrication process variables. The last two factors are the least predictable and most difficult to control. Fortunately, within any single chip, temperature and process variation factors are constant for nearly-identical active devices. This concept is exploited by the present invention to produce equivalent or scaled replicas of a reference current Io flowing through a reference element in nearly-identical active devices of an IC chip. Moreover, precision replicas of the reference current can also be reproduced in dissimilar devices of the IC chip in accordance with the present invention.
Referring back to FIG. 1, it can be said that the NPN devices, Q1 and Q2 are almost identical twins but for their difference in top view dimensions (W1 /L1 ≠W2 /L2). If the width/length dimensions are made equal, then Q1 and Q2 could be considered identical twins with respect to their electrical operating characteristics. That is, when the same output voltage occurs across their respective output terminals (VDS1 =VDS2) and the same bias voltage is applied at their gate terminals (VGS1 =VGS2) then their output currents will be of identical magnitude (IDS1 =IDS2). Even when the width/length dimensions of the twin devices, Q1 and Q2, are different; a porportional current relationship IDS2 =(W2 /L2).(L1 /W1).IDS1 remains generally true when the bias and output voltages of the devices are equal.
FIG. 6 is a schematic diagram of a first biasing circuit 600 in accordance with the present invention. Q1 and Q2 are "twin" active devices formed on a common semiconductor substrate (IC chip) 602. Q1 is referred to herein as an exemplary active device because its operating characteristics are repeated consistently throughout the integrated circuit chip in similar "twin" devices such as Q2. Q2 is referred to as an operating device. The output terminals of the exemplary device Q1 are placed in series with a current reference element 610 such that the magnitude of an output current I1 flowing through the output terminals of the exemplary device Q1 will be precisely predictable, independent of temperature and process variations, once a reference current Io through the reference element 610 is known. In the illustrated biasing circuit 600, the output current I1 of the exemplary device Q1 is substantially equal to the reference current I0 flowing through the current reference element 610 by virtue of Kirchhoff's current law. Little or no current flows into an input terminal 620 of a differential amplifier U1 that is coupled to one of the output terminals of the exemplary device Q1. A desired voltage VDD is produced by a voltage source 650. The voltage source 650 is preferably a precision voltage divider which is formed integrally on the IC chip 602 and connected between ground and a supply voltage Vcc of the chip. In one variation, the voltage source 650 could include a direct coupling (indicated by the chained line in FIG. 6) to the output voltage VD2 of the operating device Q2. The output voltage VD1 of the exemplary device Q1 is forced equal to the desired voltage VDD by means of the difference amplifier U1. The difference amplifier U1 has a pair of voltage sensing inputs, one of which (620) is tied to an output terminal of the exemplary device Q1 and the other of which (640) is connected to the desired voltage VDD produced by the voltage source 650. The output of the difference amplifier U1 is coupled to a gate terminal G1 of the exemplary device Q1. The difference amplifier U1 produces a gate biasing level VB1 at the gate terminal G1 of the exemplary device. The exemplary device Q1 and the difference amplifier U1 together form a voltage-mirroring feedback loop which forces the output voltage VD1 of the exemplary device to be substantially equal to the desired voltage VDD. Since the output current I1 of the exemplary device Q1 is known to be substantially equal to the reference current I0, and the output voltage VD1 is known to be substantially equal to the desired voltage VDD, it can be stated that the gate biasing level VG2 required for replicating the current I1 in a nearly-identical device (Q2) will be substantially equal to the developed biasing level VB1 at the gate terminal G1 of the exemplary device Q1. If this same biasing level VB1 is duplicated at a second gate terminal G2 of the "twin" active device Q2 when the output voltage VD2 across the twin device Q2 is equal to the desired voltage VDD, then the output current I2 through the twin device will be known to be I2 =(W2 /L2).(L1 /W1).I1. In other words, the output current I2 will be a scaled replica of the exemplary device current I1 and the precision of I1 will be duplicated in I2 (even if the magnitude of I2 is scaled up or down by a precisely determinable proportionality factor). As mentioned, the desired voltage VDD can be made equal to the output voltage VD2 of the twin device Q2 simply by connecting the appropriate input terminal 640 of the difference amplifier U1 to an output terminal 660 of the twin device Q2 (as indicated by the chained line in FIG. 6). In the illustrated embodiment 600 however, it will be noted that the input terminal 640 is connected instead to a precision voltage divider which produces the desired voltage VDD. In some circuits it is not necessary to have a precise operating current output I2 except at a particular voltage state wherein the output voltage VD2 of the twin device Q2 is equal to a predetermined (desired) voltage VDD. In FIG. 5 for example, the steady state input voltage Vin of the VCO 550 (after lock-in of the CLOCK and DATA phases) is often set equal to one-half of the supply voltage Vcc. This means that the steady state output voltages of the p-channel FET 530 and n-channel FET 540 will also be equal to one-half of the supply voltage Vcc. Consequently, if the biasing circuit 600 of FIG. 6 is used to produce at least one of the gate biasing voltages, VG1 and V.sub. G2, for the FETs 530 and 540 shown in FIG. 5, the desired voltage VDD can be set equal to one-half of the supply voltage Vcc by means of a precision voltage divider 650 without need for direct connections between the input terminal 640 of the difference amplifier U1 and the drain terminals D1 and D2 of the FETs 530 and 540. It should be appreciated, that aside from eliminating a direct connection from the input terminal 640 to the output terminal 660 of the twin operating device Q2 shown in FIG. 6, there is the added benefit that the input lead 640 of the difference amplifier U1 may be made very short by locating the voltage divider 650 close to the difference amplifier U1 so the danger of undesirable noise coupling into the input terminal 640 is minimized.
The difference amplifier U1, exemplary device Q1 and precision voltage source 650 are preferably formed together on the integrated circuit chip near a peripheral edge of the semiconductor substrate 602. The current reference element 610 is preferably an external precision resistor that is connected to the biasing circuit 600 through a substrate connection pad 615. An opposed end of the external precision resistor 610 may be connected to a voltage supply (Vcc) pad 605 of the integrated circuit. The reference current I0 through the precision resistor 610 can then be calculated to be I0 =(Vcc -VDD)/Rex, where Rex is the resistance of the external precision resistor 610.
Numerous variations will present themselves once the concept of FIG. 6 is understood. If the twin operating device Q2 is operating in saturation (FIG. 2) then the magnitude of its output current I2 will be generally insensitive to small variations in the output voltage VD2 across the output terminals of Q2. The exemplary device Q1 will be operating at a corresponding saturation point (same constant bias level VGS =VB1) of its characteristic curve (FIG. 2). Small differences between the output voltage VD1 of the exemplary device and the output voltage VD2 of the operating device will create minor differences between the precision of the output currents flowing through each device. If these minor differences are acceptable for a particular circuit, there is no need to assure that VD1 and VD2 are precisely matched. The output current I2 of the exemplary device will be approximately equal to or a scaled replica of the output current I1 through the exemplary device.
FIG. 7 shows an integrated circuit chip 700 in which an exemplary n-channel FET Q1 and a twin n-channel FET Q2 are operated at or near such an output-voltage insensitive saturation region of their respective characteristic curves. An external current reference element 610 having a precisely known resistance Rex is connected to internal components of the chip 700 through a first substrate contact pad 615. The output current I1 through the exemplary device Q1 will be substantially equal to the current I0 passing through the current reference 610 by virtue of Kirchhoff's current law. The output voltage VD1 across Q1 is coupled through an electrostatic input protection pad 618 to a first input 620 of a difference amplifier U1. The difference amplifier U1 senses the voltage VD1 and compares it with a desired voltage VDD (which in this case is set equal to 1.7 V) and outputs a biasing level VB1 to a gate terminal G1 of the exemplary device Q1 to drive the output voltage VD1 of Q1 toward the desired voltage VDD. An integrated circuit capacitor C1 is connected to the gate G1 of Q1 to inhibit undesirable oscillation. The biasing level VB1 is also coupled to a second gate G2 of a twin operating device Q2. The twin device Q2 will be operating along the same bias curve VGS =VB1 as the exemplary device Q1. Since generally speaking, the output current ID (FIG. 2) of an active device changes very little relative to output voltage VD at or near saturation, the output current I2 through Q2 will be determinable, within specifiable tolerances, to be approximately equal to or to be approximately a scaled replica of the output current I1 flowing through the exemplary device Q1. The exemplary device Q1 has a width/length dimension of 104/3 in the illustrated IC 700. The twin n-channel device Q2 has a dimension of 16/3. Accordingly, the current through the twin device Q2 will be approximately I2 =I1 /6.5.
A p-channel FET Q3 is connected in series with the n-channel twin device Q2 in FIG. 7. Although Q3 is dissimilar to Q2 and Q1, its output current I3 is forced to be substantially equal to the output current I2 of Q2 by virtue of Kirchhoff's current law. The gate voltage VG3 of Q3 is self-adjusted to conform with its output current I3 by typing the gate terminal G3 to the drain terminal D3. The same gate voltage, VG3 is applied to the gate of a half-sized p-channel device Q4. The current through Q4, which is I4 =I2 /2, is reflected into an output n-channel FET Q5 through a difference amplifier U701. When the difference amplifier U701 is balanced, that is, when the input voltage Vin coupled to one of its inputs 702 through an input pad 720 and an electrostatic protection pad 718, is equal to an internally provided reference voltage V.sub. REF =2.5 V then the current I4 supplied by the p-channel device Q4 is split symmetrically through mirror image symmetrical halves of U701. Half of the current I4 flows through an n-channel device 707 at the right side of U701 and the other half flows through a second n-channel device 705 at the left side of the amplifier U701. The gate of the right side n-channel device 707 is tied to its own drain so the voltage thereat VG5 ' self adjusts for the current I4 /2. The self adjusted gate voltage VG5 ' is applied to the gate of the opposing left n-channel FET 705. The gate of the n-channel output FET Q5 is cross coupled to the drain of the left side n-channel FET 705 to create a mirror gate voltage VG5 thereat such that the output current IADJ through Q5 is determinable on the basis of device geometry (width/length dimensions). A current adjusting pad 725 is connected to the drain of Q5. The pad 725 may be connected for example, to a current/voltage feedback system 730 which changes the input voltage Vin according to the magnitude of the output current IADJ. (Vin is a function of IADJ ; Vin =f(IADJ).) One example of such a current/voltage converting system 730 is the earlier described charge integrating capacitor C1 as shown in FIGS. 4 and 5. When the input voltage Vin at pad 720 rises above VREF =2.5V, less current will flow through the right side (FET 707) of the amplifier U701 and more current will be reflected into the left side FET 705. The drain voltage VG5 ' of the right side n-channel FET 707 will drop as a result. The mirror voltage VG5 across the left-side FET 705 will consequently rise causing an increase in the current IADJ through Q5. Conversely, when Vin drops below 2.5 V, the current IADJ through Q5 will decrease through an opposing sequence of events. At Vin =2.5 V, the output current through Q5 will be IADJ =(40/10).(3/16).I4 /2 because VG5 '=VG5 and the current through the right FET 707 is mirrored into the output FET Q5. This current may be used to precisely control the voltage of a charge accumulating capacitor such as CI of FIGS. 4 and 5.
A two legged embodiment 800 is shown in FIG. 8. A dissimilar active device Q3 is placed in series with the twin Q2 of the exemplary device Q1. An open circle is indicated at the gate G3 of the third active device Q3 to indicate that it is not a twin of the other two active devices, Q1 and Q2. Since Q3 is in series with Q2, its output current I3 will be substantially equal to the output current I2 of the second device Q2. A difference amplifier U3 is connected to the gate G3 of the dissimilar device Q3 to drive the output voltage VD2 of Q2 equal to a desired device VDD. Since the output voltage VD2 of Q2 is known to be equal to the output voltage VD1 of the exemplary device Q1, the output current I2 of the twin device Q2 will be scaled replica (I.sub. 2 =W2 /L2.L1 /W1.I1) of the output current I1 of Q1 regardless of whether Q1 and Q2 are in saturation or operating at an unsaturated level where output current is sensitive to output voltage variations. The output voltage VD3 of the dissimilar device Q3 will be known since the voltages Vcc and VD2 are also known. The bias voltage VB3 developed at the gate G3 of the dissimilar device Q3 is precisely the voltage necessary for driving twins of Q3 to produce scaled replicas of the current I3 when the respective output voltages of Q3 's twins are equal to VD3. The desired voltage VDD is preferably made exactly one-half Vcc so that VD2 =VD3.
Referring to both FIG. 5 and FIG. 8, it will be apparent that in a case where Q3 is a twin of the p-channel FET 530 and Q2 is a twin of the n-channel FET 540, then the respective gate voltages VB3 and VB1 developed at the gates of Q3 and Q2, may be used to bias the gates of the complementary FETs 530 and 540 of FIG. 5 (by setting VG1 =VB3 and VG2 =VB1). In such a case, the sink and source currents provided by the complementary FETs, 530 and 540, in the phase-locking system 500 will be identical when Vin =VDD. The output of the charge integrating capacitor CI will remain at this voltage Vin =VDD once the CLOCK signal is locked into phase with the DATA signal because the source current will be substantially identical to the sink current.
Referring to FIG. 8 alone, it will be noted that the right leg L2 of the two legged embodiment 800 is merely an upside-down version of the left leg L1 with the twin active device Q2 substituted for the current reference element 610. It will be understood that the arrangement can be repeated to produce biasing voltages for additional devices on the integrated circuit chip that are dissimilar both to Q1 and Q3. Although mentioned briefly earlier, it should also be understood that the difference amplifiers U1 and U3 are formed with relatively high input impedences so that the series current relations I1 =Io and I3 =I2 in respective legs, L1 and L2, will be substantially unaffected by the input impedances of amplifiers U1 and U3.
In FIG. 9, a second twin device Q4 is controllably connected in parallel with Q2 by means of a gain switch to increase the output current I3 of the dissimilar device Q3. When the gain switch is closed, the output VB3 of the difference amplifier U3 changes to accommodate the increased device current I3. This increase is reflected into a third leg L3 of the circuit shown in FIG. 9. A new biasing signal VB6 is generated by a feedback loop comprised of a third difference amplifier U6 and an active device Q6. VB6 and VB3 are respectively fed into the gates of twin devices Q8 (n-channel) and Q7 (p-channel) to produce matched sink and source currents, I6, and I5'. The system gain may be switched from a low gain mode to a high gain mode simply by activating the gain switch to increase the output currents of devices Q7 and Q8. I5 ' and I6 ' will remain precisely matched in either mode.
Referring to FIGS. 6, 8 and 9, it will be noted that the purpose of the difference amplifiers U1, U3 and U6 is to drive an output voltage VD of an active device such that the output VD will be substantially equal to a desired voltage VDD. FIG. 10 shows a special amplifier U* which is devised for this purpose. The special amplifier U* is referred to herein as a self-reflecting amplifier. The self-reflecting amplifier U* comprises a current reference leg L10 through which a first current I10 is controllably passed preferably using the concept of the above disclosed precision biasing circuit. Namely, a biasing voltage VB1 is applied to an n-channel device Q10 in the reference leg L10 to establish the magnitude of the first current I10. The same current I10 flows through two p-channel devices, Q11 and Q12 in the reference leg L10. The gate of Q11 is tied to a desired voltage VDD. The gate of Q12 is connected to the drain of Q.sub. 10 to produce a self-adjusting gate voltage VBP that is necessary for allowing the current I10 to pass through Q12. The self-adjusted gate voltage VBP is brought to another p-channel device Q22 that is shared by two symmetrical legs, L20 and L30, of the difference amplifier U*. For simplicity of explanation, it will be assumed that Q22 is double dimensioned so a current I22 equal to twice the magnitude of I10 passes through the uppermost device Q22. The current I22 splits into two streams I20 and I30 each equal to I10. The two streams I20 and I30 pass through the symmetrical leg portions L20, L30 of the amplifier U8. Symmetry occurs because a p-channel FET Q21 in the left leg L20 is a mirror of a right-side twin device Q31 and a lower left-side n-channel FET Q20 is a mirror of a right-side lower device Q30. Each of the symmetrical legs, L20 and L30, (Q22 is shared by both legs) is a mirror image of the first leg L10 that is; Q22 is a twin of Q12 ; Q11 is a twin of Q21 and Q31 ; and Q10 is a twin of Q20, Q30. Any imbalance between the gate voltages of Q21 and Q31 will result in a counter-balancing adjustment of the current streams I20 and I30. A current-controlling active device Q40 is cross-coupled to the gate of Q31 and the drain of Q20. It is to be noted that Q40 is a twin of Q10, Q20 and Q30. The drain of Q40 may be coupled to Q31 through a feedback system 730 which produces a voltage Vin =f(I40 ) at the gate of Q31 or may be connected directly (dotted line) to the gate of Q31 in which case the voltage Vin at the gate of Q31 will be equal to the output voltage VD40 of the current-controlling device Q40. If the gate voltage Vin of Q31 shifts to be less than the gate voltage VDD of Q21, more current will flow through the right-side device Q31. A corresponding decrease in the current stream I20 through the complementary left symmetrical leg L20 will result. The increased right-side current flow of I30 will force the drain voltage of Q30 upward. A corresponding downward shift will take place in the drain voltage VG40 of Q20. This downward shift of VG40 is coupled to the gate of Q40 resulting in less current flow through Q40. The drain of Q40 is coupled to the gate of Q3, in such a manner that Vin will rise (in the case of Vin >VDD) to match VDD. The reverse situation will occur if Vin is greater than VDD.
In the case where the drain of Q40 is connected directly to the gate of Q31, the output voltage VD40 of the current-controlling device Q40 will be urged equal to the gate voltage VDD of Q21. The gate voltage VG40 of Q40 will be substantially equal to the gate voltage VG30 of Q30 when U* is in the balanced condition. Since the right symmetrical leg L30 is almost a mirror image of the reference leg L10 in this condition (VG30 will be nearly identical to VB1) the current I30 through Q30 will be a close replica of the current I10 through the reference leg L10. I30 is reflected into Q40 by the principle of current mirroring so I40 will be a close replica of I10 as well.
Referring to FIG. 7 it can be seen that a similar principle is used in the amplifier U701 of the chip 700. U* differs from U701 in the fact that the desired voltage VDD is replicated in the reference leg L10 while U701 operates with a 1.7 V voltage forced across Q1. The advantage of the U* amplifier (FIG. 10) is that not only does each mirror-image symmetrical leg L20, L30 force a balancing of Vin to VDD but that the precision current I10 through the leg L10 is replicated with better precision through Q40 because Q40 is mirror-image wise symmetrical with Q10, Q20 and Q30 while Q22 is mirror-image wise symmetrical with Q12 and moreover Q21, Q31 are mirror-image wise symmetrical with Q11. This causes the current mirroring of I10 into the right leg L30 to be more precise. That is, the circuit of FIG. 10 does not have to rely on Q22 being in a "saturation" state for its current precision, it can rely on the fact that Q22 is mirror-image wise symmetrical with Q12 (the output voltage of Q12 is "reflected " across Q22) so VBP will cause I22 to be a scaled replica of I10. When VD40 is balanced with VDD, the load current ILOAD =I40 through Q40 will be in a scaled replica of the reference current I10. The self-reflecting amplifier U* can be substituted for amplifiers U3 and U6 in FIG. 9. A conventional difference amplifier is preferably used for U1 to generate the voltage VB1 which controls the current I10 in the first leg L10 of the self-reflecting amplifier U*.
While a number of variations have been described above, many additional embodiments will become apparent to those skilled in the art once the spirit of the present invention is understood. Accordingly, the scope of the present invention is not limited merely to the specific embodiments described above but rather defined by the appended claims and equivalents thereof.
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|U.S. Classification||327/530, 327/565, 327/561, 323/315|
|International Classification||G05F1/46, H03L7/089|
|Cooperative Classification||G05F1/462, H03L7/0895|
|European Classification||G05F1/46B, H03L7/089C4|
|Apr 30, 1991||CC||Certificate of correction|
|Jul 9, 1993||FPAY||Fee payment|
Year of fee payment: 4
|Feb 25, 1997||FPAY||Fee payment|
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|Sep 28, 2000||AS||Assignment|
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|Jun 29, 2001||AS||Assignment|
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