|Publication number||US4916519 A|
|Application number||US 07/358,992|
|Publication date||Apr 10, 1990|
|Filing date||May 30, 1989|
|Priority date||May 30, 1989|
|Also published as||CA1300761C, EP0400324A2, EP0400324A3|
|Publication number||07358992, 358992, US 4916519 A, US 4916519A, US-A-4916519, US4916519 A, US4916519A|
|Inventors||William C. Ward|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (4), Referenced by (55), Classifications (31), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to packaged wire bonded semiconductor chips. More particularly, it relates to a wire bonded chip in which none of the wires used to make electrical contact between the lead frame and the chip terminals cross one another, thus eliminating a possible defect mechanism.
2. Description of the Prior Art
Wire bonding techniques have long been employed to position and affix leads to semiconductor chips prior to encapsulation of the chip in a protective coating.
Such techniques generally employ a lead frame to which the semiconductor chip is attached prior to encapsulation. Gold wires are used to connect terminals on the surface of the semiconductor chip to corresponding lead frame conductors.
In general, the initial design is such that these wires are kept within specified lengths. Good practice dictates that the length of the wires should be minimized and not exceed 100 times the diameter of the wire. However, when new chip designs are created in order, for example, to stack the chips in a denser package or to replace prior existing chips, the new designs often require one or more new terminal locations while the outside circuit or machine requirements demand that the external lead frame conductors remain in the same position. In such a case, extremely long wires which can cross several such other wires might be considered. If such long wires are used, as these long wires pass from the conductors of the lead frame to the respective terminal on the chip surface, undesirable effects can occur especially during the subsequent encapsulation step. For example, during the encapsulation steps there exists a strong likelihood that any such long wire will deform and short to one or more of the wires it is crossing. The possibility of such shorting, during the encapsulation process, increases with both the length of the crossing wire and the number of wires over which it crosses.
It is the object of this invention to provide a packaged semiconductor chip with improved mechanical, and electrical performance.
Another object of the invention is to provide a semiconductor chip package in which lead frame conductors can be easily and safely connected to a number of different chip terminals, thereby permitting the use of the same external lead frame configuration with different semiconductor chips.
It is yet another object of the present invention to provide a semiconductor package with enhanced reliability.
These and other objects of the present invention are provided in an encapsulated semiconductor module in which a semiconductor chip, having a major surface with terminals thereon, is deposed within the encapsulating material, a plurality of self-supporting, unitary, discrete, and continuous lead frame conductors formed of metal sheet stock are positioned at various locations around the chip and cantilevered out of the encapsulating material, so that discrete wires can be used to connect respective ones of said conductors to respective ones of said terminals. In the present invention excessively long bonding wires are avoided by connecting a selected one of said lead frame conductors to a parallel conductor by a jumper wire and connecting the parallel conductor to the desired terminal with a short wire.
These and other objects, features, and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention as illustrated in the accompanying drawings.
FIG. 1, is a schematic representation of a wire bonded encapsulated semiconductor chip. Part of the encapsulation material has been broken away to expose the lead frame conductors, the semiconductor chip, the chip terminals, and the wires used to connect the conductors to the chip terminals.
FIG. 2, shows the chip in FIG. 1 with one long wire that has been rerouted because of design changes in the terminal locations on the chip surface.
FIG. 3, shows the redesigned chip of FIG. 2 in which one embodiment of the present invention is used to avoid the hazards of the long wire shown in FIG. 2.
A semiconductor package 12 containing a semiconductor chip 14 in which part of the encapsulation is removed is shown in FIG. 1. The chip 14 supports a multi-conductor lead frame 15 whose leads or conductors 18 are electrically connected to respective terminals 17 on the surface of the semiconductor chip 14 by bonding wires 16.
During encapsulation in material 19, the conductors 18 are supported as a unit by the lead frame bar 20 shown in phantom in FIG. 1. After the encapsulation material is hardened, this lead frame bar 20 is removed.
The term "lead frame", as used herein, has a definite meaning in the semiconductor art. The material, thickness, strength, etc. of such lead frames has long been specified and known to the art, such that the use of the term "lead frame" is all that is necessary to purchase such items. In essence, the term "lead frame", means a metal structure, preferably a spot plated copper alloy, formed from sheet stock and a sufficient size and strength to meet specific mechanical strength requirements. For example, such a lead frame is discussed in the Semiconductor International, April, 1985. In the present invention the lead frame is typically between 0.005 and 0.015 inches thick and comprised of a number of fingers or conductors between 0.008 and 0.017 inches wide. These conductors are thus of a sufficient mechanical strength to be successfully handled and inserted into sockets or assembled and soldered to printed circuit boards.
As shown in FIG. 1, the interior portions of the lead frame conductors 18 extend over the semiconductor chip 14 but are separated from the semiconductor chip surface by an interposer 22 that can also serve both as an insulator and/or as an alpha particle barrier.
When it is desired that this interposer 22 be also an alpha particle barrier, then it should be comprised of a polymeric film having thermal stability at temperatures of 175 degrees C. and not contain an ionizable species such as halides and active metals, including sodium, potassium, and phosphorus. Polyimide films are suitable for such use as alpha barriers. One such polyimide film is sold under the trade name Kapton. Desirably, such Kapton films should be between 1.0 and 2.0 mils in thickness and may be thermally enhanced by alumina or silicon nitride.
The interposer layer 22 can also be solely an adhesive layer, so long as it is electrically insulating. In use, such an adhesive layer is applied to the lead frame conductors or the top active surface of chip 14; i.e., the major upper surface of the chip which contains the chip terminals 17. To absolutely assure there is no possibility of short circuit to the chip, in spite of the fact that the chips are coated with this passivating insulating adhesive, it is preferable to further use a dielectric interposer positioned between the lead frame conductors and the chip. When such an interposer is used, the adhesive layer should be applied to both surfaces of the interposer with suitable adhesive materials. Adhesives which are suitable for use for attaching the lead frame conductors to the semiconductor chip or to such a dielectric interposer can be selected from the group of epoxies, acrylics, and polyimides containing phenolics, such as polyimide-butyral:phenolic.
Once the lead frame 15 has been suitably secured to the surface of the chip, wires 16 are bonded to the tips of selected lead frame conductors 18 and bonded to selected chip terminals 17. Each wire extends from the tip of a selected lead frame conductor to a selected chip terminal. Once the desired wire bonds are in place, as shown in FIG. 1, the device is encapsulated in a suitable plastic material using well known packaging techniques. Following encapsulation of the assembly, the lead frame bar 20, which supports the leads and which is required during encapsulation, is removed. This lead frame bar is originally provided to connect the conductors 18, of the lead frame 15, so as to impart rigidity to the lead frame 15 and to limit flow of the encapsulating material. Because the lead frame bar 20 has been removed, it is shown in the figure in phantom.
Following this removal of the lead frame bar 20, those portions of the lead frame conductors 18, which extend beyond the encapsulation 19, may be formed as required.
As previously noted, respective terminals 17 are connected to respective conductors 18 by wires 16. The configuration of the lead frame conductors 18 is preferably such that the length of the wires 17 is maintained at a length of less than about 80 mils. Minimizing the length of these wires 17 not only improves the electrical performance of the packaged semiconductor chip, but further imparts a greater rigidity to the wires reducing the possibility of breakage or shorting of the wires to other elements in the package.
Since, it is preferable to maintain these wires at the shortest possible length, the initial semiconductor chip design and lead frame design is usually done so as to assure such wires are as short as possible and within the 80 mil length. In the structure shown in FIG. 1, the wires 16 are maintained in this short configuration by arranging the bulk of the terminal pads 17 in a central row. This arrangement not only reduces the impedance of the chip itself by reducing conducting channel lengths within the chip, but also reduces time delays, signal noise, and etc.
When the chip design shown in FIG. 1, for some reason or other, cannot be compactly designed or must be redesigned, for example to make the chip meet different requirements or to assure different speeds or to correct errors made in the design, it is sometimes necessary to relocate a particular chip terminal pad. Thus, for example, as shown in FIG. 1, lead frame conductor 18a is bonded via wire 16a to a nearby terminal 17a. For purposes of illustration only, it will be assumed that the terminal 17a will have to be eliminated and functionally relocated because of a chip redesign.
FIG. 2 shows for example, the prior art method of accommodating this design change. In FIG. 2 there is shown the same structure as shown in FIG. 1 except that the terminal 17a has been eliminated and the conductor 18a is now connected to a distant, newly created terminal 17d via an excessively long wire 24, which crosses the wire 16b, connected between conductor 18b and pad 17b, and wire 16c connected between conductor 18c and pad 17c. Because the wire 24 is quite long and crosses over, or is immediately adjacent to, these two additional wires; namely, wires 16a and 16b, any distortion of this wire 24, during encapsulation, can cause the wire 24 to bend or deform such that it can contact and short out either or both of the crossed wires 16a or 16b, thus causing a failure in the packaged chip. It is desirable that this is avoided.
FIG. 3 shows the present invention in which this long wire 24 has been completely eliminated and with its elimination, the defect mechanisms described above. In this FIG. 3, parallel conductors 18a and 18d are each provided with a respective T-like extension or jutty, 30 and 31. These jutties 30 and 31 extend toward one another and toward an intermediate conductor 18b. A distinctive short jumper wire 32 spans conductor 18b and connects the two jutties 30 and 31 while a separate and distinct short wire 33 connects lead 18d to the newly created chip terminal 17d. To assure that conductor 18d does not contact any exterior unit and that only lead 18a will supply information via wires 32 and 33 to the newly created terminal 17d, the end of conductor 18d can be excised during removal of the cross member 20 after encapsulation.
Thus these extended jutties and unused leads, together with the short wires 32 and 33, replace the long undesirable wire 24 shown in FIG. 2. This design now provides a method as to how the length of relocated wires can now be controlled. The present invention therefore teaches that the lead frame conductors can be redesigned in such a way that wire bonds can be significantly reduced in length and the bridging of an excessive number of other conductors can be eliminated.
It should be obvious that each such extended jutty need only be of a size to accommodate the bonding of a wire thereto and need not extend any significant distance toward any other jutty. Also, such jutties can be placed at any convenient place on the lead frame conductor.
While the normal features of this invention have been described in terms of a preferred embodiment, in particular applications it will be appreciated that various omissions, and substitutions may be made by those skilled in the art without departing from the spirit of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3842492 *||Dec 2, 1971||Oct 22, 1974||Philips Corp||Method of providing conductor leads for a semiconductor body|
|US4264917 *||Aug 24, 1979||Apr 28, 1981||Compagnie Internationale Pour L'informatique Cii-Honeywell Bull||Flat package for integrated circuit devices|
|US4417392 *||Oct 19, 1981||Nov 29, 1983||Cts Corporation||Process of making multi-layer ceramic package|
|US4532538 *||Feb 8, 1982||Jul 30, 1985||Siemens Aktiengesellschaft||Semiconductor arrangement with connector conductors cut out of sheetmetal|
|US4771330 *||May 13, 1987||Sep 13, 1988||Lsi Logic Corporation||Wire bonds and electrical contacts of an integrated circuit device|
|US4800419 *||Jan 28, 1987||Jan 24, 1989||Lsi Logic Corporation||Support assembly for integrated circuits|
|US4801997 *||Apr 19, 1988||Jan 31, 1989||Fujitsu Limited||High packing density lead frame and integrated circuit|
|US4812896 *||Nov 13, 1986||Mar 14, 1989||Olin Corporation||Metal electronic package sealed with thermoplastic having a grafted metal deactivator and antioxidant|
|US4818895 *||Nov 13, 1987||Apr 4, 1989||Kaufman Lance R||Direct current sense lead|
|US4821148 *||Jun 4, 1986||Apr 11, 1989||Hitachi, Ltd.||Resin packaged semiconductor device having a protective layer made of a metal-organic matter compound|
|US4843036 *||Jun 29, 1987||Jun 27, 1989||Eastman Kodak Company||Method for encapsulating electronic devices|
|1||*||Co pending application, Ser. No. 161,319, filed Feb. 19, 1988.|
|2||Co-pending application, Ser. No. 161,319, filed Feb. 19, 1988.|
|3||*||Supplement to Electronic News, 8 15 75.|
|4||Supplement to Electronic News, 8-15-75.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4965654 *||Oct 30, 1989||Oct 23, 1990||International Business Machines Corporation||Semiconductor package with ground plane|
|US5070390 *||May 31, 1990||Dec 3, 1991||Shinko Electric Industries Co., Ltd.||Semiconductor device using a tape carrier|
|US5115298 *||Jan 26, 1990||May 19, 1992||Texas Instruments Incorporated||Packaged integrated circuit with encapsulated electronic devices|
|US5164815 *||Jul 15, 1991||Nov 17, 1992||Texas Instruments Incorporated||Integrated circuit device and method to prevent cracking during surface mount|
|US5200364 *||Jan 21, 1992||Apr 6, 1993||Texas Instruments Incorporated||Packaged integrated circuit with encapsulated electronic devices|
|US5206536 *||Jan 23, 1991||Apr 27, 1993||Texas Instruments, Incorporated||Comb insert for semiconductor packaged devices|
|US5227232 *||Jan 23, 1991||Jul 13, 1993||Lim Thiam B||Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution|
|US5227661 *||Sep 24, 1990||Jul 13, 1993||Texas Instruments Incorporated||Integrated circuit device having an aminopropyltriethoxysilane coating|
|US5229329 *||Aug 21, 1992||Jul 20, 1993||Texas Instruments, Incorporated||Method of manufacturing insulated lead frame for integrated circuits|
|US5229639 *||Oct 31, 1991||Jul 20, 1993||International Business Machines Corporation||Low powder distribution inductance lead frame for semiconductor chips|
|US5250840 *||Jan 19, 1993||Oct 5, 1993||Samsung Electronics Co., Ltd.||Semiconductor lead frame with a chip having bonding pads in a cross arrangement|
|US5252853 *||Sep 14, 1992||Oct 12, 1993||Mitsubishi Denki Kabushiki Kaisha||Packaged semiconductor device having tab tape and particular power distribution lead structure|
|US5293065 *||Aug 27, 1992||Mar 8, 1994||Texas Instruments, Incorporated||Lead frame having an outlet with a larger cross sectional area than the inlet|
|US5304842 *||Jun 26, 1992||Apr 19, 1994||Micron Technology, Inc.||Dissimilar adhesive die attach for semiconductor devices|
|US5313102 *||Dec 22, 1989||May 17, 1994||Texas Instruments Incorporated||Integrated circuit device having a polyimide moisture barrier coating|
|US5334802 *||Jun 30, 1993||Aug 2, 1994||Texas Instruments Incorporated||Method and configuration for reducing electrical noise in integrated circuit devices|
|US5357139 *||Sep 8, 1993||Oct 18, 1994||Hitachi, Ltd.||Plastic encapsulated semiconductor device and lead frame|
|US5381036 *||Aug 16, 1993||Jan 10, 1995||Motorola, Inc.||Lead-on chip semiconductor device having peripheral bond pads|
|US5432380 *||Jun 9, 1994||Jul 11, 1995||Samsung Electronics Co., Ltd.||Apparatus for tape-mounting a semiconductor device|
|US5434106 *||Feb 16, 1994||Jul 18, 1995||Texas Instruments Incorporated||Integrated circuit device and method to prevent cracking during surface mount|
|US5442233 *||Dec 10, 1992||Aug 15, 1995||Hitachi, Ltd.||Packaged semiconductor device and a lead frame therefor, having a common potential lead with lead portions having dual functions of chip support and heat dissipation|
|US5455200 *||Jul 27, 1993||Oct 3, 1995||Motorola, Inc.||Method for making a lead-on-chip semiconductor device having peripheral bond pads|
|US5529474 *||Mar 1, 1995||Jun 25, 1996||Texas Instruments Incorporated||System for preheating a molding compound|
|US5567655 *||Jun 5, 1995||Oct 22, 1996||Lsi Logic Corporation||Method for forming interior bond pads having zig-zag linear arrangement|
|US5633206 *||Nov 14, 1995||May 27, 1997||Samsung Electronics Co., Ltd.||Process for manufacturing lead frame for semiconductor package|
|US5648299 *||Jun 4, 1996||Jul 15, 1997||Hitachi, Ltd.||Packaged semiconductor device and a leadframe therefor|
|US5661082 *||Jan 20, 1995||Aug 26, 1997||Motorola, Inc.||Process for forming a semiconductor device having a bond pad|
|US5684328 *||Jul 22, 1996||Nov 4, 1997||Samsung Electronics Co., Ltd.||Semiconductor chip package using improved tape mounting|
|US5684330 *||Nov 30, 1995||Nov 4, 1997||Samsung Electronics Co., Ltd.||Chip-sized package having metal circuit substrate|
|US5696033 *||Aug 16, 1995||Dec 9, 1997||Micron Technology, Inc.||Method for packaging a semiconductor die|
|US5789803 *||Apr 15, 1997||Aug 4, 1998||Micron Technology, Inc.||Semiconductor package|
|US5814893 *||Feb 13, 1997||Sep 29, 1998||Motorola Inc.||Semiconductor device having a bond pad|
|US5821613 *||Aug 28, 1997||Oct 13, 1998||Fujitsu Limited||Semiconductor device in which semiconductor chip has bottom surface with reduced level of organic compounds relatively to other sufaces thereof|
|US5840599 *||Oct 27, 1994||Nov 24, 1998||Texas Instruments Incorporated||Process of packaging an integrated circuit with a conductive material between a lead frame and the face of the circuit|
|US6012502 *||Jul 24, 1997||Jan 11, 2000||Micron Technology, Inc.||Apparatus for attaching adhesive tape to lead-on-chip leadframes|
|US6025212 *||Mar 2, 1998||Feb 15, 2000||Micron Technology, Inc.||Method for attaching semiconductor dice to lead-on-chip leadframes|
|US6100580 *||Oct 7, 1998||Aug 8, 2000||Hitachi, Ltd.||Semiconductor device having all outer leads extending from one side of a resin member|
|US6236107 *||Jun 7, 1995||May 22, 2001||Texas Instruments Incorporated||Encapsulate resin LOC package and method of fabrication|
|US6281044||Jul 16, 1999||Aug 28, 2001||Micron Technology, Inc.||Method and system for fabricating semiconductor components|
|US6383842||Aug 7, 1998||May 7, 2002||Fujitsu Limited||Method for producing semiconductor device having increased adhesion between package and semiconductor chip bottom|
|US6531760 *||Apr 25, 2000||Mar 11, 2003||Gen Murakami||Semiconductor device|
|US6541846||Jan 23, 2001||Apr 1, 2003||Micron Technology, Inc.||Dual LOC semiconductor assembly employing floating lead finger structure|
|US6626222||Nov 22, 2000||Sep 30, 2003||Micron Technology, Inc.||System for fabricating semiconductor components|
|US6664649||Feb 28, 2001||Dec 16, 2003||Siliconware Precision Industries Co., Ltd.||Lead-on-chip type of semiconductor package with embedded heat sink|
|US6720208||Dec 19, 2002||Apr 13, 2004||Renesas Technology Corporation||Semiconductor device|
|US6762079||Feb 25, 2002||Jul 13, 2004||Micron Technology, Inc.||Methods for fabricating dual loc semiconductor die assembly employing floating lead finger structure|
|US6919622||Feb 10, 2004||Jul 19, 2005||Renesas Technology Corp.||Semiconductor device|
|US6965157 *||Dec 16, 2003||Nov 15, 2005||Amkor Technology, Inc.||Semiconductor package with exposed die pad and body-locking leadframe|
|US7629675 *||May 3, 2006||Dec 8, 2009||Marvell International Technology Ltd.||System and method for routing signals between side-by-side die in lead frame type system in a package (SIP) devices|
|US8039318||Nov 18, 2009||Oct 18, 2011||Marvell International Technology Ltd.||System and method for routing signals between side-by-side die in lead frame type system in a package (SIP) devices|
|US20040155323 *||Feb 10, 2004||Aug 12, 2004||Gen Murakami||Semiconductor device|
|US20070257340 *||May 3, 2006||Nov 8, 2007||Briggs Randall D||System and method for routing signals between side-by-side die in lead frame type system in a package (SIP) devices|
|DE4230039A1 *||Sep 8, 1992||Apr 29, 1993||Mitsubishi Electric Corp||Semiconductor component with chip embedded in cast plastics material - has electrode protrusions at required height on coupling faces, and numerous leads|
|EP0400324A2 *||Apr 24, 1990||Dec 5, 1990||International Business Machines Corporation||Semiconductor package|
|EP0400324A3 *||Apr 24, 1990||Apr 15, 1992||International Business Machines Corporation||Semiconductor package|
|U.S. Classification||257/666, 257/786, 257/784, 257/787, 257/E23.031|
|International Classification||H01L23/50, H01L23/495|
|Cooperative Classification||H01L2924/181, H01L2224/45015, H01L2224/49, H01L2924/3011, H01L2224/4826, H01L24/45, H01L2924/01006, H01L2924/01029, H01L2924/01014, H01L23/495, H01L2224/48091, H01L2924/01079, H01L2924/19107, H01L2224/45144, H01L2924/01011, H01L2924/07802, H01L2924/01015, H01L24/49, H01L2224/48247, H01L2924/01019, H01L2924/014, H01L24/48|
|European Classification||H01L24/49, H01L23/495|
|May 30, 1989||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WARD, WILLIAM C.;REEL/FRAME:005086/0510
Effective date: 19890523
|Jul 15, 1993||FPAY||Fee payment|
Year of fee payment: 4
|Sep 2, 1997||FPAY||Fee payment|
Year of fee payment: 8
|Sep 20, 2001||FPAY||Fee payment|
Year of fee payment: 12