|Publication number||US4931406 A|
|Application number||US 07/282,138|
|Publication date||Jun 5, 1990|
|Filing date||Dec 9, 1988|
|Priority date||Dec 18, 1987|
|Also published as||EP0320977A2, EP0320977A3|
|Publication number||07282138, 282138, US 4931406 A, US 4931406A, US-A-4931406, US4931406 A, US4931406A|
|Original Assignee||Kabushiki Kaisha Toshiba|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (11), Classifications (22), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing semiconductor devices having twin wells, such as CMOS semiconductor devices and Bi-CMOS semiconductor devices.
2. Description of the Related Art
CMOS semiconductor devices and Bi-CMOS semiconductor devices have P-type and N-type wells formed in a substrate. Such semiconductor devices having two wells of different conductivity types are well known in the art as twin well type semiconductor devices.
In the twin well type semiconductor device, an embedded layer of a conductivity type opposite to that of the substrate is formed below a well of the same conductivity type as that of the substrate in order to prevent occurrence of latch-up phenomenon. For example, in a semiconductor device having a P-type substrate, an N-type embedded layer is formed below a P-type well so as to prevent occurrence of latch-up phenomenon.
In a case where the twin well type semiconductor device is formed, an embedded layer is first formed in the surface area of a substrate by a normal photolithographic technique and ion implantation process. Then, an epitaxial layer is formed on the entire surface of the semiconductor structure, and P-type and N-type wells are sequentially formed in the epitaxial layer. In this case, the P-type well is formed by use of the photolithographic technique and P-type impurity ion implantation process. Likewise, N-type well is formed by use of the photolithographic technique and N-type impurity ion implantation process.
Thus, it is necessary to repeatedly effect the photolithographic process and P-type impurity ion implantation process three times in order to form a twin well type semiconductor device. Such a complicated manufacturing method causes low manufacturing yield and high cost of semiconductor devices.
An object of this invention is to provide a method for manufacturing semiconductor devices having twin wells and an embedded layer in a simple process without repeatedly effecting the photolithographic process and ion implantation process.
According to this invention, there is provided a method for manufacturing semiconductor devices comprising the steps of forming a first layer on a semiconductor substrate of a first conductivity type; selectively removing part of the first layer to expose a predetermined portion of the substrate surface; ion-implanting impurities of a second conductivity type to introduce the impurity of the second conductivity type into the surface area of the substrate under the first layer and into a portion of the substrate deeper than the substrate surface area below the predetermined portion of the substrate surface; ion-implanting impurities of the first conductivity type to introduce the impurity of the first conductivity type into the surface areas of the first layer and the predetermined portion of the substrate; removing the first layer; and effecting heat treatment to diffuse the first and second impurities.
In the above manufacturing method, since the first and second impurities are ion-implanted with the first layer used as a common mask, only one patterning process is required to form the mask. Further, since the first impurities are introduced into different regions in different depths, the first conductivity type well and the first conductivity type embedded layer are formed by one ion-implantation process. In this way, a semiconductor device having twin wells can be formed in a simple process without repeatedly effecting the photolithographic process and ion implantation process.
FIGS. 1A to 1H are cross sectional views showing a method for manufacturing a semiconductor having twin wells according to one embodiment of this invention; and
FIG. 2 is a cross sectional view of a Bi-CMOS semiconductor device formed by the manufacturing method shown in FIG. 1A to 1H.
There will now be described a method for manufacturing semiconductor devices having twin wells according to one embodiment of this invention with reference to FIGS. 1A to 1H.
As shown in FIG. 1A, silicon oxide film (SiO2) 12 with 3 to 4 μm thickness is first formed on P-type silicon substrate 11. Then, silicon nitride film (Si3 N4) 13 with the thickness of 3000 to 5000 Å is formed on silicon oxide film 12, and resist layer 14 containing organic compound as the main component is formed to a thickness of 3 to 8 μm on silicon nitride film 13.
Next, as shown in FIG. 1B, resist film 14 is patterned by a photolithographic technique, and then an anisotropic etching process such as RIE process is effected with patterned resist film 14 used as a mask. As shown in FIG. 1C, at the end of the etching process, silicon nitride film 13 and silicon oxide film 12 are selectively removed to expose a predetermined portion of the surface of substrate 11.
Then, an N-type impurity such as phosphorus (P) is ion-implanted with block layer 15, which is formed of the remaining resist layer 14, silicon nitride film 13 and silicon oxide film 12, used as a mask in order to form N-type wells and N-type embedded layers. The acceleration voltage in the ion-implantation process is so set that phosphorus can be introduced into the surface area of substrate 11 through block layer 15 as shown by marks x in FIG. 1D and into a portion deeper than the substrate surface area in the exposed predetermined portion. In a case where three-layered block layer 15 is used as a mask as described before, it is preferable to ion-implant phosphorus by use of an acceleration voltage of 1.5 to 2.5 MeV. In this condition, it is possible to introduce phosphorus into an area near the surface area of substrate 11 under block layer 15 and into a portion deeper than the substrate surface area by approx. 9 μm under the predetermined portion. The dose amount of phosphorus at the time of the ion-implantation is preferably set to approx. 3×1012.
Next, a P-type impurity such as boron (B) is ion-implanted with block layer 15 used as a mask in order to form P-type wells. The acceleration voltage in the ion-implantation process is so set that introduction of boron into substrate 11, as shown by marks o in FIG. 1E, is prevented by block layer 15, and at the same time boron can be introduced into the substrate surface area in the exposed predetermined portion. It is preferable to ion-implant boron at an acceleration voltage of 80 to 120 KeV. In this condition, boron is not introduced into substrate 11 under block layer 15 and is introduced into substrate 11 in the predetermined portion to substantially the same depth as phosphorus doped into substrate 11 under block layer 15. The dose amount of boron at the time of the ion-implantation is preferably set to approx. 2×1012.
Then, as shown in FIG. 1F, a wet etching process is effected using a mixture of sulfuric acid solution and hydrogen peroxide solution to remove resist layer 14.
After this, as shown in FIG. 1G, silicon nitride film 13 is removed by a chemical vapor etching process, and then a wet etching process is effected using ammonium fluoride (NH4 F) solution to remove silicon oxide film 12. Further, a heat treatment is effected to diffuse phosphorus and boron which have been introduced in substrate 11. The heat treatment is effected for approx. three hours at a temperature of 1000° to 1200° C. At the end of the heat treatment, the phosphorus and boron are diffused to form N-type wells 16, P-type wells 17 and N-type embedded layers 18 as shown in FIG. 1G. In this case, the impurity concentration of N-type wells 16 and P-type wells 17 is approx. 1×1016 to 1×1017 /cm3, and the impurity concentration of N-type embedded layers 18 is approx. 1×1018 to 1×1019 /cm3.
In this way, the impurity concentration of N-type embedded layer 18 is set to be higher than that of N-type well 16. This is because phosphorus has been ion-implanted into that part of substrate 11 which corresponds to the N-type well through block layer 15 and phosphorus has been directly ion-implanted into that portion of substrate 11 which corresponds to N-type embedded layer 18. In other words, the amount of phosphorus introduced into substrate 11 under block layer 15 is reduced by the presence of block layer 15.
In general, the latch-up phenomenon can be more effectively prevented as the impurity concentration of N-type embedded layer 18 is set higher. Therefore, it is a significant advantage that N-type embedded layer 18, having a higher impurity concentration than N-type well 16, can be formed by effecting a single ion-implantation process.
Next, as shown in FIG. 1H, P-channel MOS transistors TP and PNP transistors Qp are respectively formed in N-type wells 16 and P-type wells 17 by using the normal MOS process and bipolar process which are well known in the art.
In P-channel MOS transistor Tp, P-type layers 19 and 20 act as the source and drain of transistor Tp, and metal film 22 formed on insulation film 21 which is formed on N-type well 16 acts as a gate electrode thereof. In PNP transistor Qp, P-type well 17 acts as a collector of PNP transistor Qp, and N-type layer 23 and P-type layer 24 respectively act as the base and emitter thereof.
In this embodiment, boron is ion-implanted as the P-type impurity after phosphorus of N-type impurity has been ion-implanted. However, it is also possible to ion-implant boron first and then ion-implant phosphorus. Further, it is possible to use boron fluoride (BF2) instead of boron and arsenide instead of phosphorus.
It is also possible to remove resist layer 14 prior to the ion-implantation process, and effect the ion-implantation process with the two-layered block layer of silicon oxide film 12 and silicon nitride film 13 used as a mask. However, in this case, it is necessary to make silicon nitride film 13 thicker so that the two-layered block layer may have the same ion stopper function as block layer 15 having resist layer 14.
Further, it is possible to form an N-channel MOS transistor instead of PNP transistor Qp in P-type well 17. In this case, the semiconductor device shown in FIG. 1H is modified to a CMOS semiconductor device.
FIG. 2 is a cross sectional view of a semiconductor device in which a plurality of P-type wells 17 are formed in substrate 11, and PNP transistors Qp and N-channel MOS transistors TN are selectively formed in P-type wells 17. In N-channel MOS transistor TN of FIG. 2, N-type layers 25 and 26 act as the source and drain and metal film 28 formed on insulation film 27 which is in turn formed on P-type well 17 acts as a gate electrode. The semiconductor device of FIG. 2 is a Bi-CMOS semiconductor device.
As described above, according to the manufacturing method of this invention, block layer 15 is used as a common mask for ion-implantation processes of N- and P-type impurities. Therefore, the patterning process necessary for forming the mask is effected only once. Further, N-type well 16 and high impurity N-type embedded layer 18 can be formed by a single ion-implantation process without forming an epitaxial layer. Thus, a twin well type semiconductor device can be formed by a simple manufacturing process, keeping the manufacturing cost low and enhancing the manufacturing yield.
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|U.S. Classification||438/420, 257/370, 438/234, 438/527, 257/E27.067, 257/378, 438/526, 438/208, 257/E21.644, 257/E21.696|
|International Classification||H01L29/732, H01L21/8249, H01L21/8238, H01L27/06, H01L21/331, H01L29/73, H01L27/092|
|Cooperative Classification||H01L21/8249, H01L27/0928, H01L21/823892|
|European Classification||H01L21/8238W, H01L21/8249|
|Dec 9, 1988||AS||Assignment|
Owner name: KABUSHIKI KAISHA TOSHIBA, 72 HORIKAWA-CHO, SAIWAI-
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:TOMIOKA, KAZUHIKO;REEL/FRAME:004986/0373
Effective date: 19881129
Owner name: KABUSHIKI KAISHA TOSHIBA, A CORP. OF JAPAN, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TOMIOKA, KAZUHIKO;REEL/FRAME:004986/0373
Effective date: 19881129
|Jan 11, 1994||REMI||Maintenance fee reminder mailed|
|Jun 5, 1994||LAPS||Lapse for failure to pay maintenance fees|
|Aug 16, 1994||FP||Expired due to failure to pay maintenance fee|
Effective date: 19940608