|Publication number||US4958303 A|
|Application number||US 07/193,923|
|Publication date||Sep 18, 1990|
|Filing date||May 12, 1988|
|Priority date||May 12, 1988|
|Publication number||07193923, 193923, US 4958303 A, US 4958303A, US-A-4958303, US4958303 A, US4958303A|
|Inventors||Hamid Assarpour, Lea Walton|
|Original Assignee||Digital Equipment Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (88), Classifications (8), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to exchanging pixel data among a plurality of pixel-processors in a computer graphics system.
In computer graphics an image is stored and processed electronically in a graphics processing subsystem and can be displayed on a cathode ray tube (CRT) monitor or printed at a printer. The image is often broken up into a two-dimensional array of pixels, which are the smallest addressable components of an image. A frame buffer is used to store pixel data indicating the states (e.g., color, intensity) of corresponding pixels, and the frame buffer is repeatedly accessed at a high rate (30 or 60 times per second) to display the image on the monitor. A pixel processor is used to create and process the pixel data stored in the frame buffer, and the pixel processor and frame buffer are controlled by the host computer, often in conjunction with other processors in the graphics processing subsystem.
In some graphics processing subsystems, the image is split up among a plurality of pixel-processors and associated frame buffers to speed up the processing of an image. In a parallel frame buffer architecture, the pixel array for the entire image is divided into a plurality of much smaller arrays (called cells) in which each pixel is assigned to a different pixel processor and associated frame buffer. E.g., in a 16-pixel processor arrangement having 4×4 cells, each cell is described by boundaries which occur every fourth pixel in the X-direction (from left to right of screen) and Y-direction (downward from top of screen). This permits simultaneous processing by the pixel processors when a small portion of the display is being processed at one time.
When modifying the displayed image, e.g., to move something shown in one portion of the display to another, so-called "bit-block" transfers (also referred to as "raster-ops") are used to transfer data from one frame buffer memory location (which corresponds to a particular screen location) to another. In the parallel frame buffer architecture, such bit-block transfers reguire movement of data from source pixel processors to destination pixel processors, the data being stored at the appropriate locations in the frame buffers associated with the destination pixel processors. Without such transfer between pixel processors, movements of pixel data are limited to movements along cell boundaries, e.g., every 4 pixels in the X and Y directions in a 4×4 arrangement.
One prior art method of transferring data between pixel processors involves sending the data to the host computer along a host bus and having the host computer then send the data to respective destination pixel processors. Another prior art method of transferring data between pixel processors involves providing a dedicated cache memory to receive the data being transferred from source pixel processors; the data are then forwarded to the destination processors.
In general the invention features transferring data between a plurality of pixel processors in a plural pixel-processor/associated frame buffer arrangement by using switching circuitry connected to simultaneously receive the pixel data from source pixel processors and route the pixel data to selected destination pixel processors as the data are received. The transfer of data is thus accomplished without tying up the host bus and without the need for additional dedicated external memory.
In preferred embodiments the pixel processors are arranged in rows and columns corresponding to positions of associated pixels in cells, and the switching circuitry includes two stages of multiplexers, one for column processing and one for row processing; the multiplexers are provided with different combinations of row or column rotations as inputs, and each provides a single combination as an output; the column multiplexing stage includes, for each row of pixel processors, a multiplexer receiving data from each pixel processor in the row; the row multiplexing stage includes, for each row of pixel processors, a multiplexer receiving data from each column processing multiplexer and returning data to each pixel processor in the row; and there are a plurality of serial data lines per pixel-processor and a corresponding plurality of groups of multiplexers.
Other features and advantages of the invention will be apparent from the following description of a preferred embodiment thereof and from the claims.
The preferred embodiment will now be described.
FIG. 1 is a block diagram of a computer graphics system employing a parallel frame buffer architecture.
FIG. 2 is a diagram illustrating movement of a portion of an image on a screen of the FIG. 1 system, the movement resulting in an associated transfer of a block of pixel data from one frame buffer location to another.
FIG. 3 is a block diagram showing the pixel processors of the FIG. 1 system and switching circuitry according to the invention for transferring data between the pixel processors.
FIG. 4 is a schematic of the FIG. 3 switching circuitry.
Referring to FIG. 1, graphics processing subsystem 10, host computer 12, and CRT monitor 14 of a computer graphics system are shown CRT monitor 14 includes display screen 15 for displaying the image created and processed by the computer graphics system. Graphics processing subsystem 10 includes 16 pixel processors 16A-16P (also designated PP0-PP15) and associated frame buffers 18A-18P. Pixel processors 16A-16P communicate with host computer 12 over host bus 19. Video controller 20 receives the outputs from frame buffers 18A-18P and converts the digital data to an analog signal to drive monitor 14. Not shown on FIG. 1 are other processors and data entry devices (e.g., a keyboard) used with pixel processors 16A-16P under the control of host computer 12 to provide interactive graphics processing. For a thorough discussion of the principal concepts of interactive computer graphics, reference should be made to Fundamentals of Computer Graphics, by J.D. Foley and A. Van Dam (Addison-Wesley 1982).
Referring to FIGS. 2 and 3, the graphics image is broken up into pixels 24 grouped in 4×4 cells 22, and each pixel 24 in a cell 22 is processed by a different pixel processor 16A-16P and stored in the associated frame buffer 18A-18P. Two 4×4 cells 22 are shown on display screen 15 of monitor 14 in FIG. 2; the boundaries of other cells on the screen can be obtained by horizontally extending row boundary markers 26 and vertically extending column boundary markers 28.
In FIG. 3, the pixel processors are shown in a 4×4 array corresponding to the locations of the pixel data processed by them in 4×4 cells 22 of the graphic image. Thus pixel processor 16A (also designated PPO) processes the data for the pixels in the first row and first column of every cell 22; pixel processor 16B processes the data for the pixels in the first row and second column of every cell 22, and so on. Each pixel processor 16A-16P has a serial data output line S01 connected to transfer data to switching circuit 30, a serial data output line S00 connected to transfer data to switching circuit 32, a serial data input line SI1 connected to receive data from switching circuit 30, a serial data input line SI0 connected to receive data from switching circuit 32, and two column and two row control lines used to control switching of connections between inputs and outputs of switching circuits 30, 32. Each pixel processor 16A-16P also has data, address, and control lines (not shown in FIG. 3) for communicating with host bus 19 and controlling the respective frame buffer 18A- 18P.
Referring to FIG. 4, switching circuit 30 includes two stages of multiplexers, column multiplexer stage 34 and row multiplexer stage 36. Column multiplexer stage 34 includes four 16-to-4 multiplexers 38, 40, 42, 44, each of which receives pixel data from one of the four rows of pixel processors. Row multiplexer stage 36 similarly includes four 16-to-4 multiplexers 46, 48, 50, 52, each of which returns pixel data to one of the four rows of pixel processors. The inputs to each column multiplexer 38-44 are provided in four different combinations, each one shifted in position from the preceding by one column. Thus for multiplexer 38, the four inputs from processors PP0-PP3 are provided in order (0, 1, 2, 3) in the first group, shifted by one column to the right (3, 0, 1, 2) in the second group, shifted by another column (2, 3, 0, 1) in the third group, and shifted by another column (1, 2, 3, 0) in the fourth group. The shifting is also referred to as rotations herein, because in going from one combination to the next the last column is provided as the first. Multiplexer 38 can thus output any of the four combinations provided as inputs. Each row multiplexer 46-52 receives as inputs the outputs of each of the column multiplexers 38-44. These outputs are provided in order at the first combination provided to each multiplexer 46-52 (i.e., pixel data are returned to the row from which it came), are shifted by one row at the second combination provided to each multiplexer 46-52, are shifted by two rows at the third combination provided to each multiplexer 46-52, and are shifted by three rows at the last combination provided to each multiplexer 46-52. Column multiplexers 38-44 all receive the same column control signals CA, CB (which select one of the four combinations of inputs) and thus provide the same amount of horizontal shifting for all rows of inputs. Similarly, each row multiplexer 46-52 receives the same control signals RA, RB, and thus provides the same amount of vertical shifting for each row of outputs.
In operation, graphics processing subsystem 10 and host computer 12 provide for generation and processing of a graphics image displayed on monitor 14 according to techniques known in the art, for example as described in the above-referenced text Pixel data stored in frame buffers 18A-18P are repeatedly accessed by video controller 20 and used to provide an image on display screen 15. When it is desired to perform a bit-block transfer, switching circuits 30, 32 are used to provide for the transfer of data between different frame buffers.
An illustration of a bit block transfer is shown in FIG. 2. It involves transferring the image for block 54 of pixels to block 56, which has the same size as block 54 but is in a different position on screen 15. Because this transfer is not at the boundaries of cells 22, the pixels must be transferred from one frame buffer to another. e.g., the pixels in first three columns of the upper row (indicated by dots in FIG. 2 and processed by PPO, PPI, and PP2) are to be transferred to the last three columns of the bottom row (processed by PP13, PP14, and PP15). In transferring the entire block of pixel data, there is a transfer between pixel processors 16A-16P to the right by one column and downward three rows.
In order to make the transfer, host computer 12 sends commands to the pixel processors identifying the coordinates of the first pixel (upper left-hand corner) at the source and at the destination, the height and width of the block, and what type of Boolean operation (e.g., AND, OR, EXOR) should be performed at the source and destination blocks; for example, copying an image involves leaving pixel data stored at the source locations, and moving an image involves providing background color data at the source locations. The CA, CB and RA, RB control signals are determined by displacement logic in the pixel processors from the least two significant bits of source and destination coordinates. (The least two significant bits identify pixel processors.) Although all pixel processors 16A-16P include the displacement logic, only one is connected to provide CA, CB, RA, RB control signals to switching circuits 30, 32.
In the illustration shown in FIG. 2, the column control signals CA, CB cause the second group of inputs of each column multiplexer 38-44 to be connected to the outputs. The row control signals, RA, RB, cause the last group of inputs to each row multiplexer 46-52 to be provided as outputs. Thus the 3012 input to multiplexer 38 is provided as the output of multiplexer 38, and this combination of inputs to multiplexer 52 is provided as the output of multiplexer 52 to pixel processors PP12-PP15.
For a given bit-block transfer, the column and row control signals, CA, CB, RA, RB, do not change. The pixel data for all cells 22 in block 54 are provided serially over serial data lines S01, S00 from source pixel processors and connected through switching circuits 30, 32 to serial data lines SI1, SI0 to destination pixel processors. The transfer of pixel data is thus accomplished at high-speed and without tying up host bus 19 and without using external dedicated memory. At the destination pixel processors, the transferred pixel data are sent to the addresses of the appropriate cells 22 in the associated frame buffer under control of the receiving pixel processor. Switching circuits 30, 32 operate in parallel, doubling the speed of transfer. If further serial data lines are made available, additional switching circuits could be added in modular fashion to provide a further increase in speed.
Other embodiments of the invention are within the scope of the following claims.
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|U.S. Classification||345/505, 345/536|
|International Classification||G09G5/393, G06T17/00|
|Cooperative Classification||G09G5/393, G06T17/00|
|European Classification||G06T17/00, G09G5/393|
|May 12, 1988||AS||Assignment|
Owner name: DIGITAL EQUIPMENT CORPORATION, MAYNARD, MA A MA CO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:ASSARPOUR, HAMID;WALTON, LEA;REEL/FRAME:004892/0117
Effective date: 19880503
Owner name: DIGITAL EQUIPMENT CORPORATION, MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ASSARPOUR, HAMID;WALTON, LEA;REEL/FRAME:004892/0117
Effective date: 19880503
|Mar 1, 1994||FPAY||Fee payment|
Year of fee payment: 4
|Mar 17, 1998||FPAY||Fee payment|
Year of fee payment: 8
|Jan 9, 2002||AS||Assignment|
Owner name: COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DIGITAL EQUIPMENT CORPORATION;COMPAQ COMPUTER CORPORATION;REEL/FRAME:012447/0903;SIGNING DATES FROM 19991209 TO 20010620
|Feb 21, 2002||FPAY||Fee payment|
Year of fee payment: 12
|Jan 21, 2004||AS||Assignment|
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS
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