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Publication numberUS4970408 A
Publication typeGrant
Application numberUS 07/428,678
Publication dateNov 13, 1990
Filing dateOct 30, 1989
Priority dateOct 30, 1989
Fee statusPaid
Also published asEP0426351A2, EP0426351A3
Publication number07428678, 428678, US 4970408 A, US 4970408A, US-A-4970408, US4970408 A, US4970408A
InventorsCarl C. Hanke, Carlos D. Obregon, Timothy W. Sutton
Original AssigneeMotorola, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
CMOS power-on reset circuit
US 4970408 A
Abstract
The output signal of a CMOS power-on reset circuit changes state upon detecting a predetermined threshold of the power supply voltage during the start-up transient. During the power-up of the power supply voltage, the output signal of the power-on reset circuit ramps up with the power supply voltage until the latter reaches a first predetermined level whereat a control signal begins to track the increasing power supply voltage, less two diodes potentials. Upon reaching the turn-on potential of a transistor, the control signal activates an inverter to substantially reduce the output signal signifying that the power supply voltage level is sufficient for the operation of external circuitry. The output signal then disables the current flowing through the power-on reset circuit to save power consumption.
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Claims(18)
We claim:
1. A circuit responsive to an increasing potential supplied at a first power supply conductor for providing at an output an output signal indicative of the increasing potential until reaching a predetermined threshold of the increasing potential whereat the output signal is substantially reduced, comprising:
first means coupled to the first power supply conductor for providing the output signal which tracks the increasing potential of the first power supply conductor;
second means responsive to the increasing potential of the first power supply conductor upon detecting the predetermined threshold thereof for inhibiting said first means such that the output signal is substantially reduced; and
third means responsive to the reduced output signal for suppressing the current flowing through first and second means.
2. The circuit of claim 1 wherein said second means comprises:
a first transistor having a gate, a drain and a source, said gate being coupled to the first power supply conductor, said source being coupled to a second power supply conductor;
at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor; and
a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to said second power supply conductor, said drain being coupled to the output.
3. The circuit of claim 2 wherein said first means comprises a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor, said source being coupled to the first power supply conductor.
4. The circuit of claim 3 wherein said third means comprises a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor.
5. The circuit of claim 4 wherein said third means further comprises a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.
6. The circuit of claim 5 wherein said first means further comprises a driver circuit coupled between said drain of said second transistor and the output.
7. The circuit of claim 6 wherein said driver circuit comprises a first inverter having an input coupled to said drain of said second transistor and having an output.
8. The circuit of claim 7 wherein said driver circuit further comprises a second inverter having an input coupled to said output of said first inverter and having an output coupled to the output.
9. The circuit of claim 8 wherein said first inverter comprises:
a sixth transistor having a gate, a drain and a source, said gate being coupled to said input of said first inverter, said drain being coupled to said output of said first inverter, said source being coupled to the first power supply conductor; and
a seventh transistor having a gate, a drain and a source, said gate being coupled to said input of said first inverter, said drain being coupled to said output of said first inverter, said source being coupled to said second power supply conductor.
10. The circuit of claim 9 wherein said second inverter comprises:
an eighth transistor having a gate, a drain and a source, said gate being coupled to said input of said second inverter, said drain being coupled to said output of said second inverter, said source being coupled to the first power supply conductor; and
a ninth transistor having a gate, a drain and a source, said gate being coupled to said input of said second inverter, said drain being coupled to said output of said second inverter, said source being coupled to said second power supply conductor.
11. A circuit having an output for providing an output signal in response to the power-on transient of a first power supply conductor wherein the output signal changes state at a predetermined threshold of the potential developed at the first power supply conductor independent of the slew rate thereof, comprising:
a first transistor having a drain, a source and a gate coupled to the first power supply conductor;
at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor;
a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to a second power supply conductor, said drain being coupled to the output;
a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor;
a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor; and
a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.
12. The circuit of claim 11 further comprising a driver circuit coupled between said drain of said second transistor and the output.
13. The circuit of claim 12 wherein said driver circuit comprises a first inverter having an input coupled to said drain of said second transistor and having an output.
14. The circuit of claim 13 wherein said driver circuit further comprises a second inverter having an input coupled to said output of said first inverter and having an output coupled to the output.
15. The circuit of claim 14 wherein said first inverter comprises:
a sixth transistor having a gate, a drain and a source, said gate being coupled to said input of said first inverter, said drain being coupled to said output of said first inverter, said source being coupled to the first power supply conductor; and
a seventh transistor having a gate, a drain and a source, said gate being coupled to said input of said first inverter, said drain being coupled to said output of said first inverter, said source being coupled to said second power supply conductor.
16. The circuit of claim 15 wherein said second inverter comprises:
an eighth transistor having a gate, a drain and a source, said gate being coupled to said input of said second inverter, said drain being coupled to said output of said second inverter, said source being coupled to the first power supplu conductor; and
an ninth transistor having a gate, a drain and a source, said gate being coupled to said input of said second inverter, said drain being coupled to said output of said second inverter, said source being coupled to said second power supply conductor.
17. An integrated circuit having an output for providing an output signal in response to the power-on transient of a first power supply conductor wherein the output signal changes state at a predetermined threshold of the potential developed at the first power supply conductor independent of the slew rate thereof, comprising:
a first transistor having a drain, a source and a gate coupled to the first power supply conductor;
at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor;
a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to a second power supply conductor, said drain being coupled to the output;
a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor;
a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor; and
a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.
18. The method of detecting a predetermined threshold of an increasing potential supplied at a power supply conductor during power-on and providing an output signal in response thereto, comprising the steps of:
establishing an output signal which tracks the increasing potential supplied at the power supply conductor;
developing a control signal having a slew rate substantially equal to the slew rate of the increasing potential of the power supply conductor as the increasing potential of the power supply conductor reaches a first predetermined level;
reducing the output signal upon detecting a predetermined level of said control signal corresponding to a second predetermined level of the increasing potential of the power supply conductor; and
disabling the current flow upon detecting the reduction of the output signal.
Description
BACKGROUND OF THE INVENTION

The present invention relates in general to power-on reset circuits, and more particularly, to a CMOS power-on reset circuit for providing an output signal during system start-up as the power supply voltage reaches a predetermined magnitude.

Power-on reset circuits are found in many applications wherein a delay is needed to provide time for the power supply voltage to ramp up to a sufficient operating level prior to the initialization of certain external circuitry. It is common to connect the output of the power-on reset circuit to the enable inputs of these external circuits to initially inhibit the operation thereof. In one example, the output signals of a clock distribution circuit are disabled at the system power-up until the power supply voltage reaches a sufficient level at which time the output clock signals are simultaneously enabled by the output signal of the power-on reset circuit to establish the correct phase relationship therebetween.

Conventional power-on reset circuits typically use a resistor and capacitor combination to introduce a time constant wherein some time is required to charge the capacitor to a predetermined voltage to trigger the output signal of the power-on reset circuit and thereby allow sufficient time for the power supply voltage to ramp up. In general, the time constant of the resistor and capacitor combination and the slew rate of the power supply voltage are not synchronized. A problem may occur if the slew rate of the power supply voltage is slow in comparison to the pre-established time constant permitting the output signal of the power-on reset circuit to enable the external circuitry before the power supply voltage reaches an operating level. Alternately, if the time constant is made extremely long, time is wasted after the power supply voltage reaches operating level until the time constant expires and the output signal of the power-on reset circuit changes state. Furthermore, conventional power-on reset circuits continue to consume power in static operation which is undesirable especially in CMOS technology.

Hence, there is a need for a power-on reset circuit operating independent of the slew rate of the power supply voltage and without a predetermined time constant to provide an output signal upon detecting a predetermined threshold of the power supply voltage start-up transient. In addition, the conduction paths through the power-on reset circuit are disabled during static operation for reducing the power consumption to substantially zero.

SUMMARY OF THE INVENTION

Accordingly, it is an objective of the present invention to provide an improved power-on reset circuit.

A further objective of the present invention is to provide an improved power-on reset circuit for providing an output signal upon detecting a predetermined threshold of the power supply voltage during system start-up.

Another objective of the present invention is to provide an improved power-on reset circuit operating independent of the slew rate of the power supply voltage.

Still another objective of the present invention is to provide an improved power-on reset circuit integrable with minimal space.

Yet another objective of the present invention is to provide an improved CMOS power-on reset circuit consuming negligible power during static operation.

In accordance with the above and other objectives there is provided a power-on reset circuit responsive to an increasing potential supplied at a first power supply conductor for providing at an output an output signal indicative of the increasing potential until reaching a predetermined threshold of the increasing potential whereat the output signal is substantially reduced, comprising a first circuit coupled to the first power supply conductor for providing the output signal which tracks the increasing potential of the first power supply conductor; second circuit responsive to the increasing potential of the first power supply conductor upon detecting the predetermined threshold thereof for inhibiting the first circuit wherein the output signal is substantially reduced; and a third circuit responsive to the reduced output signal for suppressing the current flowing through the first and second circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating the preferred embodiment of the present invention; and

FIG. 2 is a drawing of waveforms which are useful in the description of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, power-on reset circuit 10, which is suited to be manufactured in an integrated circuit form, comprises enhancement mode MOS transistors fabricated in a P-Well based CMOS process as is well understood. Power-on reset circuit comprises diodes 12 and 14 serially coupled between power supply conductor 16 and the drain of transistor 18 at node 20. The gate and source of transistor 18 are coupled to power supply conductor 16, typically operating at VCC, and the drain of transistor 22, respectively, while the source of transistor 22 is coupled to power supply conductor 24 which typically operates at ground potential. The source of transistor 26 is coupled to power supply conductor 16, and the drain of the same is coupled to the source of transistor 28, the latter of which includes a gate coupled to power supply conductor 24 and a drain coupled at node 30 to the drain of transistor 32. The gate and source of transistor 32 are then coupled to node 20 and power supply conductor 24, respectively. The sources of transistors 34 and 36 are coupled to power supply conductor 16, and the gates of transistor 34 and 38 are coupled together to node 30. The drain of transistor 34 is coupled to the drain of transistor 38 and to the gates of transistors 26, 36 and 40 at node 42. The sources of transistors 38 and 40 are coupled to power supply conductor 24, and the drains of transistors 36 and 40 are coupled together to output 44. The gate of transistor 22 is also coupled to output 44.

The operation of power-on reset circuit 10 proceeds as follows. Starting from zero voltage at time t0, FIG. 2, the power supply voltage VCC ramps up rendering P-channel transistors 26, 28 and 36 conductive and pulling the potentials at node 30 and output 44 up to the increasing voltage VCC to turn on N-channel transistors 22 and 38. The power supply voltage VCC continues to increase until time t1 of FIG. 2 wherein diodes 12 and 14 become forward biased whereby the potential at node 20 begins to track the slew rate of voltage VCC with a magnitude of VCC - V12 -V14, where V12 and V14 are the potentials across diodes 12 and 14, respectively. The conduction path through transistor 18 is then enabled through transistor 22 to power supply conductor 24. At time t2, the potential developed at node 20, V20, reaches the gate-source voltage necessary to turn on transistor 32. The gate length of transistor 32 is sized to have a greater drive capacity than transistor 28, hence, the voltage at node 30, V30, begins to fall as shown in FIG. 2. When voltage V30 falls to the transition threshold of the inverter formed through transistors 34 and 38 at time t3, transistor 38 turns off and transistor 34 turns on forcing the voltage at node 42 high to turn off transistor 36 and turn on transistor 40. The threshold of the inverter (34, 38) is typically made less than VCC /2 to extend the time interval between time t2 and t3. The voltage at output 44, V44, falls rapidly providing the output signal of power-on reset circuit 10 signifying to the external circuitry connected thereto that power supply voltage VCC has reached a sufficient potential to commence operation. Meanwhile, the sharp transition of voltage V44 also turns off transistor 22 disabling the conduction path through diodes 12 and 14 and transistor 18, and the high potential of voltage V42 turns off transistor 26 inhibiting the conduction path through transistors 28 and 32 such that substantially zero power is consumed during static operation. The output signal of power-on reset circuit 10 changes state at a predetermined threshold of the power supply voltage independent of the slew rate thereof. It should be appreciated by now that the slew rate of the power supply voltage is irrelevant.

The output of power-on reset circuit 10 is typically coupled to the enabled inputs of external circuitry. For example, the output signals of a clock distribution circuit may be disabled at the system power-up until the power supply voltage reaches a sufficient level at which time the output clock signals are simultaneously enabled at the change of state of the output signal of the power-on reset circuit to establish the correct phase relationship therebetween.

The predetermined threshold of the power supply voltage may be adjusted through the gate-source potentials of transistors 34 and 38 and, to a lesser extent, through the gate length of transistor 18. For example, the threshold of voltage VCC may be increased by enlarging the ratio of the gate width of transistor 38 to the gate width of transistor 34 which provides a higher turn on threshold for transistor 38 and, correspondingly, a greater value of VCC to transition the output signal. Alternately, the gate width of transistor 18 may be increased to conduct additional current therethrough and increase the potential developed across diodes 12 and 14 to increase the value of VCC at which the output signal transitions low.

Hence, what has been provided is a novel power-on reset circuit that changes the state of the output signal at a predetermined threshold of the power supply voltage independent of the slew rate of the start-up transient while achieving substantially zero steady state current flow.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3895239 *Dec 26, 1973Jul 15, 1975Motorola IncMOS power-on reset circuit
US4812679 *Nov 9, 1987Mar 14, 1989Motorola, Inc.Power-on reset circuit
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5103115 *Jul 18, 1991Apr 7, 1992Fuji Xerox Co., Ltd.Power-on reset circuit
US5109163 *Feb 15, 1991Apr 28, 1992Zilog, Inc.Integrated power-on reset circuit
US5144159 *Nov 26, 1990Sep 1, 1992Delco Electronics CorporationPower-on-reset (POR) circuit having power supply rise time independence
US5159206 *Jul 31, 1990Oct 27, 1992Tsay Ching YuhPower up reset circuit
US5166545 *Jul 10, 1991Nov 24, 1992Dallas Semiconductor CorporationPower-on-reset circuit including integration capacitor
US5300840 *Nov 23, 1992Apr 5, 1994Sgs-Thomson Microelectronics, S.A.Redundancy fuse reading circuit for integrated memory
US5323067 *Apr 14, 1993Jun 21, 1994National Semiconductor CorporationSelf-disabling power-up detection circuit
US5359297 *Oct 28, 1993Oct 25, 1994Motorola, Inc.VCO power-up circuit for PLL and method thereof
US5481299 *May 16, 1994Jan 2, 1996Coffey; Lawrence G.Power saving device for video screen
US5498987 *Jun 20, 1994Mar 12, 1996Beacon Light Products, Inc.Integratable solid state reset circuit operable over a wide temperature range
US5508649 *Jul 21, 1994Apr 16, 1996National Semiconductor CorporationVoltage level triggered ESD protection circuit
US5517015 *Aug 31, 1994May 14, 1996Dallas Semiconductor CorporationCommunication module
US5517447 *Mar 14, 1994May 14, 1996Dallas Semiconductor CorporationElectronic module energy storage circuitry
US5523724 *Aug 19, 1994Jun 4, 1996Cirrus Logic, Inc.Fast recovering charge pump for controlling a VCO in a low power clocking circuit
US5528184 *Jun 28, 1993Jun 18, 1996Sgs-Thomson Microelectronics, S.R.L.Power-on reset circuit having a low static power consumption
US5534804 *Feb 13, 1995Jul 9, 1996Advanced Micro Devices, Inc.CMOS power-on reset circuit using hysteresis
US5552736 *Apr 19, 1995Sep 3, 1996Hewlett-Packard CompanyPower supply detect circuit operable shortly after an on/off cycle of the power supply
US5555166 *Jun 6, 1995Sep 10, 1996Micron Technology, Inc.Self-timing power-up circuit
US5578951 *Dec 8, 1994Nov 26, 1996Samsung Electronics Co., Ltd.CMOS circuit for improved power-on reset timing
US5604343 *May 24, 1994Feb 18, 1997Dallas Semiconductor CorporationSecure storage of monetary equivalent data systems and processes
US5615130 *Dec 14, 1994Mar 25, 1997Dallas Semiconductor Corp.Systems and methods to gather, store and transfer information from electro/mechanical tools and instruments
US5619066 *Aug 31, 1994Apr 8, 1997Dallas Semiconductor CorporationMemory for an electronic token
US5679944 *Nov 18, 1994Oct 21, 1997Dallas Semiconductor CorporationPortable electronic module having EPROM memory, systems and processes
US5691887 *Aug 22, 1996Nov 25, 1997Micron Technology, Inc.Self-timing power-up circuit
US5696461 *Aug 31, 1995Dec 9, 1997Sgs-Thomson Microelectronics S.R.L.Power-on reset circuit
US5714898 *Jan 4, 1996Feb 3, 1998Lg Semicon Co., Ltd.Power supply control circuit
US5761697 *Nov 2, 1994Jun 2, 1998Dallas Semiconductor CorporationIdentifiable modules on a serial bus system and corresponding identification methods
US5787018 *Mar 17, 1997Jul 28, 1998Dallas Semiconductor CorporationSystems and methods to gather, store, and transfer information from electro/mechanical tools and instruments
US5844429 *Jul 15, 1996Dec 1, 1998Lg Semicon Co., Ltd.Burn-in sensing circuit
US5848541 *Nov 29, 1994Dec 15, 1998Dallas Semiconductor CorporationElectrical/mechanical access control systems
US5898242 *Mar 17, 1993Apr 27, 1999Unisys CorporationSelf-calibrating clock circuit employing a continuously variable delay module in a feedback loop
US5940345 *Dec 12, 1997Aug 17, 1999Cypress Semiconductor Corp.Combinational logic feedback circuit to ensure correct power-on-reset of a four-bit synchronous shift register
US5994770 *Apr 24, 1997Nov 30, 1999Dallas Semiconductor CorporationPortable electronic data carrier
US6078201 *Jan 6, 1998Jun 20, 2000Xilinx, Inc.Power-on reset circuit for dual supply voltages
US6107847 *Dec 30, 1997Aug 22, 2000Rambus Inc.Zero power reset circuit for low voltage CMOS circuits
US6112275 *Dec 28, 1994Aug 29, 2000Dallas Semiconductor CorporationMethod of communicating over a single wire bus between a host device and a module device which measures thermal accumulation over time
US6157227 *Dec 18, 1997Dec 5, 2000Sgs-Thomson Microelectronics SaDevice for neutralization in an integrated circuit
US6160431 *Apr 12, 2000Dec 12, 2000Xilinx, Inc.Power-on reset circuit for dual supply voltages
US6217213May 26, 1998Apr 17, 2001Dallas Semiconductor CorporationTemperature sensing systems and methods
US6236249 *Jun 14, 1999May 22, 2001Samsung Electronics Co., Ltd.Power-on reset circuit for a high density integrated circuit
US6281723 *Dec 18, 1997Aug 28, 2001Sgs-Thomson Microelectronics S.A.Device and method for power-on/power-off checking of an integrated circuit
US6335646 *Apr 19, 2000Jan 1, 2002Oki Electric Industry Co., Ltd.Power-on reset circuit for generating a reset pulse signal upon detection of a power supply voltage
US6404246Dec 20, 2000Jun 11, 2002Lexa Media, Inc.Precision clock synthesizer using RC oscillator and calibration circuit
US6580311 *Feb 4, 2002Jun 17, 2003Infineon Technologies AgCircuit configuration for supplying voltage to an integrated circuit via a pad
US6658597Oct 22, 1999Dec 2, 2003Industrial Technology Research InstituteMethod and apparatus for automatic recovery of microprocessors/microcontrollers during electromagnetic compatibility (EMC) testing
US6677787 *Jul 12, 2002Jan 13, 2004Intel CorporationPower indication circuit for a processor
US6744291Aug 30, 2002Jun 1, 2004Atmel CorporationPower-on reset circuit
US6788118 *Nov 17, 2003Sep 7, 2004Intel CorporationPower indication circuit for a processor
US6868500 *Jun 22, 2001Mar 15, 2005Cypress Semiconductor CorporationPower on reset circuit for a microcontroller
US7142024 *Nov 1, 2004Nov 28, 2006Stmicroelectronics, Inc.Power on reset circuit
US7196561 *Aug 25, 2004Mar 27, 2007Agere Systems Inc.Programmable reset signal that is independent of supply voltage ramp rate
US7231533 *Aug 24, 2004Jun 12, 2007Microchip Technology IncorporatedWake-up reset circuit draws no current when a control signal indicates sleep mode for a digital device
US7348814Aug 24, 2004Mar 25, 2008Macronix International Co., Ltd.Power-on reset circuit
US7551021 *Jun 22, 2005Jun 23, 2009Qualcomm IncorporatedLow-leakage current sources and active circuits
US7564278Feb 13, 2008Jul 21, 2009Macronix International Co., Ltd.Power-on reset circuit
US7737724Dec 27, 2007Jun 15, 2010Cypress Semiconductor CorporationUniversal digital block interconnection and channel routing
US7761845Sep 9, 2002Jul 20, 2010Cypress Semiconductor CorporationMethod for parameterizing a user module
US7765095Nov 1, 2001Jul 27, 2010Cypress Semiconductor CorporationConditional branching in an in-circuit emulation system
US7770113Nov 19, 2001Aug 3, 2010Cypress Semiconductor CorporationSystem and method for dynamically generating a configuration datasheet
US7774190Nov 19, 2001Aug 10, 2010Cypress Semiconductor CorporationSleep and stall in an in-circuit emulation system
US7825688Apr 30, 2007Nov 2, 2010Cypress Semiconductor CorporationProgrammable microcontroller architecture(mixed analog/digital)
US7844437Nov 19, 2001Nov 30, 2010Cypress Semiconductor CorporationSystem and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
US7893724Nov 13, 2007Feb 22, 2011Cypress Semiconductor CorporationMethod and circuit for rapid alignment of signals
US7969212 *Jun 30, 2009Jun 28, 2011Hynix Semiconductor Inc.Circuit for generating power-up signal of semiconductor memory apparatus
US8026739Dec 27, 2007Sep 27, 2011Cypress Semiconductor CorporationSystem level interconnect with programmable switching
US8040266Mar 31, 2008Oct 18, 2011Cypress Semiconductor CorporationProgrammable sigma-delta analog-to-digital converter
US8049569Sep 5, 2007Nov 1, 2011Cypress Semiconductor CorporationCircuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes
US8067948Feb 21, 2007Nov 29, 2011Cypress Semiconductor CorporationInput/output multiplexer bus
US8069405Nov 19, 2001Nov 29, 2011Cypress Semiconductor CorporationUser interface for efficiently browsing an electronic document using data-driven tabs
US8069428Jun 12, 2007Nov 29, 2011Cypress Semiconductor CorporationTechniques for generating microcontroller configuration information
US8069436Aug 10, 2005Nov 29, 2011Cypress Semiconductor CorporationProviding hardware independence to automate code generation of processing device firmware
US8078894Mar 27, 2008Dec 13, 2011Cypress Semiconductor CorporationPower management architecture, method and configuration system
US8078970Nov 9, 2001Dec 13, 2011Cypress Semiconductor CorporationGraphical user interface with user-selectable list-box
US8085067Dec 21, 2006Dec 27, 2011Cypress Semiconductor CorporationDifferential-to-single ended signal converter circuit and method
US8085100Feb 19, 2008Dec 27, 2011Cypress Semiconductor CorporationPoly-phase frequency synthesis oscillator
US8089461Jun 23, 2005Jan 3, 2012Cypress Semiconductor CorporationTouch wake for electronic devices
US8092083Oct 1, 2007Jan 10, 2012Cypress Semiconductor CorporationTemperature sensor with digital bandgap
US8103496Nov 1, 2001Jan 24, 2012Cypress Semicondutor CorporationBreakpoint control in an in-circuit emulation system
US8103497Mar 28, 2002Jan 24, 2012Cypress Semiconductor CorporationExternal interface for event architecture
US8106689 *May 26, 2011Jan 31, 2012Hynix Semiconductor Inc.Circuit for generating power-up signal of semiconductor memory apparatus
US8120408Jul 14, 2008Feb 21, 2012Cypress Semiconductor CorporationVoltage controlled oscillator delay cell and method
US8130025Apr 17, 2008Mar 6, 2012Cypress Semiconductor CorporationNumerical band gap
US8149048Aug 29, 2001Apr 3, 2012Cypress Semiconductor CorporationApparatus and method for programmable power management in a programmable analog circuit block
US8160864Nov 1, 2001Apr 17, 2012Cypress Semiconductor CorporationIn-circuit emulator and pod synchronized boot
US8176296Oct 22, 2001May 8, 2012Cypress Semiconductor CorporationProgrammable microcontroller architecture
US8286125Aug 10, 2005Oct 9, 2012Cypress Semiconductor CorporationModel for a hardware device-independent method of defining embedded firmware for programmable systems
US8358150Oct 11, 2010Jan 22, 2013Cypress Semiconductor CorporationProgrammable microcontroller architecture(mixed analog/digital)
US8370791Jun 3, 2008Feb 5, 2013Cypress Semiconductor CorporationSystem and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
US8402313Nov 20, 2007Mar 19, 2013Cypress Semiconductor CorporationReconfigurable testing system and method
US8476928Aug 3, 2011Jul 2, 2013Cypress Semiconductor CorporationSystem level interconnect with programmable switching
US8499270Jun 28, 2011Jul 30, 2013Cypress Semiconductor CorporationConfiguration of programmable IC design elements
US8516025Apr 16, 2008Aug 20, 2013Cypress Semiconductor CorporationClock driven dynamic datapath chaining
US8527949Jul 13, 2011Sep 3, 2013Cypress Semiconductor CorporationGraphical user interface for dynamically reconfiguring a programmable device
US8533677Sep 27, 2002Sep 10, 2013Cypress Semiconductor CorporationGraphical user interface for dynamically reconfiguring a programmable device
US8555032Jun 27, 2011Oct 8, 2013Cypress Semiconductor CorporationMicrocontroller programmable system on a chip with programmable interconnect
CN1333525C *Nov 30, 2004Aug 22, 2007旺宏电子股份有限公司A circuit and a method for generating a power-on reset signal
EP0575687A1 *Jun 26, 1992Dec 29, 1993SGS-THOMSON MICROELECTRONICS s.r.l.Power-on reset circuit having a low static consumption
EP0700159A1 *Aug 31, 1994Mar 6, 1996SGS-THOMSON MICROELECTRONICS S.r.l.Threshold detection circuit
WO1994024762A1 *Apr 4, 1994Oct 27, 1994Nat Semiconductor CorpSelf-disabling power-up detection circuit
WO1995035596A1 *Jun 19, 1995Dec 28, 1995Beacon Light Prod IncIntegratable solid state reset circuit operable over a wide temperature range
Classifications
U.S. Classification327/143
International ClassificationH03K17/22
Cooperative ClassificationH03K17/223
European ClassificationH03K17/22B
Legal Events
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Feb 2, 2007ASAssignment
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