|Publication number||US4987088 A|
|Application number||US 07/381,283|
|Publication date||Jan 22, 1991|
|Filing date||Jul 18, 1989|
|Priority date||Jul 29, 1988|
|Also published as||EP0362147A2, EP0362147A3|
|Publication number||07381283, 381283, US 4987088 A, US 4987088A, US-A-4987088, US4987088 A, US4987088A|
|Inventors||Carlo Bergonzoni, Tiziana Cavioni, Giuseppe P. Crisenza|
|Original Assignee||Sgs-Thomson Microelectronics S.R.L.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (6), Classifications (10), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a process for fabricating doped polycrystalline silicon and/or polycrystalline silicide gate integrated CMOS devices, and more particularly to a process for fabricating devices having a sub-micron gate length designed to operate with a relatively high supply voltage.
2. Description of the Prior Art
According to state-of-the-art fabrication technology of CMOS devices, e.g. n-welltype devices, wherein polycrystalline silicon and/or polycrystalline silicide gate structures are commonly subjected to n-type doping on n-channel transistors as well as on p-channel transistors in order to obtain an acceptable threshold voltage, the practice of introducing, in these integrated circuits, "buried" p-channel transistors is common. These special transistors are obtained during the fabrication process of the device by creating a thin p-doped region at the surface of n-well regions; i.e. above the channel region of a p-channel transistor. This configuration, if from one side allows appropriate adjustment of the threshold voltage value, determines far from optimal electrical characteristics especially for transistors having a very small gate length, such as a relatively steep "below ground" curve and an increased sensitivity to punch-through. Moreover, the thickness of this p-doped region below the gate of the transistor constitutes a very critical feature because a too thick layer would cause the device to operate as a depletion type MOS transistor with totally different and inadequate characteristics. Of course, with correctly inverted polarities, the same problem also arises in p-well CMOS devices as well as in twin-well devices.
This technical problem is overcome, according to the present invention without introducing the above-noted critical modification in the fabrication process and without the need of an additional mask as in the case of such a prior art technique. In other words, by the present invention, it is no longer necessary to resort to the creation of buried channel transistors for achieving the desired threshold voltage values when devices having an extremely reduced gate length are designed for operation at relatively high supply voltages, as in nonvolatile EPROM memories.
It has also been found that for devices having a gate length of about a micrometer or a fraction thereof, requiring the use of a gate oxide having a thickness less than or equal to 200 Angstroms, it is possible to maintain the threshold voltage transistors made in the well diffusion, e.g. of the p-channel transistor in n-well devices, within an entirely satisfactory range of variation: from -1.0 to -1.2 V, without exceeding a surface concentration of 1×1016 atoms of impurities per square centimeter in the diffused n-well region. This is achieved according to the present invention by performing an unmasked boron implantation over the entire surface of the silicon substrate after having formed the n-well deep diffused region so as to produce a partial compensation of the superficial doping level of the n-well region and simultaneously an enrichment of the superficial doping level of the monocrystalline p-type silicon outside the n-well regions where n-channel transistors will be made.
It has been found that by implanting boron ions in a dose comprising between 0.5×1012 and 3×1012 atoms per square centimeter of exposed surface of the substrate and with a kinetic energy nominally comprising between 20 and 30 KeV, n-well CMOS devices are obtained wherein the p-channel transistor threshold voltage remains contained between about -1.0 and -1.2 V, though having a gate length reduced to 0.6 micrometers. Of course the technique of the instant invention is also equally applicable in the case of p-well CMOS devices as well as in the case of the so-called twin-well CMOS devices. The additional process step required by the method of the present invention is easily performed and is compatible with each of the different architectures of these kinds of devices.
The improved CMOS fabrication process of the present invention is particularly useful for fabricaing nonvolatile, EPROM type memories, wherein for maintaining very small gate dimensions, it is necessary to provide the transistors with adequate protections against breakdown and punch-through. The introduction of an implantation process step for compensating the well region doping at the surface coupled with the possibility of utilizing arrangements such as the lightly doped drain (LDD) for transistors of one or both polarities allows the maintaining of a high breakdown voltage of the transistor formed within the well, by lowering the doping concentration of the well near the transistors's junctions without critically affecting the punch-through voltage characteristic of the same transistor, which is determined by the doping profile of a deeper portion of the well region. Simultaneously, through the same compensating implantation, the transistor formed outside the well regions receives substantially an anti punch-through implantation making it more suitable for operation at a relatively high voltage. To be noted is the fact that by carrying out the unmasked compensation implantation before growing the field oxide allows the making of the doping profiles characteristics independent in a large measure from the heat treatments required for forming the dielectric insulating layers between stacked layers of polycrystalline silicon or silicide in EPROM memories fabrication processes because the main diffusion occurs during field oxidation and the thermal balance of this step is so high as to substantially stabilize the doping profiles in respect to successive heat treatments.
An example of a fabrication process for n-well CMOS devices modified in accordance with the present invention comprises the following steps:
1. formation of the deep n-well diffusion on a monocrystalline p-type silicon substrate;
2. unmasked compensating implantation of boron over the whole substrate;
3. definition and isolation of the active areas by field oxidation according to any one of the commonly used techniques;
4. formation of a gate oxide layer over the substrate surface;
5. deposition, doping and definition of a first polycrystalline silicon layer;
6. formation of the p+ mask and implantation of the p+ junctions;
7. formation of the n+ mask and implantation of the n+ junctions;
8. formation in a conventional manner of the contacts and of the interconnecting lines and completion of the final steps of the standard fabrication process.
Of course the fabrication process may also contemplate the forming of a gate of stacked polycrystalline silicon and polycristalline silicide, polycrystalline silicide, etc., as well as the formation of ligthly doped drain (LDD) transistors, the formation of spacers with material other than silicon oxides, and other known techniques as well.
Naturally, if the process of the present invention is applied for fabricating devices with a p-well architecture, the unmasked compensating implantation step on the entire substrate (step 2) will be of an n-type dopant, while in the case of fabricating devices with a twin-well architecture, the polarity of the dopant implanted during said additional step of the process will be chosen in accordance with of the specific necessity and required performances, according to considerations which will be readily made by a skilled technician on the basis of the present disclosure.
Following a standard, polycrystalline silicon gate, CMOS fabrication process, n-well CMOS devices are produced having a gate length of 0.6 μm for "low" supply voltage devices and with a 0.8 μm gate length for "high" supply voltage devices. A series of devices is fabricated by practicing the modified process in accordance with the present invention and by implanting boron over the entire substrate after having formed the deep n-well diffusions and employing a dose of about 1-2×1012 atoms per square centimeter at 25 KeV. Another series of devices is fabricated without performing the additional unmasked compensation implantation step of the present invention and by forming buried channel, p-channel transistors in accordance with the known art.
The devices fabricated in accordance with the present invention have a threshold voltage comprised between: -1.1 and -1.2 V and a below-ground slope of 75-80 mV/decade. By contrast the devices with buried p-channel transistors made in accordance with the known technique have a below-ground slope of about 100-110 mV/decade.
The compensating boron dose implanted in accordance with the present invention is also adequate to simultaneously form an anti punch-through diffusion in n-channel transistors.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4459741 *||Aug 17, 1982||Jul 17, 1984||Siemens Aktiengesellschaft||Method for producing VLSI complementary MOS field effect transistor circuits|
|US4613885 *||Jan 12, 1984||Sep 23, 1986||Texas Instruments Incorporated||High-voltage CMOS process|
|US4839301 *||Dec 19, 1988||Jun 13, 1989||Micron Technology, Inc.||Blanket CMOS channel stop implant employing a combination of n-channel and p-channel punch-through implants|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5834966 *||Dec 8, 1996||Nov 10, 1998||Stmicroelectronics, Inc.||Integrated circuit sensing and digitally biasing the threshold voltage of transistors and related methods|
|US5883544 *||Dec 3, 1996||Mar 16, 1999||Stmicroelectronics, Inc.||Integrated circuit actively biasing the threshold voltage of transistors and related methods|
|US5929695 *||Jun 2, 1997||Jul 27, 1999||Stmicroelectronics, Inc.||Integrated circuit having selective bias of transistors for low voltage and low standby current and related methods|
|US5939934 *||Dec 3, 1996||Aug 17, 1999||Stmicroelectronics, Inc.||Integrated circuit passively biasing transistor effective threshold voltage and related methods|
|US5970314 *||Mar 24, 1997||Oct 19, 1999||Sumitomo Electric Industries, Ltd.||Process for vapor phase epitaxy of compound semiconductor|
|USRE41764||Jun 5, 2000||Sep 28, 2010||Thomas Skotnicki||Semiconductor device with compensated threshold voltage and method for making same|
|U.S. Classification||438/217, 438/211, 257/E27.081, 257/E21.633|
|International Classification||H01L27/105, H01L27/092, H01L21/8238|
|Cooperative Classification||H01L27/105, H01L21/823807|
|Jul 18, 1989||AS||Assignment|
Owner name: SGS-THOMSON MICROELECTRONICS S.R.L., VIA C. OLIVET
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:BERGONZONI, CARLO;CAVIONI, TIZIANA;CRISENZA, GIUSEPPE;REEL/FRAME:005107/0737
Effective date: 19890710
|Jul 5, 1994||FPAY||Fee payment|
Year of fee payment: 4
|Jul 13, 1998||FPAY||Fee payment|
Year of fee payment: 8
|Jun 27, 2002||FPAY||Fee payment|
Year of fee payment: 12