|Publication number||US4987101 A|
|Application number||US 07/286,443|
|Publication date||Jan 22, 1991|
|Filing date||Dec 16, 1988|
|Priority date||Dec 16, 1988|
|Also published as||DE68924468D1, DE68924468T2, EP0373360A2, EP0373360A3, EP0373360B1, US5144411|
|Publication number||07286443, 286443, US 4987101 A, US 4987101A, US-A-4987101, US4987101 A, US4987101A|
|Inventors||Carter W. Kaanta, Stanley Roberts|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (115), Classifications (13), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates generally to a method and structure for reducing the capacitive coupling either between lines on the same layer (intralayer) or between lines on superposed layers (interlayer) in VLSI or ULSI circuits. In more particular aspects the present invention relates to a method and structure for yielding an effectively reduced dielectric constant between lines on the surface of a given VLSI or ULSI chip or on lines mounted on various layers or surfaces on VLSI or ULSI structures utilizing air, other gasses, or a partial vacuum as a dielectric medium.
It has been conventional prior art practice in integrated circuit chip production to utilize materials such as silicon dioxide, silicon nitride, polyimides and certain other organic materials as delectric materials interposed between the metal lines on a give layer and between various layers of metalization in the wiring portion of the integrated circuit chip.
However, as the integrated circuit technology progresses into a Very Large Scale Intergration (VLSI) and beyond to Ultra Large Scale Integration (ULSI) the spacing between the metal lines on any given plane and the interplanar spacing of metal lines becomes less and less, extending into the submicron range for intralayer spacing. This increases the capacitive losses between the lines and gives rise to a need for the space between the lines having improved dielectric properties; i.e., with a dielectric constant as low as possible.
The dielectric constants of silicon nitride (which is about 7.0), CVD silicon dioxide (which is 3.9), and polyimides (which are about 3.6), are not sufficiently low to provide acceptable insulation in these submicron ranges; hence, it is necessary to provide a medium with improved dielectric properties, e.g. a constant of 2.0 or less in the intraplanar spaces between lines and interplanar spaces between lines at different levels.
According to the present invention a method and structure for providing an insulating electrical space between two lines on a layer of material or between lines on adjacent superposed layers of material are provided. According to this invention a base member is formed having a plurality of support members extending upwardly from said base member. A removable material is deposited on said base member and around said support members. A cap member of insulating material is then disposed over said support members and said removable material. Access openings are formed in at least one of the base member or the cap member communicating with said removable material. The removable material is removed through the access openings to thereby define a space between said cap member and said base member and between said support members. During this step a partial vacuum (in which some inert gas may be dispersed) may be created in the space vacated by the removable material. The access openings are then filled in so as to provide a sealed space between the cap member and the base member which has a very low dielectric constant.
FIGS. 1a through 1h are perspective sectional views somewhat diagrammatic showing various steps in one method of producing a structure according to this invention; and
FIGS. 2a through 2m are perspective sectional views somewhat diagrammatic showing various steps in another method of producing a structure according to this invention.
Referring now to the drawing and for the present FIGS. 1a through 1f the various steps in producing a structure according to one method of the present invention are depicted, somewhat diagrammatically. As shown in FIG. 1a insulating substrate material 10 such as SiO2 is provided which may overlie the devices on a VLSI or ULSI integrated circuit chip (not shown). The insulating material 10 has disposed thereon metal lines 12 which may be aluminum or other metal which have been patterned by conventional photolithographic techniques to provide the desired wiring structure on top of the insulating layer 10. A layer of removable material 14 is deposited atop the substrate material 10 and around the metal lines 12. The preferred material for this is a poly-para-xylylene, (PPX) an organic polymer sold by Union Carbid Corporation, under the Trademark Parylene N, which can be readily selectively removed under certain specific conditions as will be described presently. However, other removable materials which have the property of being etched or consumed at a rate significantly and substantially faster than any of the material surrounding it (i.e. the metal and silicon dioxide) can also be used. Other such additional materials include spun on glasses which can be removed in HF acid etch.
When parylene is used, this can be deposited by chemical vapor deposition (CVD) techniques which are well known in the art. For example, CVD deposition by the Gorham method is a very good technique. This is done after first optionally applying an adhesion promoter such as A1100 sold by Shipley Co. Thereafter the PPX is applied by heating the PPX source material to 165° C. and passing the vapor through a furnace in a tube at 425° C. and thereafter depositing the heated vapor onto the substrate in a chamber at 40 microns pressure and room temperature. When the material has been deposited it is planarized by a suitable technique such as an etch back or other planarization techniques so that the top surface is flush with the top of the metal lines 12. One such etch back technique is as follows: A layer of planarizing resist material, such as AZ1350 sold by Shipley Co. is spun applied and then baked at about 120° C. This is followed by etching in O2 in a reactive ion etching tool. This etching continues until all the resist has been removed and the resulting structure is a planarized surface of parylene 14 and metal lines 12. This structure is shown in FIG. 1b.
An insulating cap material 16 is then deposited on top of the planarized parylene surface and metal, which cap preferably also is silicon dioxide which can be deposited by conventional techniques. In one such technique the SiO2 is deposited in an AME 3300 deposition tool using 1.9% SiH4 with He at 3000 sccm, and N2 O at 2500 sccm, carried out at a pressure of 2.0 Torr, a temperature of 340° C., and a power of 150 watts. Following this, a layer of photoresist material 18 is deposited on top of the insulating material 16 and patterned by conventional photolithographic processes so as to provide the desired opening configurations 19 for access to the metal lines and to parylene material as will become clear presently and as shown in FIG. 1c.
The revealed SiO2 material on the cap 16 underlying the openings 19 is removed by any conventional etching technique utilizing the unexposed remaining photoresist material 18 as a mask. One such technique being as follows: The SiO2 is etched in an AME 8100 etching tool using CHF3 at 75 sccm, and CO2 at 8 sccm, carried out at 40 millitor, at ambient temperature and at a power of 1200 watts. The remaining photoresist 18 is then removed. This will result in the structure shown in FIG. 1d. As can be seen in FIG. 1d there are a plurality of openings one of which is shown at 20, which extends through the cap material 16 to the underlying metalization layer 12, while other openings, one of which is shown at 22, extend through the insulating cap material 16 and communicate with the underlying parylene material 14. The openings 20 will be used to provide interlayer contact and the openings 22 will be used as access openings to remove the material 14 as will be described presently.
A metal such as tungsten 24 is deposited in the openings 20 as shown in FIG. 1e which can be effectively accomplished by selective deposition as follows: The tungsten is deposited in a Varian 5100 tool, using WF6 at 10 sccm, H2 at 200 sccm, SiH4 at 10 sccm and at a temperature of about 300° C.
Following the tungsten deposition, the parylene material is removed through the access openings by heating the entire structure in the O2 rich atmosphere at a temperature of about 200° C. This will cause the parylene material 14 to react with the oxygen in the atmosphere and essentially turn to gas and be expelled through the access openings 22 leaving spaces 25 between the metal lines 12 and between the base layer 10 and the cap 16 as shown in FIG. 1f.
At this point in the process, the access openings 22 are filled, preferably by a technique of CVD deposition of SiO2 utilizing an inert carrier gas at a pressure of about 100 millitorr. This is quite a low pressure and any ambient atmosphere which is contained within the spaces between the base 10 and cap 16 and between metal lines 12 is replaced by the vacuum and a certain small amount of whatever carrier gas is used to perform chemical vapor deposition of the SiO2. This chemical deposition of SiO2 will effectively close the access openings 22, and, since the process is being carried out at the very low pressure of 100 millitorr with inert carrier gas the resulting space between the metal lines 14 has a very low pressure therein containing only small amounts of inert gas. This will give a dielectric constant of 2.0 or less.
In the deposition of the SiO2 on the cap 16 to close the acces openings 22 there will also be a layer 26 of the SiO2 material deposited on the top thereof as shown in FIG. 1g. This layer 26 is then blanket etched by the reactive ion etching (R.I.E.) process as described above to expose the top of the tungsten as shown in FIG. 1h, which can then act as a via or stud for interlayer connection. The desired metallization can then be applied to the top of the cap layer 16, and the whole process repeated if additional layers of metallizations are desired.
Referring, now to FIGS. 2a through 2m the steps in another embodiment of this invention are shown which is particularly effective for providing not only intralayer insulation between two metal lines on a given layer, but also is especially effective for providing interlayer insulation of metal lines on two superposed layers of insulation.
In this embodiment, a first layer of metal 31 such as tungsten is blanket deposited onto an insulating substrate 30 such as silicon dioxide by any suitable deposition technique. One such technique is a sputter process utilizing a Perkins-Elmer 4450 tool at 600 watts D.C. magnetron sputtering at 10-30 millitorr pressure with a bias of between 0 and-60 volts. Thereafter a layer of aluminum is blanket deposited onto the tungsten by any suitable process. This aluminum can be deposited by using an RF evaporation source at a pressure of about 1 microtorr. On top of the aluminum metal 32, a silicon dioxide layer 34 is deposited as previously described. On top of the silicon dioxide layer 34 a layer of silicon nitride 36 is deposited. The silicon nitride deposition is preferably done in an ASM tool utilizing SiH4 at 175 sccm, and NH3 at 325 sccm, carried out at a pressure of 2 torr, a temperature of 375° C., and a power of 160 watts. This is the starting structure and is shown in FIG. 2a.
The overlying silicon nitride layer 36 is then patterned by convention photolithographic techniques and reactive ion etched to provide the structure shown in FIG. 2b wherein there are a series of pads of silicon nitride 36 atop the silicon dioxide layer 34.
A layer of photoresist material 38 is then deposited over the surface of the structure shown in FIG. 2b and patterned and developed in a conventional manner to provide the pattern shown in FIG. 2c. The pattern of the photoresist 38 corresponds to the desired pattern of lines which will be etched in the underlying metal layer 32 as will become apparent presently.
The silicon nitride pads 36 have been intentionally made slightly wider than the width of the photoresist pattern material 38 so as to provide a self-aligning feature which is well known in the art. At this point the excess nitride 36 is trimmed in an AME Hexode tool using CHF3 at 75 sccm, and O2 at 10 sccm, carried out at a power of 800 watts. This provides the structure shown in FIG. 2d.
At this point the structure is etched using the undeveloped photoresist pattern 38 as a mask, the etching first being through the exposed silicon dioxide 34 down to the exposed metal layer 32 and thereafter the aluminum metal layer 32 is etched so as to reveal the underlying tungsten 31 and provide a line pattern as shown in FIG. 2e. This etching takes place by the following process: First the SIO2 is etched as previously described until it is completely removed to expose the aluminum metal. The aluminum is etched in an AME 8300 tool using a multi-step process as follows:
first in CF4 at 40 sccm, carried out at a pressure of 25 millitorr with a D.C. bias of 25 volts;
thereafter in BCl3 at 140 sccm, Cl2, at 30 sccm, CH3 at 15 sccm, and CH4 at 15 sccm, carried out at a pressure of 30 millitorr and a D.C. bias of -160 volts until the unmasked aluminum is removed.
At this point the remaining photoresist 38 is stripped away. The silicon dioxide which underlies the photoresist but which is not covered by the Si3 N4 pads 36 is removed by etching as previously described, the pads 36 acting as etch marks on the SiO2 layer 34 and the tungsten 31 acting as an etch mask on the SiO2 layer 30. The tungsten 31 is then removed by any suitable means, such as by reactive ion etching in a suitable gas such as SF6 at a rate of 150 nm per minute. This will provide the structure as shown in FIG. 2f. At this stage in the process underlying aluminum metal lines 32 have disposed thereon stanchions 40, two of which are shown in FIG. 2f, each stanchions being comprised of a silicon nitride layer 36 and a silicon dioxide layer 34.
Removable material 41 such as parylene is deposited(as previously described) onto the surface of the substrate 30 so that it fills between the metal lines 32 and around the stanchions 40, and is planarized back as previously described to the structure shown in FIG. 2g. (The silicon nitride need not remain after this point in the process, and if desired can be removed as a part of the planarization operation using conventional techniques as previously described.)
A cap layer 42 of silicon dioxide is then blanket deposited on top of the structure shown in FIG. 2h. A layer of photo resist is deposited on the cap layer 42 and patterned and developed as described in the previous embodiment to provide for the necessary via and access openings. Via openings, one of which is shown at 44, and access opeinings 46, are etched through the silicon dioxide cap layer 42 by the technique as previously described, the via openings being located above the stanchions 40 and the removal or access openings 46 being located above the removable material 41 and the photoresist material removed to provide the structure as shown in FIG. 2i. It should be noted that the etching of the via hole 44 proceeds through both the oxide cap material 42 and the silicon nitride 36 and the underlying oxide material 34 to the metal 32. This etching process is carried out in an AME 8100 etching tool wherein the SiO2 is first etched as previously described to remove the SiO2 revealing the silicon nitride. The silicon nitride is then etched in an AME Hexode tool as previously described to reveal the SiO2. This final layer of SiO2 is etched as previously described to reveal the underlying aluminum lines.
As in the previously described embodiment, metal 48 is deposited into the via 44 to provide an interconnection which preferably is tungsten as previously described and shown in FIG. 2j. The material 41 is then removed as previously described. It the material is parylene it is removed by heating the structure in an O2 atmosphere at about 200° C. or less until the material is removed as shown in FIG. 2k providing spaces 50 between the lines 32 and between the base 30 and cap 42. If the material is spun on glass it can be etched out by a solution of 100 parts HNO3, 100 parts H2 O, and 1 part HF. If other material is used it can be suitable removed by selecting enchants that do not significantly react either with the silicon dioxide, or the silicon nitride or the metal.
The structure is then subjected to a CVD silicon dioxide deposition as previously described to close the access openings 46 and provide a layer 52 on top of cap 42 which when done at a pressure of 100 millitorr will result in a relatively low pressure spaces 50 as shown in FIG. 2l. The layer 52 is then etched back as previously described to provide the resulting structure shown in FIG. 2m.
This particular embodiment is particularly adapted not only for use with intralayer insulation but also interlayer insulation in that there is provided a plurality of stanchions or supports 40 separating the base layer 30 and cap layer 42, which stanchions are comprised of a layer of silicon dioxide and silicon nitride overlying the metal lines 32 thus increasing the space 50 constituting the space between the layer 32 and the cap 42.
While several embodiments of this invention have been shown and described, various adaptations and modifications can be made without departing from the scope of the invention as defined in the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3689992 *||Aug 2, 1965||Sep 12, 1972||Telefunken Patent||Production of circuit device|
|US3890636 *||Sep 11, 1972||Jun 17, 1975||Hitachi Ltd||Multilayer wiring structure of integrated circuit and method of producing the same|
|US3925880 *||Jun 18, 1973||Dec 16, 1975||Signetics Corp||Semiconductor assembly with beam lead construction and method|
|US3932226 *||Dec 6, 1974||Jan 13, 1976||Rca Corporation||Method of electrically interconnecting semiconductor elements|
|US4289846 *||Dec 28, 1979||Sep 15, 1981||General Electric Company||Process for forming low-reactance interconnections on semiconductors|
|US4849071 *||Dec 9, 1987||Jul 18, 1989||Spectrol Reliance Limited||Method of forming a sealed diaphragm on a substrate|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5308440 *||Sep 2, 1992||May 3, 1994||Matsushita Electric Industrial Co., Ltd.||Method of making semiconductor device with air-bridge interconnection|
|US5407860 *||May 27, 1994||Apr 18, 1995||Texas Instruments Incorporated||Method of forming air gap dielectric spaces between semiconductor leads|
|US5422590 *||Apr 26, 1994||Jun 6, 1995||Texas Instruments Incorporated||High voltage negative charge pump with low voltage CMOS transistors|
|US5432128 *||May 27, 1994||Jul 11, 1995||Texas Instruments Incorporated||Reliability enhancement of aluminum interconnects by reacting aluminum leads with a strengthening gas|
|US5461003 *||May 27, 1994||Oct 24, 1995||Texas Instruments Incorporated||Multilevel interconnect structure with air gaps formed between metal leads|
|US5470802 *||May 20, 1994||Nov 28, 1995||Texas Instruments Incorporated||Method of making a semiconductor device using a low dielectric constant material|
|US5472913 *||Aug 5, 1994||Dec 5, 1995||Texas Instruments Incorporated||Method of fabricating porous dielectric material with a passivation layer for electronics applications|
|US5476817 *||May 31, 1994||Dec 19, 1995||Texas Instruments Incorporated||Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers|
|US5488015 *||May 20, 1994||Jan 30, 1996||Texas Instruments Incorporated||Method of making an interconnect structure with an integrated low density dielectric|
|US5494858 *||Jun 7, 1994||Feb 27, 1996||Texas Instruments Incorporated||Method for forming porous composites as a low dielectric constant layer with varying porosity distribution electronics applications|
|US5510293 *||May 31, 1994||Apr 23, 1996||Texas Instruments Incorporated||Method of making reliable metal leads in high speed LSI semiconductors using thermoconductive layers|
|US5512775 *||Jun 7, 1995||Apr 30, 1996||Texas Instruments Incorporated||Low dielectric constant insulation in VLSI applications|
|US5519250 *||Jun 7, 1995||May 21, 1996||Numata; Ken||Reliability of metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers|
|US5523615 *||Jun 7, 1995||Jun 4, 1996||Texas Instruments Incorporated||Porous dielectric material with improved pore surface properties for electronics applications|
|US5525857 *||Aug 19, 1994||Jun 11, 1996||Texas Instruments Inc.||Low density, high porosity material as gate dielectric for field emission device|
|US5561318 *||Jun 7, 1995||Oct 1, 1996||Texas Instruments Incorporated||Porous composites as a low dielectric constant material for electronics applications|
|US5569058 *||Jun 5, 1995||Oct 29, 1996||Texas Instruments Incorporated||Low density, high porosity material as gate dielectric for field emission device|
|US5625232 *||Jul 15, 1994||Apr 29, 1997||Texas Instruments Incorporated||Reliability of metal leads in high speed LSI semiconductors using dummy vias|
|US5661344 *||Jun 7, 1995||Aug 26, 1997||Texas Instruments Incorporated||Porous dielectric material with a passivation layer for electronics applications|
|US5668398 *||Apr 12, 1996||Sep 16, 1997||Texas Instruments Incorporated||Multilevel interconnect structure with air gaps formed between metal leads|
|US5670828 *||Feb 21, 1995||Sep 23, 1997||Advanced Micro Devices, Inc.||Tunneling technology for reducing intra-conductive layer capacitance|
|US5675187 *||May 16, 1996||Oct 7, 1997||Texas Instruments Incorporated||Reliability of metal leads in high speed LSI semiconductors using dummy vias|
|US5723368 *||Jun 7, 1995||Mar 3, 1998||Cho; Chi-Chen||Porous dielectric material with improved pore surface properties for electronics applications|
|US5728628 *||Feb 26, 1996||Mar 17, 1998||Texas Instruments Incorporated||Two-step metal etch process for selective gap fill of submicron inter-connects and structure for same|
|US5747880 *||Nov 18, 1996||May 5, 1998||Texas Instruments Incorporated||Interconnect structure with an integrated low density dielectric|
|US5751056 *||Jun 7, 1995||May 12, 1998||Texas Instruments Incorporated||Reliable metal leads in high speed LSI semiconductors using dummy leads|
|US5751066 *||Aug 22, 1995||May 12, 1998||Texas Instruments Incorporated||Structure with selective gap fill of submicron interconnects|
|US5789819 *||Jun 7, 1995||Aug 4, 1998||Texas Instruments Incorporated||Low dielectric constant material for electronics applications|
|US5801092 *||Sep 4, 1997||Sep 1, 1998||Ayers; Michael R.||Method of making two-component nanospheres and their use as a low dielectric constant material for semiconductor devices|
|US5804508 *||Oct 23, 1996||Sep 8, 1998||Texas Instruments Incorporated||Method of making a low dielectric constant material for electronics|
|US5811352 *||Nov 6, 1996||Sep 22, 1998||Texas Instruments Incorporated||Method of making reliable metal leads in high speed LSI semiconductors using dummy leads|
|US5818110 *||Nov 22, 1996||Oct 6, 1998||International Business Machines Corporation||Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same|
|US5843836 *||Nov 6, 1996||Dec 1, 1998||Advanced Micro Devices, Inc.||Tunneling technology for reducing intra-conductive layer capacitance|
|US5847439 *||Jul 9, 1996||Dec 8, 1998||Micron Technology, Inc.||Integrated circuit having a void between adjacent conductive lines|
|US5861653 *||May 10, 1996||Jan 19, 1999||Nec Corporation||Semiconductor device having gaseous isolating layer formed in inter-level insulating layer and process of fabrication thereof|
|US5880018 *||Oct 7, 1996||Mar 9, 1999||Motorola Inc.||Method for manufacturing a low dielectric constant inter-level integrated circuit structure|
|US5882963 *||Aug 12, 1997||Mar 16, 1999||Siemens Aktiengesellschaft||Method of manufacturing semiconductor components|
|US5908318 *||Sep 17, 1997||Jun 1, 1999||Advanced Micro Devices, Inc.||Method of forming low capacitance interconnect structures on semiconductor substrates|
|US5936295 *||Mar 4, 1997||Aug 10, 1999||Texas Instruments Incorporated||Multilevel interconnect structure with air gaps formed between metal leads|
|US5965465 *||Sep 18, 1997||Oct 12, 1999||International Business Machines Corporation||Etching of silicon nitride|
|US6033996 *||Nov 13, 1997||Mar 7, 2000||International Business Machines Corporation||Process for removing etching residues, etching mask and silicon nitride and/or silicon dioxide|
|US6066267 *||Jun 29, 1999||May 23, 2000||International Business Machines Corporation||Etching of silicon nitride|
|US6083821 *||Oct 29, 1998||Jul 4, 2000||Micron Technology, Inc.||Integrated circuit having a void between adjacent conductive lines|
|US6090724 *||Dec 15, 1998||Jul 18, 2000||Lsi Logic Corporation||Method for composing a thermally conductive thin film having a low dielectric property|
|US6117796 *||Aug 13, 1998||Sep 12, 2000||International Business Machines Corporation||Removal of silicon oxide|
|US6150282 *||Nov 13, 1997||Nov 21, 2000||International Business Machines Corporation||Selective removal of etching residues|
|US6162838 *||Jun 4, 1999||Dec 19, 2000||Georgia Tech Research Corporation||Porous insulating compounds and method for making same|
|US6165890 *||Jan 21, 1998||Dec 26, 2000||Georgia Tech Research Corporation||Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections|
|US6200891||Aug 13, 1998||Mar 13, 2001||International Business Machines Corporation||Removal of dielectric oxides|
|US6277766||Feb 3, 2000||Aug 21, 2001||Michael Raymond Ayers||Method of making fullerene-decorated nanoparticles and their use as a low dielectric constant material for semiconductor devices|
|US6306753 *||Mar 14, 2000||Oct 23, 2001||Kabushiki Kaisha Toshiba||Feasible, gas-dielectric interconnect process|
|US6307265 *||Aug 15, 1996||Oct 23, 2001||Kabushiki Kaisha Toshiba||Feasible, gas-dielectric interconnect process|
|US6319852||Jan 20, 2000||Nov 20, 2001||Texas Instruments Incorporated||Nanoporous dielectric thin film formation using a post-deposition catalyst|
|US6319858 *||Jul 11, 2000||Nov 20, 2001||Nano-Architect Research Corporation||Methods for reducing a dielectric constant of a dielectric film and for forming a low dielectric constant porous film|
|US6329062||Feb 29, 2000||Dec 11, 2001||Novellus Systems, Inc.||Dielectric layer including silicalite crystals and binder and method for producing same for microelectronic circuits|
|US6355551||Mar 21, 2000||Mar 12, 2002||Micron Technology, Inc.||Integrated circuit having a void between adjacent conductive lines|
|US6380105||Jun 2, 1999||Apr 30, 2002||Texas Instruments Incorporated||Low volatility solvent-based method for forming thin film nanoporous aerogels on semiconductor substrates|
|US6437007||Apr 14, 2000||Aug 20, 2002||Texas Instruments Incorporated||Aerogel thin film formation from multi-solvent systems|
|US6498031||May 26, 2000||Dec 24, 2002||Oxidor Corporation, Inc.||Column reactor for testing and evaluating refractory ores|
|US6509386||Apr 5, 2000||Jan 21, 2003||Georgia Tech Research Corporation||Porous insulating compounds and method for making same|
|US6511859||Mar 10, 2000||Jan 28, 2003||California Institute Of Technology||IC-compatible parylene MEMS technology and its application in integrated sensors|
|US6576848||Nov 22, 1996||Jun 10, 2003||International Business Machines Corporation||Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same|
|US6576976||Feb 22, 2001||Jun 10, 2003||Integrated Device Technology, Inc.||Semiconductor integrated circuit with an insulation structure having reduced permittivity|
|US6610593||Aug 31, 2001||Aug 26, 2003||Georgia Tech Research Corporation||Fabrication of semiconductor device with air gaps for ultra low capacitance interconnections and methods of making same|
|US6614097||Sep 30, 1998||Sep 2, 2003||Lsi Logic Corporation||Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device|
|US6645878||Apr 30, 2002||Nov 11, 2003||Texas Instruments Incorporated||Low volatility solvent-based method for forming thin film nanoporous aerogels on semiconductor substrates|
|US6710538||Aug 26, 1998||Mar 23, 2004||Micron Technology, Inc.||Field emission display having reduced power requirements and method|
|US6806181 *||Mar 19, 2002||Oct 19, 2004||Fujitsu Quantum Devices Limited||Method of fabricating an air bridge|
|US6821554||Jan 8, 2001||Nov 23, 2004||Texas Instruments Incorporated||Polyol-based method for forming thin film aerogels on semiconductor substrates|
|US6835111||Nov 26, 2001||Dec 28, 2004||Micron Technology, Inc.||Field emission display having porous silicon dioxide layer|
|US6888249||Aug 25, 2003||May 3, 2005||Georgia Tech Research Corporation||Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnections and methods of making same|
|US6946382||Apr 1, 2003||Sep 20, 2005||Dow Global Technologies Inc.||Process for making air gap containing semiconducting devices and resulting semiconducting device|
|US6953375||Mar 29, 2004||Oct 11, 2005||Micron Technology, Inc.||Manufacturing method of a field emission display having porous silicon dioxide insulating layer|
|US6995439 *||Mar 17, 2004||Feb 7, 2006||Novellus Systems, Inc.||Method of fabricating low dielectric constant dielectric films|
|US7042148||Feb 26, 2004||May 9, 2006||Micron Technology, Inc.||Field emission display having reduced power requirements and method|
|US7256127||Sep 13, 2003||Aug 14, 2007||Shipley Company, L.L.C.||Air gap formation|
|US7504699||Nov 21, 2000||Mar 17, 2009||George Tech Research Corporation||Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections|
|US7510959 *||Mar 16, 2005||Mar 31, 2009||Interuniversitair Microelektronica Centrum (Imec)||Method of manufacturing a semiconductor device having damascene structures with air gaps|
|US7531209||Feb 24, 2005||May 12, 2009||Michael Raymond Ayers||Porous films and bodies with enhanced mechanical strength|
|US7541277||Apr 30, 2008||Jun 2, 2009||International Business Machines Corporation||Stress relaxation, selective nitride phase removal|
|US7585785||Jan 30, 2004||Sep 8, 2009||Dow Global Technologies||Sacrificial benzocyclobutene copolymers for making air gap semiconductor devices|
|US7598114||Jan 30, 2004||Oct 6, 2009||Dow Global Technologies Inc.||Sacrificial benzocyclobutene/norbornene polymers for making air gap semiconductor devices|
|US7723850||Aug 13, 2007||May 25, 2010||Rohm And Haas Electronic Materials Llc||Electronic devices having air gaps|
|US7790234||May 31, 2007||Sep 7, 2010||Michael Raymond Ayers||Low dielectric constant materials prepared from soluble fullerene clusters|
|US7875315||May 31, 2007||Jan 25, 2011||Roskilde Semiconductor Llc||Porous inorganic solids for use as low dielectric constant materials|
|US7883742||Feb 8, 2011||Roskilde Semiconductor Llc||Porous materials derived from polymer composites|
|US7919188||May 31, 2007||Apr 5, 2011||Roskilde Semiconductor Llc||Linked periodic networks of alternating carbon and inorganic clusters for use as low dielectric constant materials|
|US8034890||Oct 11, 2011||Roskilde Semiconductor Llc||Porous films and bodies with enhanced mechanical strength|
|US20010041459 *||Jan 8, 2001||Nov 15, 2001||Smith Douglas M.||Polyol-based method for forming thin film aerogels on semiconductor substrates|
|US20020140007 *||Mar 19, 2002||Oct 3, 2002||Fujitsu Quantum Devices Limited||Semiconductor device and method for fabricating the same|
|US20040038513 *||Aug 25, 2003||Feb 26, 2004||Kohl Paul Albert||Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnections and methods of making same|
|US20040075159 *||Oct 17, 2002||Apr 22, 2004||Nantero, Inc.||Nanoscopic tunnel|
|US20040077107 *||Oct 17, 2002||Apr 22, 2004||Nantero, Inc.||Method of making nanoscopic tunnel|
|US20040087162 *||Oct 17, 2002||May 6, 2004||Nantero, Inc.||Metal sacrificial layer|
|US20040137728 *||Sep 13, 2003||Jul 15, 2004||Shipley Company, L.L.C.||Air gap formation|
|US20040169453 *||Feb 26, 2004||Sep 2, 2004||Ahn Kie Y.||Field emission display having reduced power requirements and method|
|US20040189175 *||Mar 29, 2004||Sep 30, 2004||Ahn Kie Y.||Field emission display having reduced power requirements and method|
|US20050124172 *||Apr 1, 2003||Jun 9, 2005||Townsend Iii Paul H.||Process for making air gap containing semiconducting devices and resulting semiconducting device|
|US20050215047 *||Mar 16, 2005||Sep 29, 2005||Roel Daamen||Method of manufacturing a semiconductor device having damascene structures with air gaps|
|US20060152134 *||Mar 7, 2006||Jul 13, 2006||Micron Technology, Inc.||Field emission display having reduced power requirements and method|
|US20060185794 *||Feb 24, 2005||Aug 24, 2006||Ayers Michael Raymond||Porous films and bodies with enhanced mechanical strength|
|US20060246681 *||Jan 30, 2004||Nov 2, 2006||Youngfu Li||Sacrificial benzocyclobutene/norbornene polymers for making air gap semiconductor devices|
|US20060292892 *||Jan 30, 2004||Dec 28, 2006||Kirchhoff Robert A||Sacrificial benzocyclobutene copolymers for making air gap semiconductor devices|
|US20070292700 *||May 31, 2007||Dec 20, 2007||Roskilde Semiconductor Llc||Porous materials derived from polymer composites|
|US20080020197 *||May 31, 2007||Jan 24, 2008||Roskilde Semiconductor Llc||Porous inorganic solids for use as low dielectric constant materials|
|US20080038518 *||Aug 13, 2007||Feb 14, 2008||Shipley Company, L.L.C.||Air gap formation|
|US20080044642 *||May 31, 2007||Feb 21, 2008||Roskilde Semiconductor, Llc||Low dielectric constant materials prepared from soluble fullerene clusters|
|US20090192281 *||Apr 3, 2009||Jul 30, 2009||Michael Raymond Ayers||Porous Films and Bodies with Enhanced Mechanical Strength|
|US20140322910 *||Jul 15, 2014||Oct 30, 2014||Taiwan Semiconductor Manufacturing Company, Ltd.||Via-free interconnect structure with self-aligned metal line interconnections|
|DE102005004376A1 *||Jan 31, 2005||Aug 10, 2006||Infineon Technologies Ag||Semiconductor memory device e.g. high-density chain-ferroelectric RAM, has capacitor arrangement with capacitors serving as memory units, where memory units and capacitors are separated from each other by insulation area|
|EP0684642A1||May 19, 1995||Nov 29, 1995||Texas Instruments Incorporated||Method of fabrication of a porous dielectric layer for a semiconductor device|
|EP0687004A1||Jun 7, 1995||Dec 13, 1995||Texas Instruments Incorporated||Method for fabrication of dielectrics on semiconductor devices|
|EP0688052A2||May 17, 1995||Dec 20, 1995||Texas Instruments Incorporated||Improvements in or relating to fabrication of semiconductor devices|
|EP0692824A2||Jul 14, 1995||Jan 17, 1996||Texas Instruments Incorporated||Improvements in and relating to semiconductor devices|
|WO2000054312A1 *||Mar 10, 2000||Sep 14, 2000||California Institute Of Technology||Ic-compatible parylene mems technology and its application in integrated sensors|
|U.S. Classification||438/619, 438/703, 216/17, 438/702, 257/E21.581, 257/E23.144|
|International Classification||H01L21/768, H01L23/522|
|Cooperative Classification||H01L2924/0002, H01L23/5222, H01L21/7682|
|European Classification||H01L23/522C, H01L21/768B6|
|Dec 16, 1988||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, A COR
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:KAANTA, CARTER W.;ROBERTS, STANLEY;REEL/FRAME:005009/0272;SIGNING DATES FROM 19881215 TO 19881216
|Aug 25, 1994||SULP||Surcharge for late payment|
|Aug 25, 1994||FPAY||Fee payment|
Year of fee payment: 4
|Aug 30, 1994||REMI||Maintenance fee reminder mailed|
|Aug 18, 1998||REMI||Maintenance fee reminder mailed|
|Jan 24, 1999||LAPS||Lapse for failure to pay maintenance fees|
|Apr 6, 1999||FP||Expired due to failure to pay maintenance fee|
Effective date: 19990122