|Publication number||US5057883 A|
|Application number||US 07/463,478|
|Publication date||Oct 15, 1991|
|Filing date||Jan 11, 1990|
|Priority date||May 10, 1989|
|Also published as||DE4015067A1, DE4015067C2|
|Publication number||07463478, 463478, US 5057883 A, US 5057883A, US-A-5057883, US5057883 A, US5057883A|
|Original Assignee||Mitsubishi Denki Kabushiki Kaisha|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Non-Patent Citations (8), Referenced by (34), Classifications (14), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a permeable base transistor (hereinafter, referred to as PBT) and, more particularly, to a structure where a channel current flows in a direction transverse to the substrate thickness.
FIG. 2(a) shows a cross-sectional view of a prior art buried type PBT. In FIG. 2(a), reference numeral 3 designates a source (emitter) n+ semiconductor layer. An n+ substrate or an epitaxially grown layer is used for this source layer 3. A channel layer 1 is epitaxially grown on the source n+ semiconductor layer 3. A drain (collector) n+ semiconductor layer 4 is disposed on the channel layer 1. Gates (bases) 2 comprising a grating of a Schottky barrier metal are arranged centrally in the channel layer 1. Gate depletion layers are broadened in a region at the neighborhood of gates 2 during transistor operation.
FIGS. 2(b) and 2(c) show cross-sectional views of a prior art dug side wall type PBT and a prior art dug edge type PBT, respectively. In the digged side wall type PBT in FIG. 2(b), grooves reaching the central portion of channel layer 1 from the surface of drain layer 4 are produced and gates 2 are disposed in the grooves. In the dug edge type PBT shown in FIG. 2(c), gates 2 are disposed in the grooves and the gates 2 are processed to produce a trapezoidal cross-sectional configuration.
Although the cross-sectional structures of above-described PBTs are different from each other, in all PBTs, the base region including a grating of thin-film Schottky metal gates and a current permeable channel portion, and the operating current (channel current) flows in the vertical direction, that is, transverse to the substrate thickness.
The main operation thereof is as follows. When an input control signal is applied to the Schottky metal gate as a base, the gate depletion layer is modulated, whereby the gate current at the channel is modulated.
These PBTs have operational characteristics as in the following.
1) Since the base region is a longitudinal type structure in which the channel current flows in the substrate thickness direction, the thickness of the gate metal corresponds to the gate length, whereby quite short gate lengths of about 0.1 micron can be easily realized. A super high frequency operation is expected in the device of such a longitudinal type structure.
2) Since the active layer between the drain and source layer is produced by an epitaxial growth method, the film thickness is as thin as about 0.2 to 0.5 microns. In a compound semiconductor including charge carriers having a small effective mass, such as GaAs, ballistic electronic conduction arises in such thin active layer, thereby reducing gate propagation delay. This results in super high speed operation.
3) Since the input control signal is applied to the gate depletion layer capacitance through the gate metal, the loss due to parasitic resistances is less than with bipolar transistors in which the input control signal is applied through the base.
4) In a structure where the n+ substrate is used for the source n+ layer, grounding with a quite small amount of inductance can be realized, thereby resulting in a transistor which is suitable for a high frequency and high power operation.
In the prior art longitudinal type PBT structure, however, since the gate electrode 2 is positioned at the central portion of the channel layer 1 as an epitaxial growth layer as shown in FIG. 2(a), the quality of semiconductor crystal is poorer at the upper half portion of channel layer 1, resulting in difficulty in increasing the breakdown voltage. Furthermore, in the PBT structures shown in FIGS. 2(b) and 2(c), although the deterioration of crystallinity is not a great problem because no semiconductor layer is disposed on the gate electrode 2, separation of the gate electrode 2 from the drain electrode 4 is structurally difficult.
It is an object of the present invention to provide a permeable base transistor preventing the deterioration of the quality of the semiconductor crystal in the neighborhood of the gate (base) electrode, and appropriate for producing a transistor structure with high controllability and reproducibility.
Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
According to an aspect of the present invention, a permeable base transistor is provided with a source n+ layer and a drain n+ layer which are disposed in a semi-insulating semiconductor layer perpendicular to the thickness direction of the semi-insulating and a layer gate electrode grating is disposed between the source and drain n+ layers, thereby enabling the flow of an operational current in the transverse direction, that is, in the direction perpendicular to the substrate thickness. Therefore, a channel layer can be produced without growing an epitaxial layer on the gate electrode as in the prior art longitudinal type PBT structure, and deterioration of the crystallinity of the epitaxially grown channel layer in the neighborhood of gate electrode is prevented.
Furthermore, since the drain layer and the gate electrode are arranged in a longitudinal direction with a predetermined distance therebetween, there is no necessity of separating the gate electrode and the drain electrode in the transverse direction, thereby avoiding the problem that the gate electrode and the drain electrode cannot be completely separated. This results in an enhancement of transistor performance and production yield.
FIGS. 1(a) to 1(c) are a plan view and two cross-sectional views of a PBT according to a first embodiment of the present invention;
FIGS. 2(a) to 2(c) are diagrams showing cross-sectional views of prior art PBT structures, respectively;
FIGS. 3(a) to 3(h) are cross-sectional views and FIG. 3(i) is a plan view of process steps for producing the PBT embodiment of FIG. 1; and
FIG. 4 is a diagram showing a plan view of a PBT according to a second embodiment of the present invention.
An embodiment of the present invention will be described in detail with reference to the drawings.
FIGS. 1(a) to 1(c) show a PBT according to a first embodiment of the present invention. FIG. 1(a) shows a plan view of the PBT, the FIG. 1(b) shows a cross-section taken along line Ib--Ib' parallel to the channel direction of FIG. 1(a), and FIG. 1(c) shows a cross-section taken along line Ic--Ic' perpendicular to the channel direction of FIG. 1(a). In FIG. 1, reference numeral 100 designates a semi-insulating GaAs substrate having a charge carrier concentration of 1014 to 1016 cm-3 at most. A source n+ region 3 and a drain n+ region 4 are disposed in the substrate 100 opposing each other. A buried gate (base) electrode 2 of a finger configuration a metal or low resistance semiconductor layer is disposed in a region between the source and drain n+ regions 3 and 4. The finger configuration includes metal gate fingers with intervening apertures, the current permeable apertures of the PBT. A source electrode 5 and a drain electrode 6 are disposed on the source n+ region 3 and the drain n+ region 4, respectively. A gate contacting electrode 7 is disposed opposite the substrate 1 and connected with the buried gate electrode 2. Spaces 8 may be disposed between adjacent gate buried electrodes 2 as shown in FIG. 1(c) so that the gate contacting electrode 7 does not directly contact the substrate 1. These spaces 8 are not necessarily required.
The buried gate electrodes 2 extend over several hundred microns length with intervals of about 0.1 to 10 microns between adjacent electrodes, along the longitudinal direction of the source and drain regions. The gate length is less than 0.5 micron (5000 angstroms). The depth of the source and drain n+ layers 3 and 4 are more than several microns so that the driving current is equivalent to that of the prior art longitudinal type PBT structure.
In the PBT structure of this embodiment, although the principal of operation is the same as that of the prior art PBT, the channel current flows between the source n+ layer 3 and the drain n+ layer 4 in the direction transverse to the substrate thickness.
The production method of the PBT of this embodiment will be described with reference to FIG. 3(a) to 3(i).
First of all, as shown in FIG. 3(a), a first insulating film is deposited on the entire surface of a semi-insulating GaAs substrate 100 and is patterned with the first photoresist film 9, thereby producing an insulating pattern 10 for producing source and drain n+ layers. The width of the pattern 10 is established such that the interval between the source and drain n+ layers 3 and 4 is less than about 0.5 micron.
Next, as shown in FIG. 3(b), the GaAs substrate 100 is selectively etched in excess of several microns using the insulating film pattern 10 as a mask. Thereafter, as shown in FIG. 3(c), the source and drain n+ layers 3 and 4 are epitaxially grown in the etched portion 1a. Subsequently thereto, as shown in FIG. 3(d), a second insulating film 12 of a different kind from the insulating film pattern 10 is deposited on the entire surface. Then, the pattern 10 is removed which removes the second insulating film 12 which is disposed thereon, thereby selectively and self-aligningly leaving second insulating film 12 on the n+ epitaxial layers 3 and 4.
Next, as shown in FIG. 3(e), a third insulating film 20 of the same kind as the insulating film pattern 10 is deposited on the entire surface. Then, as shown in FIG. 3(f), the insulating film 20 is etched to level side walls 20a at the side walls of the insulating film 12 on the epitaxial layers 3 and 4. The GaAs surface is exposed at 1b to a width below 0.5 micron (typically below 0.1 micron width) self-alignedly between the side walls 20a between insulating films 12. Thereafter, a second photoresist film 13 is deposited on the entire surface, and is patterned to produce an aperture 13a having larger width than the exposed portion 1b of substrate 100. This photoresist pattern 13 includes portions 13b, as shown in FIG. 3(i), that result in the spaces 8 in the PBT as shown in FIG. 1(c).
Next, as shown in FIG. 3(g), the GaAs exposure portions 1b, regions for burying the gate electrode material, are etched to more than several microns in depth to produce pits 1c. A gate metal is selectively deposited in the pits 1c by sputtering, or vapor deposition. Thereafter, a gate contacting electrode metal 7 is deposited by sputtering or vapor deposition using the photoresist film 13 as a mask. Finally, as shown in FIG. 3(h), the second insulating film 12 and the side walls 20a are removed, and a source electrode 5 and a drain electrode 6 are self-alignedly produced using a evaporation method.
The PBT of this embodiment is substantially different from the prior art PBT in that the source region 3, the drain region 4, and the gate buried electrodes 2 are arranged such that the channel current flows in a direction transverse the substrate thickness. By adopting such arrangement, the buried gate electrodes 2 can be produced in the pits 1c of the substrate 100, and a channel layer is not an epitaxial layer on the buried gate electrode but a semi-insulating bulk crystalline substrate. Therefore, since there is no necessity of producing an epitaxial growth channel layer on a gate, the deterioration of crystallinity in the neighborhood of the gate, that is, the characteristic deterioration due to the epitaxial growth is absent. This results in a higher performance PBT having a higher breakdown voltage and producing ballistic electronic conduction.
Furthermore, since the drain layer and the gate electrode are arranged in a longitudinal direction relative to the substrate with a predetermined distance therebetween, faulty separation between the gate electrode and the drain electrode can be avoided, thereby improving the controllability of the production of the PBT.
Furthermore, since this PBT has a transverse type structure, the production process is compatible with that of FETS. That is, there is a high possibility of realizing an IC in which both a PBT and FET are fabricated.
While in the above-illustrated embodiment, the gate contacting electrode is after producing the buried gate, the gate electrode and the contacting buried gate may be produced at the same time. Furthermore, the substrate is not restricted to GaAs, and other III-V group compounds such as InP or InGaAs having high carrier mobility, or Si may be used. As the semiconductor layer, an epitaxial growth layer having a carrier concentration of less than 1014 cm-3 which is grown on the substrate may be used instead of the above-described substrate.
The plan arrangement of the source/drain layers and the gate electrode is not restricted to that shown in FIG. 1(a). Another arrangement is shown in FIG. 4. In FIG. 4, reference numeral 3 designates an annular source n+ region disposed in a semi-insulating semiconductor substrate 100. Buried gate buried 2 are inwardly spaced from the internal line boundary of the source n+ region 3. A cylindrical drain n+ region 4 is disposed inside the buried gate electrodes 2. Reference numerals 5 and 6 designate a source electrode and a drain electrode, respectively. In this second embodiment, the same advantages as those of the above-described first embodiment are achieved.
As is evident from the foregoing description, according to the present invention, since a source layer, a drain layer, and a gate electrode are arranged such that the channel current flows transverse to the substrate thickness, an epitaxial growth for producing a channel layer on the buried (base) gate electrode is unnecessary, thereby avoiding deterioration of the crystallinity of the channel layer. This results in a higher performance PBT having a high breakdown voltage and a superior ballistic conductivity.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4463366 *||Jun 20, 1980||Jul 31, 1984||Nippon Telegraph & Telephone Public Corp.||Field effect transistor with combination Schottky-junction gate|
|US4583107 *||Aug 15, 1983||Apr 15, 1986||Westinghouse Electric Corp.||Castellated gate field effect transistor|
|US4724223 *||Dec 11, 1986||Feb 9, 1988||Gte Laboratories Incorporated||Method of making electrical contacts|
|1||Adachi et al, "A New Gate . . . FET", IEEE Electron Device Letters, vol. EDL-6, No. 6, Jun. 1985, pp. 264-266.|
|2||*||Adachi et al, A New Gate . . . FET , IEEE Electron Device Letters, vol. EDL 6, No. 6, Jun. 1985, pp. 264 266.|
|3||Howes et al, "Gallium Arsenide", John Wiley & Sons, 1986, pp. 420-421.|
|4||*||Howes et al, Gallium Arsenide , John Wiley & Sons, 1986, pp. 420 421.|
|5||Mishra et al, "Short-Channel Effects . . . Investigation", IEEE Electron Device Letters, vol. EDL-4, No. 4, Apr. 1983, pp. 125-127.|
|6||*||Mishra et al, Short Channel Effects . . . Investigation , IEEE Electron Device Letters, vol. EDL 4, No. 4, Apr. 1983, pp. 125 127.|
|7||Rathman et al, "The Effect of Base-Schottky . . . Performance", IEEE Electron Device Letters, vol. EDL-5, No. 6, Jun. 1984, pp. 191-193.|
|8||*||Rathman et al, The Effect of Base Schottky . . . Performance , IEEE Electron Device Letters, vol. EDL 5, No. 6, Jun. 1984, pp. 191 193.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5220186 *||Dec 5, 1991||Jun 15, 1993||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device with a mushroom-shaped gate electrode|
|US5270556 *||Jul 30, 1992||Dec 14, 1993||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device with upper and lower gate electrode structure|
|US5288654 *||Feb 8, 1993||Feb 22, 1994||Mitsubishi Denki Kabushiki Kaisha||Method of making a mushroom-shaped gate electrode of semiconductor device|
|US5369044 *||Jul 20, 1993||Nov 29, 1994||Mitsubishi Denki Kabushiki Kaisha||Method for producing a semiconductor device|
|US6020607 *||Feb 20, 1996||Feb 1, 2000||Nec Corporation||Semiconductor device having junction field effect transistors|
|US6574130||Jul 25, 2001||Jun 3, 2003||Nantero, Inc.||Hybrid circuit having nanotube electromechanical memory|
|US6643165||Jul 25, 2001||Nov 4, 2003||Nantero, Inc.||Electromechanical memory having cell selection circuitry constructed with nanotube technology|
|US6706402||Apr 23, 2002||Mar 16, 2004||Nantero, Inc.||Nanotube films and articles|
|US6759693||Jun 19, 2002||Jul 6, 2004||Nantero, Inc.||Nanotube permeable base transistor|
|US6774052||Jun 19, 2002||Aug 10, 2004||Nantero, Inc.||Method of making nanotube permeable base transistor|
|US6784028||Dec 28, 2001||Aug 31, 2004||Nantero, Inc.||Methods of making electromechanical three-trace junction devices|
|US6835591||Apr 23, 2002||Dec 28, 2004||Nantero, Inc.||Methods of nanotube films and articles|
|US6836424||Mar 5, 2003||Dec 28, 2004||Nantero, Inc.||Hybrid circuit having nanotube electromechanical memory|
|US6911682||Dec 28, 2001||Jun 28, 2005||Nantero, Inc.||Electromechanical three-trace junction devices|
|US6919592||Jul 25, 2001||Jul 19, 2005||Nantero, Inc.||Electromechanical memory array using nanotube ribbons and method for making same|
|US6942921||Feb 11, 2004||Sep 13, 2005||Nantero, Inc.||Nanotube films and articles|
|US6979590||Apr 15, 2004||Dec 27, 2005||Nantero, Inc.||Methods of making electromechanical three-trace junction devices|
|US7056758||May 20, 2004||Jun 6, 2006||Nantero, Inc.||Electromechanical memory array using nanotube ribbons and method for making same|
|US7120047||Oct 24, 2003||Oct 10, 2006||Segal Brent M||Device selection circuitry constructed with nanotube technology|
|US7176505||Mar 17, 2004||Feb 13, 2007||Nantero, Inc.||Electromechanical three-trace junction devices|
|US7264990||Dec 13, 2004||Sep 4, 2007||Nantero, Inc.||Methods of nanotubes films and articles|
|US7274078||Jun 22, 2005||Sep 25, 2007||Nantero, Inc.||Devices having vertically-disposed nanofabric articles and methods of making the same|
|US7298016||May 25, 2004||Nov 20, 2007||Nantero, Inc.||Electromechanical memory array using nanotube ribbons and method for making same|
|US7304357||Jul 29, 2005||Dec 4, 2007||Nantero, Inc.||Devices having horizontally-disposed nanofabric articles and methods of making the same|
|US7335395||Jan 13, 2003||Feb 26, 2008||Nantero, Inc.||Methods of using pre-formed nanotubes to make carbon nanotube films, layers, fabrics, ribbons, elements and articles|
|US7335528||Dec 8, 2004||Feb 26, 2008||Nantero, Inc.||Methods of nanotube films and articles|
|US7342818||Oct 13, 2004||Mar 11, 2008||Nantero, Inc.||Hybrid circuit having nanotube electromechanical memory|
|US7521736||Jun 15, 2006||Apr 21, 2009||Nantero, Inc.||Electromechanical three-trace junction devices|
|US7560136||Jan 13, 2003||Jul 14, 2009||Nantero, Inc.||Methods of using thin metal layers to make carbon nanotube films, layers, fabrics, ribbons, elements and articles|
|US7566478||Jan 13, 2003||Jul 28, 2009||Nantero, Inc.||Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles|
|US7745810||Feb 9, 2004||Jun 29, 2010||Nantero, Inc.||Nanotube films and articles|
|US7915066||Sep 2, 2008||Mar 29, 2011||Nantero, Inc.||Methods of making electromechanical three-trace junction devices|
|US8101976||Sep 11, 2007||Jan 24, 2012||Nantero Inc.||Device selection circuitry constructed with nanotube ribbon technology|
|US20030236000 *||Jun 19, 2002||Dec 25, 2003||Nantero, Inc.||Method of making nanotube permeable base transistor|
|U.S. Classification||257/287, 257/E29.243, 257/E21.406|
|International Classification||H01L21/335, H01L29/68, H01L21/285, H01L29/772, H01L29/80|
|Cooperative Classification||H01L29/66454, H01L29/7722, H01L21/28587|
|European Classification||H01L29/66M6T6E2, H01L29/772B, H01L21/285B6C|
|Jan 11, 1990||AS||Assignment|
Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:NODA, MINORU;REEL/FRAME:005215/0147
Effective date: 19891128
|Mar 28, 1995||FPAY||Fee payment|
Year of fee payment: 4
|Apr 8, 1999||FPAY||Fee payment|
Year of fee payment: 8
|Apr 30, 2003||REMI||Maintenance fee reminder mailed|
|Oct 15, 2003||LAPS||Lapse for failure to pay maintenance fees|
|Dec 9, 2003||FP||Expired due to failure to pay maintenance fee|
Effective date: 20031015