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Publication numberUS5059830 A
Publication typeGrant
Application numberUS 07/435,932
Publication dateOct 22, 1991
Filing dateNov 14, 1989
Priority dateNov 14, 1988
Fee statusPaid
Also published asEP0369405A2, EP0369405A3
Publication number07435932, 435932, US 5059830 A, US 5059830A, US-A-5059830, US5059830 A, US5059830A
InventorsTakeji Tokumaru, Tsuneaki Kudou, Kazuyuki Omote
Original AssigneeKabushiki Kaisha Toshiba
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated circuit using bus driver having reduced area
US 5059830 A
Abstract
A bus driver in which at least two P channel MOS transistors and at least two N channel MOS transistors are employed and these are respectively connected in series. A data signal is inputted into a gate of one of the P channel MOS transistors, an inverted input of an enable signal is inputted into a gate of the other of the P channel MOS transistors, the enable signal is inputted into a gate of one of the N channel MOS transistors and the data signal is also inputted into a gate of the other of the N channel MOS transistors. Further, an output signal is outputted from a connection point of the P channel MOS transistors and the N channel MOS transistors. Also disclosed is another embodiment of a bus driver in which an inverted signal of an enable signal is inputted into the other of the P channel MOS transistors through an inverter.
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Claims(3)
What is claimed is:
1. An integrated circuit bus driver for driving bus lines, the bus driver including a clocked inverter having two P channel MOS transistors and two N channel MOS transistors connected to one another in series, each bus driver having a data input terminal, a control terminal for inputting an enable signal, and an output terminal, comprising:
a plurality of bus drivers each having an output terminal;
a plurality of first bus lines for transferring data among the components of the integrated circuit; and
a plurality of second bus lines, for transferring data among the components of the integrated circuit, each of which are respectively coupled to the first bus lines;
wherein the output terminal of each bus driver is connected to one of the second bus lines.
2. A n integrated circuit according to claim 1, wherein the first bus lines are main bus lines, the second bus lines are internal bus lines, the internal bus lines being formed in a plurality of hierarchies, each of which comprises a plurality of internal bus lines, the bus drivers being used at least in one or more internal bus lines.
3. An integrated circuit according to claim 1, wherein the first bus lines are main bus lines, the second bus lines are internal bus lines and the bus drivers are used in the internal bus lines.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a bus driver integrated circuit for driving a bus, and particularly to a bus driver integrated circuit having a reduced integrated circuit area.

2. Description of the Prior Art

Generally, a bus driver which is used for bus driving in a microprocessor has sufficient driving ability for driving heavily loaded wiring. FIG. 1 is a compositional diagram of a bus driver 100 which is conventionally used. The bus driver 100 is so arranged that an enable signal E and a data signal A are inputted to input terminals of a NAND gate 101 and a NOR gate 102 respectively. Further, the enable signal E is also inputted to the NOR gate 102 through an inverter 103. An output terminal of the NAND gate 101 is connected to a gate electrode of a P channel MOS transistor (PMOS transistor) P1. The output terminal of the NOR gate 102 is connected to a gate electrode of an N channel MOS transistor (NMOS transistor) N1, and an output Z is obtained from a connection point of transistors P1 and N1. Reference character VDD designates a power source.

Accordingly, an output of the NAND gate 101 becomes 0 only when A is 1 and E is 1, and P1 becomes ON. While, an output of the NOR gate 102 becomes 1 only when A is 0 and E is 1, and N1 becomes ON. Thus, the bus driving is performed.

FIG. 2 is a compositional diagram of a bus driver system 200 in which is employed the bus driver 100. In the same diagram, the bus driver system 200 is used for an internal bus having relatively small wiring load. In the diagram, reference numerals 201, 202, 203, 204, 205, . . . , IN are respectively composed of the bus drivers 100, and these drive main buses 0, 1, . . . , n respectively.

More specifically, these bus drivers are respectively composed of the NAND gates 101, NOR gates 102 and inverters 103.

However, in the internal bus system having relatively small wiring load as shown in the same diagram, since the bus drivers 201, 202, 203, 204, 205, . . . , In respectively use bus drivers which are used for a bus system having large wiring load, it is difficult to reduce an area of a bus driver integrated circuit which employs such a bus driver system. Accordingly, an entire and actual pattern area of the integrated circuit becomes inevitably large.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a bus driver integrated circuit having a reduced actual pattern area.

To achieve the object, in the present invention, a bus driver integrated circuit has a plurality of bus drivers for controlling output into a main bus and an internal bus which is connected to the main bus. Further, the respective bus drivers are composed of clocked inverters comprising at last two P channel MOS transistors and at least two N channel MOS transistors so that data outputs are outputted into the internal bus in accordance with the presence of enable signals.

Namely, since these clocked inverters are not composed of NAND gates and NOR gates, a simple integrated circuit can be realized.

Accordingly, an area required for arrangement of these compositional elements in the integrated circuit can be reduced as compared with conventional circuits. Moreover, the gate delay caused on the bus drivers themselves can be also reduced.

These and other objects, features and advantages of the present invention will be more apparent from the following description of preferred embodiments, taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a compositional diagram of a bus driver which is conventionally used.

FIG. 2 is a compositional diagram of an internal bus system using the bus driver shown in FIG. 1.

FIG. 3 is a compositional diagram of a bus driver or clocked inverter which is an embodiment of the present invention.

FIG. 4 is a compositional diagram of a bus driver or clocked inverter which is another embodiment of the present invention.

FIG. 5 is a compositional diagram of an internal bus system using the clocked inverter shown in FIG. 3.

FIG. 6 is a compositional diagram of an internal bus system using the clocked inverter shown in FIG. 4.

FIG. 7 is a diagram to show the internal bus system shown in FIG. 5 at an actual pattern level.

FIG. 8 is an example of an actual pattern of an integrated circuit of the bus driver shown in FIG. 3.

FIG. 9 is an example of an actual pattern of an integrated circuit of the bus driver shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 is a compositional diagram of a bus driver which is an embodiment of the present invention. A first and a second P channel MOS transistor P1, P2 and a first and a second N channel MOS transistor N1, N2 are connected in series respectively, and a data signal or input A is supplied to a gate electrode of the first PMOS transistor P1 and a gate electrode of the second NMOS transistor N2, and an enable signal or input E and an inverted input E obtained by inversion of the input E through an inverter 301 are respectively supplied to a gate electrode of the second PMOS transistor P2. Moreover, an output Z is obtained from a connection point of the second PMOS transistor P2 and the first NMOS transistor N1.

Hereinafter, operation of the bus driver having the above mentioned composition of the present invention will be described.

When A is 1 and E is 1, the transistors N1 and N2 become ON, and the transistor P1 becomes OFF, and P2 becomes ON. When A is 0 and E is 1, P1, P2 and N1 become ON, and only N2 becomes OFF. While, when A is 1 and E is 0, P1, P2 and N1 become OFF, and only N2 becomes ON. Further, when A is 0 and E is 0, only P1 becomes ON and the others become OFF.

By the above-mentioned operation, the bus driver of this embodiment drives a main bus and an internal bus.

FIG. 4 is a compositional diagram of a bus driver which is another embodiment of the present invention. The bus driver or clocked inverter 400 has a composition in which the inverter 301 in the embodiment shown in FIG. 3 is removed, and an inverted enable signal EN of the enable signal E is directly inputted. In operation of the clocked inverter 400, only the MOS transistor P2 is on-off controlled in accordance with a low or high level of the inverted enable signal EN of the enable signal E. Since respective operation of the other transistors P1, N1 and N2 are the same as those in the case of the bus driver 300 shown in FIG. 3, explanations on them are omitted herein.

FIG. 5 is a compositional diagram of an internal bus system 500 using the bus driver 300 of the embodiment shown in FIG. 3.

In the embodiment, bus drivers 501, 502, . . . , N are respectively composed of the clocked inverters 300. Therefore the gate delay caused on the bus drivers 501, 502, . . . , N themselves can be also reduced. In operation of the internal bus system 500, when data DATA 0, DATA 1, DATA 2, DATA N are respectively inputted into the clocked inverters 501, 502, . . . , N, internal buses 0, 1, . . . . , n are respectively driven corresponding to control of the enable signal E.

FIG. 6 is a compositional diagram of an internal bus system 600 using the bus driver 400 of the embodiment shown in FIG. 4.

In the same diagram, bus drivers 601, 602, . . . , N are respectively composed of the clocked inverters 400. In operation of the internal bus system 600, when data DATA 0, DATA 1, DATA 2, . . . , DATA N are respectively inputted, internal buses 0, 1, N . . . , N are respectively driven corresponding to control of the enable signal E and the inverted enable signal EN. Since the operation is very similar to the embodiment of FIG. 5, it is not described in detail herein.

FIG. 7 shows an example in which the internal bus system shown in FIG. 5 is formed in an actual pattern on an integrated circuit. In the same diagram, reference numerals 701, 702,703, . . . , N respectively designate but drivers, and reference characters R1, R2, R3, . . . , RN respectively designate trunk terminals, further O1, O2, O3, . . . , ON are output lines of the respective bus drivers.

FIG. 8 shows an example of a pattern of an actual integrated circuit which comprises mounting the clocked inverter 300 shown in FIG. 3 on a chip.

In the same diagram, reference characters VSS, VDD designate power source terminals, and reference numeral 801 designates a terminal for output of the output Z of the clocked inverter 300, and 802 and 803 respectively designate a terminal for input of the data A and a terminal for input of the enable signal E.

FIG. 9 shows an example of a pattern of an actual integrated circuit which comprises mounting the conventional bus driver 100 on a chip.

In the same diagram, reference characters VSS, VDD designate power source terminals, and reference numeral 901 designates a terminal for output of the output Z of the bus driver 100, and 902 and 903 respectively designate a terminal for input of the data A and a terminal for input of the enable signal E.

In comparison of these actual patterns shown in FIGS. 8 and 9, it can be apparently seen that an area required for the bus driver 300 of the present invention is reduced into about a half of that in the conventional one.

Various modifications will become possible for those skilled in the are after receiving the teachings of the present disclosure without departing from the scope thereof.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4920282 *Jun 20, 1988Apr 24, 1990Kabushiki Kaisha ToshibaDynamic latch circuit for preventing short-circuit current from flowing during absence of clock pulses when under test
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5294845 *Aug 17, 1992Mar 15, 1994Motorola, Inc.Data processor having an output terminal with selectable output impedances
US5426383 *Apr 19, 1994Jun 20, 1995Hewlett Packard CompanyNCMOS - a high performance logic circuit
US5467455 *Nov 3, 1993Nov 14, 1995Motorola, Inc.Data processing system and method for performing dynamic bus termination
US5528166 *Mar 14, 1995Jun 18, 1996Intel CorporationPulse controlled impedance compensated output buffer
US5787291 *Feb 5, 1996Jul 28, 1998Motorola, Inc.Low power data processing system for interfacing with an external device and method therefor
US5859541 *Sep 15, 1993Jan 12, 1999Motorola, Inc.Data processor having an output terminal with selectable output impedances
US5951688 *Feb 17, 1998Sep 14, 1999Motorola, Inc.Low power data processing system for interfacing with an external device and method therefor
US6025739 *Apr 21, 1998Feb 15, 2000International Business Machines CorporationCMOS driver circuit for providing a logic function while reducing pass-through current
US6037816 *Apr 15, 1999Mar 14, 2000Matsushita Electric Industrial Co., Ltd.Signal transmitting circuit, signal receiving circuit, signal transmitting/receiving circuit, signal transmitting method, signal receiving method, signal transmitting/receiving method, semiconductor integrated circuit, and control method thereof
US6043683 *Sep 17, 1997Mar 28, 2000Lg Semicon Co., Ltd.Output pad circuit using control signal
US6119240 *May 27, 1999Sep 12, 2000Motorola, Inc.Low power data processing system for interfacing with an external device and method therefor
US6246259 *May 5, 1998Jun 12, 2001Xilinx, Inc.High-speed programmable logic architecture having active CMOS device drivers
Classifications
U.S. Classification326/86, 327/108
International ClassificationG06F3/00, H04L25/02, H03K17/687, G06F13/40, H03K19/094
Cooperative ClassificationH04L25/028, H03K19/09429, G06F13/4072
European ClassificationH04L25/02K7, H03K19/094M2, G06F13/40E2B
Legal Events
DateCodeEventDescription
Mar 31, 2003FPAYFee payment
Year of fee payment: 12
Apr 15, 1999FPAYFee payment
Year of fee payment: 8
May 30, 1995REMIMaintenance fee reminder mailed
Apr 3, 1995FPAYFee payment
Year of fee payment: 4
Nov 14, 1989ASAssignment
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:TOKUMARU, TAKEJI;KUDOU, TSUNEAKI;OMOTE, KAZUYUKI;REEL/FRAME:005176/0427
Effective date: 19891101