|Publication number||US5105288 A|
|Application number||US 07/598,493|
|Publication date||Apr 14, 1992|
|Filing date||Oct 16, 1990|
|Priority date||Oct 18, 1989|
|Publication number||07598493, 598493, US 5105288 A, US 5105288A, US-A-5105288, US5105288 A, US5105288A|
|Inventors||Koji Senda, Fumiaki Emoto, Eiji Fujii, Atsuya Yamamoto, Akira Nakamura|
|Original Assignee||Matsushita Electronics Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Referenced by (38), Classifications (15), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to a liquid crystal display apparatus and a method of driving the same. More particularly, this invention relates to a liquid crystal display apparatus provided with a display panel having two-dimensionally arranged pixels, and a method of driving such a display apparatus.
2. Description of the Prior Art
Generally, a conventional active matrix type liquid crystal display (LCD) apparatus has a number of pixels which are arranged in a matrix. FIG. 5 shows the sectional structure of a pixel 20 in a display panel of such an LCD apparatus. In the LCD apparatus shown in FIG. 5, two glass plates 11 and 12 are opposed to each other. On one surface of the glass plate 11, pixel electrodes 13 and signal lines 4 made of indium tin oxide (ITO) are formed, and, on the opposing surface of the other glass plate 12, a common electrode 15 made of ITO is formed. A black matrix 16 is formed on the common electrode 15. Usually, the black matrix 16 is made of a metal such as Cr. Between the two glass plates 11 and 12, a liquid crystal material 17 such as TN (Twisted Nematic) type liquid crystal is filled. Polarizing plates 18 and 19 are disposed on the outer surface of the glass plates 11 and 12, respectively. The liquid crystal disposed between the pixel electrode 13 and common electrode 15 can be simply considered as a light valve switch which is transparent when an adequate voltage is applied and opaque when no voltage is applied. When the LCD apparatus is of the normally black type, a voltage of the same level as that of the common electrode 15 is applied to the pixel electrode 13 of a pixel which is to be displayed as black, through the corresponding signal line 4, thereby making the liquid crystal 17 above the pixel electrode 13 opaque.
In such an active matrix type LCD apparatus of the prior art, when a white level area (area A of FIG. 4) is displayed so that as shown in FIG. 4 it is surrounded by black level areas (areas B-E of FIG. 4), the black level areas B and D which are above and below the white area A in FIG. 4 are not as sufficiently black as the other black level areas C and E. Namely, the gray scale of the black areas B and D has an intermediate value, while signals applied to the pixel electrodes 13 in the areas B and D have a level corresponding to black. This is caused by leakage light or smear (spurious) light due to crosstalk.
This will be described in more detail. When a signal voltage is applied to the pixel electrodes 13 in the area A via the corresponding signal lines 4 which extend in the areas B, A and D, the liquid crystal in the portion E (FIG. 5) which is disposed between the signal lines 4 and the common electrodes 15 also functions as a light valve switch, and becomes transparent. Therefore, light leaks through the liquid crystal in the portion E, resulting in that the gray scale of the areas B and D which should be displayed as black (i.e., the pixel electrodes 13 therein are not energized) becomes to have an intermediate value as a whole.
The LCD apparatus of this invention, which overcomes the above-discussed and numerous other disadvantages and deficiencies of the prior art, comprises pixels arranged in a matrix form; signal lines each for transferring image signals to each column of said pixels; and image signal means for supplying image signals to said signal lines, and further comprises: potential means for supplying a predetermined potential; a first connecting means for connecting said signal lines to said potential means during a first period of time, and for disconnecting said signal lines from said potential means for a second period of time; and a second connecting means for connecting said signal lines to said image signal means within said second period of time.
According to another aspect of this invention, a driving circuit for driving an LCD panel which comprises pixels arranged in a matrix form, a signal lines each for transferring image signals to each column of said pixels is provided. The driving circuit comprises: potential means for supplying a predetermined potential; a first connecting means for connecting said signal lines to said potential means during a first period of time, and for disconnecting said signal lines from said potential means for a second period of time; and a second connecting means for connecting said signal lines to said image signal means within said second period of time.
According to a further aspect of this invention, a method of driving an LCD apparatus which comprises: pixels arranged in a matrix form; signal lines each for transferring image signals to each column of said pixels; and image signal means for supplying image signals to said signal lines is provided. The method comprises the steps of: applying a predetermined potential to said signal lines during a first period of time; and transferring image signals to one row of said pixels through said signal lines within a second period of time.
In one preferred embodiment, said predetermined potential has a level by which the liquid crystal is driven to the black level.
Preferably, said predetermined potential pulsates.
Preferably, said apparatus further comprises storage means for holding said image signals, said storage means being connected between said image signal means and said second connecting means.
Preferably, each of said pixels comprises a storage capacitor for holding an image signal supplied from a corresponding one of said signal lines.
Preferably, said second period of time is the horizontal blanking period.
Thus, the invention described herein makes possible the objectives of:
(1) providing an LCD apparatus in which leakage of light does not occur;
(2) providing an LCD apparatus in which leakage of light through neighborhood of signal lines can be prevented;
(3) providing an LCD apparatus which is excellent in image quality;
(4) providing an LCD apparatus in which a black matrix is not required;
(5) providing a driving circuit for driving an LCD panel which can prevent leakage of light through the neighborhood of signal lines from occurring;
(6) providing a method of driving an LCD apparatus in which leakage of light does not occur; and
(7) providing a method of driving an LCD apparatus which can drive the LCD apparatus without leakage of light through the neighborhood of signal lines.
This invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawings as follows:
FIG. 1 is a circuit diagram illustrating an LCD apparatus according to the invention.
FIG. 2 is a timing chart illustrating the operation of the LCD apparatus of FIG. 1.
FIG. 3 shows a sectional structure of the LCD apparatus of FIG. 1.
FIG. 4 is a diagram illustrating a display in a conventional LCD apparatus.
FIG. 5 shows a sectional structure of a conventional LCD apparatus.
FIG. 6 shows waveforms of the reset voltage in pulse form.
FIG. 1 is a circuit diagram of an LCD apparatus according to the invention. The general structure of a pixel 20 of the display panel of this embodiment is shown in FIG. 3 wherein like numerals represent like components in FIG. 5. As seen from FIG. 3, the sectional structure of the display panel of this embodiment is constructed in substantially the same manner as that shown in FIG. 5, but the black matrix 16 is not formed. In this embodiment, the pixel 20 comprises a TFT 5 which functions as a switching element, and a storage capacitor 6. The pixel electrode 13 of each pixel 20 is connected to the drain of the TFT 5. The gates of the TFTs 5 for the pixels 20 of the nth row are connected to a gate signal line 7n, while the source of the TFTs 5 for the pixels 20 of the mth column are connected to a video signal line 4m. The gate signal line 7n is connected to an output φVn of a vertical scan circuit 9. The common electrode 15 is coupled to a voltage Vc of a predetermined level. Between the pixel electrode 13 and the next gate signal line 7n+1 for the (n+1)th row, a storage capacitor 6 is formed.
One end of the video signal line 4m is connected to a video input Is to which video signals are supplied, through a series connection of a transfer gate 3m and an analog switch 1m. The gate of the analog switch 1m is coupled to an output φHm of a horizontal scan circuit 10. The gate terminal of the transfer gate 3m is coupled to an input terminal φT to which a signal for activating the video signal line 4m. A capacitor 2m is formed between the ground and the junction point of the switch 1m and gate 3m. The other end of the video signal line 4m is connected to a reset voltage terminal VR through a reset switch 8m. The level of the reset voltage applied to the terminal VR (hereinafter, such a reset voltage also is referenced by VR) is selected so that, when the reset voltage VR is applied to the video signal line 4m, the liquid crystal disposed above the electrode 4m is "opaque". When the LCD apparatus is driven by the normally black drive method, therefore, the voltage level VR equals the voltage level applied to the common electrode 15 (i.e., VR =VC). The gate of the reset switch 8m is coupled to an input terminal φR to which a signal for activating the reset switch 8m. Although only two columns and two rows of pixels are shown in FIG. 1, actually, a number of pixels are arranged in a matrix form.
FIG. 2 shows waveforms appearing when the LCD apparatus of FIG. 1 is driven by the so-called "1H inverting drive method" in which the polarity of the video signal is inverted every horizontal scan period. In FIG. 2, Is ((a) of FIG. 2) is the waveform of the 1H inverted video signal input form the input terminal Is, φHm and φHM+1 ((b) and (c) of FIG. 2) are the waveforms of the respective pulse signals produced by the horizontal scan circuit 10 to drive the analog switches 1m and 1m+1, φT ((d) of FIG. 2) is the waveform of the pulse signal supplied to the terminal φT, φVn ((e) of FIG. 2) is the waveform of the pulse signal produced by the vertical scan circuit 9 to drive the TFTs 5 in the nth row, and φR ((f) of FIG. 2) is the waveform of the reset signal applied to the terminal φR to drive the reset switch 8m.
The operation of this LCD apparatus will be described with reference to FIG. 2.
First, at time t1 during a horizontal scanning period, the pulse signal φHm becomes high, and the analog switch 1m for the mth column is closed. Since the signal φT supplied to the gate of the transfer gate 3m is low at time t1, the transfer gate 3m remains closed. Consequently, the potential of the video signal Is appearing at time t1 is held by the capacitor 2m. The reset pulse φR is high and the reset switch 8m is closed, so that the potential of the signal line 4m, 4m+1, . . . is kept at the voltage level VR and the liquid crystal disposed above the electrode 4m, 4m+1, . . . is opaque. Next, at time t2, the pulse signal φHm+1 becomes high so that the analog switch 1m+1 for the (m+1)th column is closed, and the potential of the video signal Is at time t2 is held by the capacitor 2m+1. In this way, the potentials of the video signal Is at each time in the horizontal scanning period respectively are held in sequence in the capacitors 2m, 2m+1, . . . by the pulses φHm, φHm+1, . . . sequentially output from the horizontal scan circuit 10.
At the commencement of the horizontal blanking period (time t3), the reset pulse φR becomes low, and the reset switch 8m is turned off so that the voltage level VR becomes not to be applied to the signal line rm, 4m+1, . . . .
During the horizontal blanking period in the horizontal scanning period (time t4), the pulse signal φT applied to the gate of the transfer gates 3m, 3m+1, . . . becomes high, and the transfer gates 3m, 3m+1, . . . are closed. The potential of each of the signal lines 4m, 4m+1, . . . becomes the potential of the video signal held in the corresponding one of the capacitors 2m, 2m+1, . . . , in accordance with the capacitance distribution. In order to adequately accomplish this capacitance distribution, it is preferable that the capacitance of the capacitors 2m, 2m+1, . . . is set at a value sufficiently larger than the stray capacitance of the corresponding signal lines 4m, 4m+1, . . . . According to our experiments, preferably results were obtained by setting the capacitance of the capacitors 2m, 2m+1, . . . to 3 to 10 pF when the capacitance of the signal lines 4m, 4m+1, . . . was about 1 pF.
At the same time (time t4), the pulse signal φVn corresponding the nth row and output from the vertical scan circuit 9 via the gate signal line 7n becomes high. The TFTs 5 of the nth row are turned on so that the potentials of the video signals respectively stored in the capacitors 2m, 2m+1, . . . are transferred to the storage capacitors 6 of the respective pixels of the nth row, in accordance with the capacitance distribution.
At time t5 within the horizontal blanking period, both the pulse signals φT and φVn return to low level. The transfer gates 3m, 3m+1, . . . are opened to disconnect the capacitors 2m, 2m+1, . . . from the signal lines 4m 4m+1, . . . , and the TFTs 5 of the nth row are turned off. Therefore, the potentials of the video signals respectively stored in the storage capacitors 6 are held until the next write (one field or one frame later) so that the pixels of the nth row are driven to perform the display operation according to the video signals during one field.
Immediately before the commencement of the next horizontal scanning period (time t6), the reset pulse φR returns to high level, thereby keeping again the potential of the signal lines 4m, 4m+1, . . . at the level VR by which the liquid crystal disposed above the electrodes 4m, 4m+1, . . . is made opaque. During the next horizontal scanning period, video signals are transferred to the storage capacitors 6 of the pixels of the (n+1)th row in the same manner as described above.
According to this embodiment, therefore, even when a white level area is sandwiched or surrounded by a black level area(s) as shown in FIG. 4, the level of all the signal lines 4m, 4m+1, . . . is forcedly set during the majority portion (i.e., the period when the pulse signal φT is not active) of one horizontal scanning period to the value at which the liquid crystal 17 is opaque. In other words, the degree of leakage light a (FIG. 5) caused by the transparent state of liquid crystal above the signal lines 4m, 4m+1, . . . is decreased to about 1/10-1/100 as compared with that in a conventional apparatus (the value corresponds to the duty ratio of the inversion of the reset pulse φR). It can be said that according to this invention leakage of light can be substantially prevented from occurring.
When the LCD apparatus is driven in the normally white drive method, pulses the level of which alternatingly varies around the potential of the common electrode 15 by, for example, 0 V to 12 V (peak-peak), as shown in FIG. 6, are applied to the reset voltage terminal VR. By this means, portions corresponding to the signal lines 4m, 4m+1, . . . can be made sufficiently white, and unevenness in the display at the borderline with displayed pixels as eliminated.
According to this invention, leakage light can be suppressed to the extent that the black matrix 16 (FIG. 5), which is employed in a conventional LCD apparatus to suppress leakage light, is no longer necessary.
In the above, embodiments in which the 1H inverting drive method is used are described. The same effect can be achieved in an LCD apparatus according to the invention which is driven by another drive method such as the 1 V inverting drive method or 1-pixel inverting drive method. In this case, it is preferable that the reset voltage VR is a pulse signal. The frequency, pulse width, etc. of such a pulse signal may be adequately selected in accordance with the adopted drive method.
As described above, according to this invention, leakage light caused by the potential of the signal lines can be suppressed, and therefore it is extremely effective in improving the display quality of an LCD display apparatus.
It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art to which this invention pertains.
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|U.S. Classification||345/87, 345/94, 348/E03.015|
|International Classification||H04N3/12, G09G3/36, G09G3/20|
|Cooperative Classification||G09G2320/0209, G09G3/3648, G09G2310/0248, G09G3/2011, G09G3/3688, H04N3/127|
|European Classification||G09G3/36C14A, H04N3/12L, G09G3/36C8|
|Dec 5, 1990||AS||Assignment|
Owner name: MATSUSHITA ELECTRONICS CORPORATION, 1006, OHAZA KA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:SENDA, KOJI;EMOTO, EIJI;FUJII, EIJI;AND OTHERS;REEL/FRAME:005539/0014
Effective date: 19901126
|Sep 26, 1995||FPAY||Fee payment|
Year of fee payment: 4
|Oct 4, 1999||FPAY||Fee payment|
Year of fee payment: 8
|Jan 29, 2002||AS||Assignment|
|Oct 29, 2003||REMI||Maintenance fee reminder mailed|
|Apr 14, 2004||LAPS||Lapse for failure to pay maintenance fees|
|Jun 8, 2004||FP||Expired due to failure to pay maintenance fee|
Effective date: 20040414