|Publication number||US5117389 A|
|Application number||US 07/577,644|
|Publication date||May 26, 1992|
|Filing date||Sep 5, 1990|
|Priority date||Sep 5, 1990|
|Publication number||07577644, 577644, US 5117389 A, US 5117389A, US-A-5117389, US5117389 A, US5117389A|
|Inventors||Tom D. H. Yiu|
|Original Assignee||Macronix International Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (16), Non-Patent Citations (2), Referenced by (196), Classifications (16), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to read-only-memory (ROM) integrated circuit design, and particularly to high density, high performance read-only-memory circuits.
There are a number of basic ROM integrated circuit design approaches. One such approach has been referred to as the flat-cell design. The flat-cell design gives a very small area per storage unit cell (ROM cell) compared to other known design approaches.
In a flat-cell FET, unlike in the traditional LOCOS (Local Oxidation Silicon) approach to FET design, the width of the polysilicon word line defines the channel width of the FET, rather than the channel length. This allows a designer to pack the polysilicon lines in the ROM cores purely from the point of view of process limitations, rather than the FET device's physical limitations. Also, because there is no thermally grown field oxide in the core ROM cell region, there is no channel width reduction due to thermal field dopant encroachments, and no packing density loss due to birdsbeaks in the field oxide. This allows the very dense core array to be achieved.
However, the size of the ROM cell alone does not determine the size of ROM array formation. The circuitry required to access the ROM cell and other peripheral circuits also contribute to the overall size of the array.
Also, in a flat-cell ROM, the bit lines are accomplished with buried diffusion, which have relatively high resistance and capacitance associated with them. Thus, it is difficult to drive the buried diffusion lines quickly. In order to get around the speed problem with the buried diffusion bit lines, metal lines running parallel with the buried diffusion lines, and making contacts with them every so often are used in the prior art. However, the core ROM cell pitch becomes limited by the metal and contact pitches, rather than the basic transistor pitches, and loses packing advantages.
A prior art flat-cell ROM design can be found in Okada, et al., "16 Mb ROM Design Using Bank Select Architecture", Symposium on VLSI Circuits, Tokyo, Japan, Aug. 22-24, 1988, Digest of Technical Papers, on pp. 85-86. In the Okada publication, the flat-cell ROM array uses a bank select architecture, in which the basic ROM cells are NOR-connected flat-cell FETs laid out in columns. The bit lines are implemented as buried diffusion lines for each array. Metal lines corresponding to the data line and virtual ground are laid out over the ROM array, and connected to the buried diffusion bit lines through flat-cell FET bank select transistors, and metal-to-diffusion contacts. See also, European Patent Application No. 88306931.2 entitled "Semiconductor Memory Device and Process for Producing Same," by Ashida, et al., published Feb. 8, 1989.
In the Okada, et al., publication, each column of transistors in a local sub-array defines a bank. Each bank of transistors shares a metal data line and a metal virtual ground line with another bank. The ROM is laid out such that bank 0 and bank 1 share a virtual ground line, while banks 1 and 2 share a metal data line, banks 2 and 3 share the next virtual ground line, and so on. Each buried diffusion region in the Okada, et al. flat-cell ROM has a first bank transistor for connecting to the adjacent metal data line, and a second bank select transistor for connecting to the adjacent metal virtual ground line.
In the Okada design, the metal lines in the ROM array are not straight. Rather, they are laid out so that the metal at a first end of the column is aligned with a bank select transistor for the even bank, and the metal at the second end of the column is aligned with the bank select transistor for the odd bank. Also, the Okada design calls for one diffusion-to-metal contact per diffusion bit line. This crooked metal line, in particular, has an undesirable effect on yield of the integrated circuits because of difficulty in reliably laying out crooked conductors.
It is desirable to design a high performance ROM, while maintaining high packing densities offered by the flat-cell design technique, which can be manufactured with high yield.
The present invention provides a flat-cell ROM array which overcomes many of the problems of the prior art, by using isolated block select transistors, allowing for the layout of straight metal lines, while sharing the metal lines between even and odd banks, and achieving a very high density, high performance ROM.
The invention can be characterized as a memory circuit which comprises a semiconductor substrate. A plurality of parallel buried diffusion regions are deposited in the substrate to form local bit lines. A gate oxide is laid over the substrate. A plurality of polysilicon word lines are laid over the gate oxide perpendicular to the local bit lines, so that the areas between the respective pairs of buried diffusion regions and under the polysilicon word lines form channels of field effect transistors, whereby a column of ROM cells lies between each pair of buried diffusion local bit lines. An insulating layer is laid over the polysilicon word lines, and a plurality of metal data lines and virtual ground lines (global bit lines) is deposited. These metal lines are shared by even and odd columns of ROM cells, yet may be laid out straight.
Access to the metal lines from the local bit lines is made through a plurality of block select transistors, each having a drain connected to one of themetal lines, a source coupled to an adjacent one of the local bit lines, and a gate connected to receive a block select signal across a block select line. These block select transistors are implemented using LOCOS technology, or other technology which provides for isolating the block select transistor, to allow for faster switching.
According to one aspect of the invention, the block select transistors connect every other local bit line to the metal lines, with the alternate local bit lines coupled to local bit lines on the left and right with fixed coded flat-cell transistors termed bank select transistors. In response to left or right bank select signals, the alternate local bit line can be coupled to a virtual ground line or metal data line by way of a bank select transistor and the local bit line on its left or its right which is connected to the desired metal line by a block select transistor.
According to another aspect of the invention, isolated block select transistors are connected to each end of the alternate local bit lines for higher speed applications.
In summary, a new ROM array design technique has been provided. The ROM array uses flat-cell transistors in a virtual ground configuration to achieve very high density. The manner in which the ROM array is divided into sub-arrays achieves very high performance. The local diffused bit line structure achieves an easy interface to each bank of ROM cells, for easy processing and high yield.
The sub-arrays of flat-cells are selected by fully decoded block select lines through conventional isolated select transistors. Inside each sub-array, two fix coded rows of flat-cells decode left and right banks for access to shared straight metal bit lines.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description, and the claims which follows.
FIG. 1 is a schematic top view of the layout of a prior art flat-cell ROM core.
FIGS. 2A and 2B show cross sectional views of the prior art flat-cell ROM core illustrated in FIG. 1.
FIG. 3 is a circuit diagram of the prior art flat-cell ROM array illustrated in FIG. 1.
FIG. 4 is a circuit diagram of a ROM sub-array according to the present invention.
FIGS. 5, 6, and 7 illustrate the manufacturing process for implementing the flat-cell ROM, with isolated bank select transistors and shared metal global bit lines, according to the present invention.
FIG. 8 is a circuit diagram of an alternate ROM subarray according to the present invention.
A detailed description of the preferred embodiments of the present invention is described with reference to FIGS. 1-8. FIGS. 1-3 illustrate the flat-cell ROM layout and basic circuit of the prior art. FIG. 4 is a schematic diagram of one ROM sub-array according to the present invention. FIGS. 5-7 illustrate the layout of the ROM sub-array according to the present invention. FIG. 8 is a schematic diagram of a ROM sub-array according to the present invention with isolated block select transistors on each end of the local bit lines.
I. Flat Cell Design
The manufacturing technique for the flat-cell is illustrated in FIGS. 1, 2A, 2B, and 3. In FIG. 1, a schematic diagram of the layout from the top view of four-transistor flat-cell array is shown. The horizontal bars 10 and 11 are polysilicon word lines. The vertical bars 12, 13, and 14, are buried n+ diffusion regions. The regions C1, C2, C3 and C4 are the gate/channel regions of respective flat-cell transistors which store data, and form the ROM cell storage unit. In order to store 1 or 0 in each of the transistors, a mask ROM technique is used to lay down low enhancement or high enhancement type channels.
FIGS. 2A and 2B are cross sectional views of the flat-cell array of FIG. 1. FIG. 2A shows a cross section taken along the line 2A--2A in the polysilicon word line 10. As can be seen, the buried diffusion lines 12, 13, and 14 are deposited in the silicon substrate. A thin gate oxide 16 is deposited over the silicon substrate. Then polysilicon word lines are deposited over the gate oxide.
FIG. 2B shows a cross section of the array of FIG. 1, taken through along the line 2B--2B in the buried diffusion region 14. This illustrates the buried diffusion region 14 as a oontinuous n+ doped conductive bit line along the array. The gate oxide 16 is laid down over the buried diffusion regions, and the polysilicon word lines 10, 11 are deposited over the gate oxide.
FIG. 3 is a circuit diagram which represents the flat-cell structure, in which lines 10 and 11 correspond to the polysilicon word lines 10 and 11 of FIG. 1. Lines 12, 13, and 14 correspond to the buried diffusion bit lines 12, 13, and 14 in FIG. 1. The transistors M1, M2, M3, and M4 are defined by the gate regions which are doped by using mask programming techniques to store by ROM code implants either 1 or 0.
II. ROM Sub-Array Circuit
FIG. 4 is a circuit diagram of a ROM sub-array according to one embodiment of the present invention. The sub-array, designated N, includes a plurality of block select transistors M1-M5, implemented using LOCOS FET techniques so that they have good isolation from other components in the integrated circuit, and therefore, low capacitive loading and high switching speeds. Each block select transistor is coupled to a metal to diffusion contact 100-1 through 100-5 at its drain; its gate is connected to a block select word line BWLN ; and its source is coupled to a buried diffusion bit line 101-1, 101-3, 101-5, 101-7, and 101-9. The contacts 100-1 through 100-5 couple the drains of the block select transistors M1-M5 to a metal virtual ground line VGN or a metal data line BLN, such that the odd block select transistors M1, M3, M5 . . . are coupled to VGN metal lines, and the even block select transistors M2, M4 . . . are coupled to BLN metal lines.
The ROM cell array further includes the buried diffusion bit lines 101-0, 101-2, 101-4, 101-6 and 101-8, which are not coupled directly to block select transistors. Polysilicon word lines SWLN1 through SWLNM are laid perpendicular to the buried diffusion regions 101-0 through 101-9. In this manner, a ROM array is defined such that the buried diffusion regions each serve as the source of a first column of ROM cells, and as the drain of a second column of ROM cells.
Buried diffusion regions 101-1, 101-3, 101-5, 101-7 and 101-9, which are connected through block select transistors M1-M5 to the respective metal lines, are coupled to the buried diffusion regions on their left and on their right through bank left and bank right fixed ROM implant flat-cells, located at the end of the buried diffusion region opposite the contact 100-1 through 100-5. These fixed bank left and bank right select transistors can be located anywhere along the bank.
The bank left select transistors are labelled L1-L10 in FIG. 4. In this fixed code, transistors L1, L3, L5, L7, L9 are all made with a ROM code implant, causing the threshold voltage to be greater than certain voltages, e.g., six volts, so that in effect, transistors L1, L3, L5, L7, and L9 are always considered off. The transistors L2, L4, L6, L8, and L10 have a low threshold voltage and are turned on and off in response to the SBLN signal.
Similarly, bank right select transistors are labelled R1-R10. Transistors R1, R3, R5, R7, and R9 have a low threshold voltage. Therefore, they are turned on and off in response to the SBRN signal. The transistors R2, R4, R6, R8, and R10 have a ROM code implant which sets the threshold voltage greater than certain voltages, so that they are always considered off.
The sub-array illustrated in FIG. 4 includes columns of ROM cells labelled A-J. The columns A, C, E, G, and I, which are to the left of the diffusion regions 101-1, 101-3, 101-5, 101-7 and 101-9, respectively, are all sampled when the SBLN is asserted. For instance, the column C is sampled because the buried diffusion region 101-2 is coupled through the transistor L2 to the diffusion region 101-1. Diffusion region 101-1 is connected through transistor M1 to the metal line VGN. Diffusion region 101-3, which makes up the other side of column C, is connected directly to transistor M2 and to metal line BLN. The metal lines VGN and BLN are connected to sense circuitry, not shown.
Similarly, columns B, D, F, H, and J, are all accessed in response to assertion of the SBRN signal. For instance, column D is accessed when the SBRN is asserted, because diffusion region 101-4 is coupled through bank right select transistor R5 to diffusion region 101-5, and through block select transistor M3 to the metal line VGN+1. The diffusion region 101-3 is directly connected through block select transistor M2 to the metal line BLN. The metal line VGN+1 and BLN are connected to sense circuitry, not shown.
In sum, the local bit lines 101-1, 101-3, 101-5, 101-7, and 101-9 are connected through the fixed cells L1-L10 and R1-R10 to the local bit lines 101-0, 101-2, 101-4, 101-6, and 101-8. These local bit lines 101-1, 101-3, 101-5, 101-7, and 101-9 are connected to metal data lines via the block select transistors M1-M5, and metal to diffusion contacts 100-1 through 100-5. In this architecture, only every other buried diffusion region is connected directly to the metal data or virtual ground lines. Thus, two core cell pitches are allocated for each metal line pitch.
This architecture can be described in an index notation for a sub-array having N local bit lines as follows. It can be seen that there is a first plurality of isolated block select transistors M1, M3, M5, each having a drain connected to one of the global bit lines forming a virtual ground line, a source connected to a respective one of the local bit lines LBL4k+1 for k equal to 0 through (N-1)/4, (101-1, 101-5, 101-9), and a gate connected to the block select line BWLN.
Also there is a second plurality of isolated block select transistors M2, M4, each having a drain connected to one of the global bit lines forming metal bit lines, a source connected to a respective one of local bit lines LBL4k+3, for k equal to 0 through (N-1)/4, (101-3, 101-7), and a gate connected to the block select line BWLN.
Field oxide regions between adjacent block select transistors isolate the block select transistors.
The bank left select word line BLN and a bank right select word line BRN intersect the plurality of local bit lines and define bank left and bank right select transistors between each pair of local bit lines and under the bank left select and bank right select word lines. The bank left and bank right select transistors are fixed coded to couple local bit lines LBL4, for j equal to 0 through (N-1)/2, (101-0, 101-2, 101-4 . . . ) to a virtual ground line through LBL4k+1, for k equal to 0 through (N-1)/4, in response to energizing voltage on the bank left select word line and to couple local bit lines LBL4, for j equal to 0 through (N-1)/2, to a data line through LBL4k+3, for k equal to 0 through (N-1)/4, in response to energizing voltage on the bank right select word line.
As illustrated in FIG. 4, sub-array N-1 at the top of FIG. 4 has block select transistors M6-M10 coupled to the same contact points 100-1 through 100-5 as sub-array N. Similarly, sub-array N+1 at the bottom of FIG. 4 is arranged so that the fixed coded left and right bank select transistors are adjacent to the fixed coded left and right bank select transistors for array N. In this way, two sub-arrays share the same metal to diffusion contact, and an efficient layout for the overall chip is achieved. An alternative embodiment is illustrated in FIG. 8, as described below.
III. ROM Sub-Array Layout
FIGS. 5-7 illustrate the layout of the ROM cell array according to the embodiment of the present invention shown in FIG. 4. FIG. 5 highlights the metal lines, the metal to diffusion contacts, and the polysilicon word lines, which are superimposed on the buried diffusion regions. FIG. 6 highlights the contacts, and the block select transistors. FIG. 7 illustrates the layout of the local buried diffusion bit lines and the position of ROM code implants to establish the bank left and bank right selection. The layouts shown in the Figures are representative, and should be altered as suits the particular manufacturing process to be used.
As can be seen in FIG. 5, the metal lines 500, 501, and 502 are straight. Three metal lines 500, 501, and 502 are shared by six local buried diffusion bit lines 503-508. Also, the polysilicon word lines 509-1 through 509-M for the ROM cell array, the polysilicon word line 510 for the block select transistor and the polysilicon word lines 511-R and 511-L for the bank select transistors are shown. Diffusion to metal contacts 513, 514, and 515 are found at the top of FIG. 5.
FIG. 6 illustrates the implementation of the block select transistors. The polysilicon word line 510 for the block select transistor, the n+ implant region generally above line 512 which defines the block select transistors, and the active areas 516, 517, and 518 of such transistors are illustrated. Note that every other local buried diffusion region 504, 506, 508 extends into the source area of a block select transistor 516, 517, 518.
Also note that the channel length in the block select transistor is defined by the width of the polysilicon word line 510, which is one micron in the embodiment described. The channel width of these devices is defined by field oxide regions 519, 520, 521 between the active regions of the transistors. These oxides are grown using the LOCOS (Local Oxidation Silicon) process as is common for MOS FETs. See description in European Patent Application No. 88306931.2, cited in the Background section above.
FIG. 7 illustrates the layout of the local buried diffusion regions 503-507 and the ROM code implants 522-526 used for the "always off" left and right bank select transistors.
IV. Alternate ROM Sub-Array Circuit
FIG. 8 is a circuit diagram of a ROM sub-array according to an alternate embodiment of the present invention. This sub-array, designated N, includes a plurality of block select transistors M1-M5 and M11-M15, each implemented using LOCOS FET techniques so that they have good isolation from other components in the integrated circuit, and therefore, low capacitive loading and high speeds. Each block select transistor is coupled to a metal to diffusion contact 100-1 through 100-5 and 100-11 through 100-15, at its drain; its gate is connected to a block select word line BWLN ; and its source is coupled to a buried diffusion bit line 101-1, 101-3, 101-5, 101-7, and 101-9. The contacts 100-1 through 100-5 couple the drains of the block select transistors M1-M5 to a metal virtual ground line VGN or a metal data line BLN, such that the odd block select transistors, M1, M3, M5 . . . are coupled to VGN metal lines, and the even block select transistors M2, M4 . . . are coupled to BLN metal lines. Similarly, on the opposite end of the local bit lines, the contacts 100-11 through 100-15 couple the drains of block select transistors M11-M15 to a metal virtual ground line VGN or a metal data line BLN such that the odd bank select transistors M11, M13, M15 are coupled to the same virtual ground line VGN as odd bank select transistors M1, M3, and M5. Similarly, the even block select transistors, M12, M14 . . . are coupled to the metal bit line BLN, as are the even block select transistors M2 and M4.
The main difference between the embodiment of FIG. 4 and the embodiment of FIG. 8 resides in the use of block select transistors M11-M15 on the second end of the local bit lines. This increases the speed of the circuit significantly by reducing the average path length from a given ROM cell to a metal line. Note that the gates of all of the block select transistors M1-M5 and M11-M15 are coupled to a single block select word line BWLN. Otherwise, this ROM sub-array operates in the same manner as the ROM sub-array described with respect to FIG. 4.
Another difference between the sub-arrays of FIGS. 4 and 8 is that the bank left select flat cell transistors L1-L10 are located at the top of the banks in FIG. 8, rather than next to the bank right select flat cells R1-R10, as shown in FIG. 4. This illustrates that these bank left and bank right flat cells can be located anywhere along the array.
Other components in the circuit are labelled with the same reference numbers as shown in FIG. 4 and are not described again here.
It can be seen that the block select transistors M6-M10 for sub-array N-1 are located at the top of FIG. 8, and the block select transistors M16-M20 for sub-array N+1 are located at the bottom of the array. This achieves optimum sharing of metal to diffusion contacts.
In sum, the present invention provides a new ROM array scheme using flat-cell technology in a NOR virtual ground configuration to achieve very high density. The ROM array is divided into sub-arrays. The sub-arrays of flat-cells are selected by fully decoded block select lines through conventional LOCOS block select transistors. Inside each sub-array, two fix coded rows of flat-cells are used to decode left and right columns of cells. Use of the local buried diffusion bit lines together with the flat-cell transistors achieves shared metal bit line access with straight metal lines, and compact layout.
Overall, a high density, high performance and high yield ROM integrated circuit has been presented.
The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4145701 *||Aug 18, 1978||Mar 20, 1979||Hitachi, Ltd.||Semiconductor device|
|US4328563 *||Apr 2, 1980||May 4, 1982||Mostek Corporation||High density read only memory|
|US4342100 *||Jan 19, 1981||Jul 27, 1982||Texas Instruments Incorporated||Implant programmable metal gate MOS read only memory|
|US4384345 *||May 8, 1981||May 17, 1983||Fujitsu Limited||Read-only memory device|
|US4404654 *||Jan 29, 1981||Sep 13, 1983||Sharp Kabushiki Kaisha||Semiconductor device system|
|US4459687 *||Apr 2, 1982||Jul 10, 1984||Tokyo Shibaura Denki Kabushiki Kaisha||Integrated circuit having a multi-layer interconnection structure|
|US4482822 *||Jan 21, 1981||Nov 13, 1984||Sharp Kabushiki Kaisha||Semiconductor chip selection circuit having programmable level control circuitry using enhancement/depletion-mode MOS devices|
|US4592027 *||Feb 8, 1984||May 27, 1986||Sharp Kabushiki Kaisha||Read control circuit in a read only memory system|
|US4703453 *||Feb 15, 1983||Oct 27, 1987||Hitachi, Ltd.||Semiconductor memory with an improved dummy cell arrangement and with a built-in error correcting code circuit|
|US4707718 *||Jul 30, 1984||Nov 17, 1987||Hitachi, Ltd.||Read-only memory|
|US4709351 *||Dec 24, 1984||Nov 24, 1987||Hitachi, Ltd.||Semiconductor memory device having an improved wiring and decoder arrangement to decrease wiring delay|
|US4839860 *||Jan 17, 1986||Jun 13, 1989||Hitachi, Ltd.||Semiconductor device having head only memory with differential amplifier|
|US4949309 *||May 11, 1988||Aug 14, 1990||Catalyst Semiconductor, Inc.||EEPROM utilizing single transistor per cell capable of both byte erase and flash erase|
|US4989062 *||Jun 16, 1988||Jan 29, 1991||Fujitsu Limited||Semiconductor integrated circuit device having multilayer power supply lines|
|US4990999 *||Oct 3, 1989||Feb 5, 1991||Ricoh Company, Ltd.||Semiconductor memory device using high-density and high-speed MOS elements|
|EP0302659A1 *||Jul 27, 1988||Feb 8, 1989||Sharp Kabushiki Kaisha||Semiconductor memory device and process for producing same|
|1||Okada, et al.; "16 Mb ROM Design Using Bank Select Architecture"; Symposium on ULSI Circuits; Tokyo, Japan, Aug. 22-24, 1988; Digest of Technical Papers, pp. 85-86.|
|2||*||Okada, et al.; 16 Mb ROM Design Using Bank Select Architecture ; Symposium on ULSI Circuits; Tokyo, Japan, Aug. 22 24, 1988; Digest of Technical Papers, pp. 85 86.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5291435 *||Jan 7, 1993||Mar 1, 1994||Yu Shih Chiang||Read-only memory cell|
|US5341337 *||Sep 16, 1993||Aug 23, 1994||Sharp Kabushiki Kaisha||Semiconductor read only memory with paralleled selecting transistors for higher speed|
|US5392233 *||Dec 16, 1992||Feb 21, 1995||Kabushiki Kaisha Toshiba||Read only memory capable of realizing high-speed read operation|
|US5420818 *||Jan 3, 1994||May 30, 1995||Texas Instruments Incorporated||Static read only memory (ROM)|
|US5422844 *||Sep 24, 1993||Jun 6, 1995||National Semiconductor Corporation||Memory array with field oxide islands eliminated and method|
|US5453392 *||Dec 2, 1993||Sep 26, 1995||United Microelectronics Corporation||Process for forming flat-cell mask ROMS|
|US5467300 *||Jun 28, 1993||Nov 14, 1995||Creative Integrated Systems, Inc.||Grounded memory core for Roms, Eproms, and EEpproms having an address decoder, and sense amplifier|
|US5493527 *||Jan 9, 1995||Feb 20, 1996||United Micro Electronics Corporation||High density ROM with select lines|
|US5512504 *||Jan 9, 1995||Apr 30, 1996||National Semiconductor Corporation||Method of making a memory array with field oxide islands eliminated|
|US5571739 *||Jul 3, 1995||Nov 5, 1996||United Microelectronics Corporation||Method for fabricating a read-only-memory (ROM) using a new ROM code mask process|
|US5597753 *||Dec 27, 1994||Jan 28, 1997||United Microelectronics Corporation||CVD oxide coding method for ultra-high density mask read-only-memory (ROM)|
|US5600586 *||Jul 25, 1994||Feb 4, 1997||Aplus Integrated Circuits, Inc.||Flat-cell ROM and decoder|
|US5621697 *||Jun 23, 1995||Apr 15, 1997||Macronix International Co., Ltd.||High density integrated circuit with bank select structure|
|US5623443 *||Mar 11, 1994||Apr 22, 1997||Waferscale Integration, Inc.||Scalable EPROM array with thick and thin non-field oxide gate insulators|
|US5663903 *||Jul 28, 1995||Sep 2, 1997||Utron Technology Inc.||Flat-cell read-only memory|
|US5675529 *||Jul 7, 1995||Oct 7, 1997||Sun Microsystems, Inc.||Fast access memory array|
|US5677867 *||Jun 30, 1995||Oct 14, 1997||Hazani; Emanuel||Memory with isolatable expandable bit lines|
|US5691216 *||May 30, 1995||Nov 25, 1997||Macronix International Co., Ltd.||Integrated circuit self-aligning process and apparatus|
|US5719806 *||Jul 8, 1993||Feb 17, 1998||Yamane; Masatoshi||Memory cell array|
|US5732012 *||Mar 17, 1994||Mar 24, 1998||Sgs-Thomson Microelectronics, S.R.L.||Rom cell with reduced drain capacitance|
|US5732013 *||Jan 8, 1997||Mar 24, 1998||Siemens Aktiengesellschaft||Matrix memory (virtual ground)|
|US5761119 *||Jul 12, 1994||Jun 2, 1998||Kabushiki Kaisha Toshiba||Nonvolatile semiconductor memory with a plurality of erase decoders connected to erase gates|
|US5767553 *||May 15, 1996||Jun 16, 1998||United Microelectronics Corporation||Flat cell mask ROM having compact select transistor structure|
|US5793086 *||Dec 23, 1996||Aug 11, 1998||Sgs-Thomson Microelectronics, S.R.L.||NOR-type ROM with LDD cells and process of fabrication|
|US5793666 *||Mar 25, 1997||Aug 11, 1998||Nec Corporation||Single-chip memory system having an array of read-only memory cells|
|US5811862 *||Oct 28, 1997||Sep 22, 1998||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device having a mask programmable memory and manufacturing method thereof|
|US5825683 *||Oct 29, 1997||Oct 20, 1998||Utron Technology Inc.||Folded read-only memory|
|US5889711 *||Oct 27, 1997||Mar 30, 1999||Macronix International Co., Ltd.||Memory redundancy for high density memory|
|US5898632 *||Feb 20, 1998||Apr 27, 1999||Lg Semicon Co., Ltd.||Sense amplifier of virtual ground flat-cell|
|US5910016 *||Feb 25, 1997||Jun 8, 1999||Waferscale Integration, Inc.||Scalable EPROM array|
|US5914906 *||Dec 20, 1995||Jun 22, 1999||International Business Machines Corporation||Field programmable memory array|
|US5949704 *||Sep 10, 1996||Sep 7, 1999||Macronix International Co., Ltd.||Stacked read-only memory|
|US5949719 *||Nov 12, 1998||Sep 7, 1999||International Business Machines Corporation||Field programmable memory array|
|US5966327 *||Jan 28, 1998||Oct 12, 1999||Lg Semicon Co., Ltd.||On-off current ratio improving circuit for flat-cell array|
|US5986914 *||Jun 7, 1995||Nov 16, 1999||Stmicroelectronics, Inc.||Active hierarchical bitline memory architecture|
|US6023421 *||Nov 12, 1998||Feb 8, 2000||International Business Machines Corporation||Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array|
|US6038192 *||Nov 10, 1998||Mar 14, 2000||International Business Machines Corporation||Memory cells for field programmable memory array|
|US6044031 *||Nov 12, 1998||Mar 28, 2000||International Business Machines Corporation||Programmable bit line drive modes for memory arrays|
|US6075745 *||Nov 12, 1998||Jun 13, 2000||International Business Machines Corporation||Field programmable memory array|
|US6084794 *||May 28, 1999||Jul 4, 2000||Winbond Electronics Corp.||High speed flat-cell mask ROM structure with select lines|
|US6091645 *||Nov 12, 1998||Jul 18, 2000||International Business Machines Corporation||Programmable read ports and write ports for I/O buses in a field programmable memory array|
|US6118707 *||Nov 10, 1998||Sep 12, 2000||International Business Machines Corporation||Method of operating a field programmable memory array with a field programmable gate array|
|US6130854 *||Nov 12, 1998||Oct 10, 2000||International Business Machines Corporation||Programmable address decoder for field programmable memory array|
|US6150700 *||Jan 19, 1999||Nov 21, 2000||Samsung Electronics Co., Ltd.||Advanced nor-type mask ROM|
|US6180979||Mar 3, 1997||Jan 30, 2001||Siemens Aktiengesellschaft||Memory cell arrangement with vertical MOS transistors and the production process thereof|
|US6233191||Feb 22, 2000||May 15, 2001||International Business Machines Corporation||Field programmable memory array|
|US6251732||Aug 10, 1999||Jun 26, 2001||Macronix International Co., Ltd.||Method and apparatus for forming self-aligned code structures for semi conductor devices|
|US6278649||Jun 30, 2000||Aug 21, 2001||Macronix International Co., Ltd.||Bank selection structures for a memory array, including a flat cell ROM array|
|US6385088 *||Feb 13, 1996||May 7, 2002||Sony Corporation||Non-volatile memory device|
|US6430077 *||Mar 28, 2000||Aug 6, 2002||Saifun Semiconductors Ltd.||Method for regulating read voltage level at the drain of a cell in a symmetric array|
|US6430079 *||Aug 2, 2001||Aug 6, 2002||Megawin Technology Co., Ltd.||Flat memory cell read only memory|
|US6459119 *||Nov 8, 1999||Oct 1, 2002||Macronix International Co., Ltd.||Contact array structure for buried type transistor|
|US6480422||Jun 14, 2001||Nov 12, 2002||Multi Level Memory Technology||Contactless flash memory with shared buried diffusion bit line architecture|
|US6525361||Nov 19, 1999||Feb 25, 2003||Macronix International Co., Ltd.||Process and integrated circuit for a multilevel memory cell with an asymmetric drain|
|US6531887||Jun 1, 2001||Mar 11, 2003||Macronix International Co., Ltd.||One cell programmable switch using non-volatile cell|
|US6545504||Jun 1, 2001||Apr 8, 2003||Macronix International Co., Ltd.||Four state programmable interconnect device for bus line and I/O pad|
|US6570810||Apr 20, 2001||May 27, 2003||Multi Level Memory Technology||Contactless flash memory with buried diffusion bit/virtual ground lines|
|US6577161||Jun 1, 2001||Jun 10, 2003||Macronix International Co., Ltd.||One cell programmable switch using non-volatile cell with unidirectional and bidirectional states|
|US6577536 *||Mar 4, 2002||Jun 10, 2003||Macronix International Co., Ltd.||Flat-cell nonvolatile semiconductor memory|
|US6587387 *||Jan 22, 2002||Jul 1, 2003||Macronix International Co., Ltd.||Device and method for testing mask ROM for bitline to bitline isolation leakage|
|US6614692||Jan 18, 2001||Sep 2, 2003||Saifun Semiconductors Ltd.||EEPROM array and method for operation thereof|
|US6633496||Dec 4, 2000||Oct 14, 2003||Saifun Semiconductors Ltd.||Symmetric architecture for memory cells having widely spread metal bit lines|
|US6633499||Mar 28, 2000||Oct 14, 2003||Saifun Semiconductors Ltd.||Method for reducing voltage drops in symmetric array architectures|
|US6636440||Apr 25, 2001||Oct 21, 2003||Saifun Semiconductors Ltd.||Method for operation of an EEPROM array, including refresh thereof|
|US6642587 *||Aug 7, 2002||Nov 4, 2003||National Semiconductor Corporation||High density ROM architecture|
|US6643181||Oct 24, 2001||Nov 4, 2003||Saifun Semiconductors Ltd.||Method for erasing a memory cell|
|US6653692 *||Apr 3, 2002||Nov 25, 2003||Holtek Semiconductor Inc.||Double access path mask ROM cell structure|
|US6677805||Apr 5, 2001||Jan 13, 2004||Saifun Semiconductors Ltd.||Charge pump stage with body effect minimization|
|US6731539||Apr 4, 2003||May 4, 2004||Sau Ching Wong||Memory with offset bank select cells at opposite ends of buried diffusion lines|
|US6771528||Feb 28, 2002||Aug 3, 2004||Samsung Electronics Co., Ltd.||Memory cell structure of metal programmable read only memory having bit cells with a shared transistor cell|
|US6788111||Oct 18, 2002||Sep 7, 2004||Macronix International Co., Ltd.||One cell programmable switch using non-volatile cell|
|US6826107||Aug 1, 2002||Nov 30, 2004||Saifun Semiconductors Ltd.||High voltage insertion in flash memory cards|
|US6829172||May 28, 2002||Dec 7, 2004||Saifun Semiconductors Ltd.||Programming of nonvolatile memory cells|
|US6853557 *||Sep 20, 2000||Feb 8, 2005||Rambus, Inc.||Multi-channel memory architecture|
|US6864739||Dec 22, 2003||Mar 8, 2005||Saifun Semiconductors Ltd.||Charge pump stage with body effect minimization|
|US6885585||Dec 20, 2001||Apr 26, 2005||Saifun Semiconductors Ltd.||NROM NOR array|
|US6888757||Sep 8, 2003||May 3, 2005||Saifun Semiconductors Ltd.||Method for erasing a memory cell|
|US6917544||Jul 10, 2002||Jul 12, 2005||Saifun Semiconductors Ltd.||Multiple use memory chip|
|US6928001||Dec 7, 2000||Aug 9, 2005||Saifun Semiconductors Ltd.||Programming and erasing methods for a non-volatile memory cell|
|US6937521||May 28, 2002||Aug 30, 2005||Saifun Semiconductors Ltd.||Programming and erasing methods for a non-volatile memory cell|
|US6975536||Aug 5, 2002||Dec 13, 2005||Saifun Semiconductors Ltd.||Mass storage array and methods for operation thereof|
|US7061801||Feb 13, 2004||Jun 13, 2006||Samsung Electronics Co., Ltd.||Contactless bidirectional nonvolatile memory|
|US7075809 *||Jun 16, 2004||Jul 11, 2006||Samsung Electronics Co., Ltd.||Memory cell structure of metal programmable read only memory having bit cells with a shared transistor cell|
|US7177998||Jan 18, 2006||Feb 13, 2007||Rambus Inc.||Method, system and memory controller utilizing adjustable read data delay settings|
|US7180788 *||Jan 7, 2005||Feb 20, 2007||Renesas Technology Corp.||Nonvolatile semiconductor memory device|
|US7200055||Sep 1, 2005||Apr 3, 2007||Rambus Inc.||Memory module with termination component|
|US7209397||Mar 31, 2005||Apr 24, 2007||Rambus Inc.||Memory device with clock multiplier circuit|
|US7210016||Nov 15, 2005||Apr 24, 2007||Rambus Inc.||Method, system and memory controller utilizing adjustable write data delay settings|
|US7221138||Sep 27, 2005||May 22, 2007||Saifun Semiconductors Ltd||Method and apparatus for measuring charge pump output current|
|US7225292||Sep 1, 2005||May 29, 2007||Rambus Inc.||Memory module with termination component|
|US7225311||Dec 11, 2003||May 29, 2007||Rambus Inc.||Method and apparatus for coordinating memory operations among diversely-located memory components|
|US7227779||Apr 26, 2006||Jun 5, 2007||Samsung Electronics Co., Ltd.||Contactless bidirectional nonvolatile memory|
|US7301831||Sep 15, 2004||Nov 27, 2007||Rambus Inc.||Memory systems with variable delays for write data signals|
|US7317633||Jul 5, 2005||Jan 8, 2008||Saifun Semiconductors Ltd||Protection of NROM devices from charge damage|
|US7352627||Jan 3, 2006||Apr 1, 2008||Saifon Semiconductors Ltd.||Method, system, and circuit for operating a non-volatile memory array|
|US7369440||Jan 19, 2006||May 6, 2008||Saifun Semiconductors Ltd.||Method, circuit and systems for erasing one or more non-volatile memory cells|
|US7405969||Aug 1, 2006||Jul 29, 2008||Saifun Semiconductors Ltd.||Non-volatile memory cell and non-volatile memory devices|
|US7420848||Jan 9, 2006||Sep 2, 2008||Saifun Semiconductors Ltd.||Method, system, and circuit for operating a non-volatile memory array|
|US7457183||Oct 16, 2006||Nov 25, 2008||Saifun Semiconductors Ltd.||Operating array cells with matched reference cells|
|US7466594||Jul 19, 2006||Dec 16, 2008||Saifun Semiconductors Ltd.||Dynamic matching of signal path and reference path for sensing|
|US7468926||Jan 19, 2006||Dec 23, 2008||Saifun Semiconductors Ltd.||Partial erase verify|
|US7480166||May 30, 2006||Jan 20, 2009||Samsung Electronics Co., Ltd.||Memory cell structure of metal programmable read only memory having bit cells with a shared transistor cell|
|US7480193||May 8, 2007||Jan 20, 2009||Rambus Inc.||Memory component with multiple delayed timing signals|
|US7484064||Oct 22, 2001||Jan 27, 2009||Rambus Inc.||Method and apparatus for signaling between devices of a memory system|
|US7512009||Apr 27, 2006||Mar 31, 2009||Saifun Semiconductors Ltd.||Method for programming a reference cell|
|US7518908||May 28, 2002||Apr 14, 2009||Saifun Semiconductors Ltd.||EEPROM array and method for operation thereof|
|US7519757||Mar 26, 2007||Apr 14, 2009||Rambus Inc.||Memory system having a clock line and termination|
|US7522443||Jul 15, 2005||Apr 21, 2009||Solomon Systech Limited||Flat-cell read-only memory structure|
|US7523244||Jul 25, 2006||Apr 21, 2009||Rambus Inc.||Memory module having memory devices on two sides|
|US7523246||Mar 2, 2007||Apr 21, 2009||Rambus Inc.||Memory system having memory devices on two sides|
|US7523247||Mar 8, 2007||Apr 21, 2009||Rambus Inc.||Memory module having a clock line and termination|
|US7532529||Aug 14, 2006||May 12, 2009||Saifun Semiconductors Ltd.||Apparatus and methods for multi-level sensing in a memory array|
|US7535765||Jul 10, 2007||May 19, 2009||Saifun Semiconductors Ltd.||Non-volatile memory device and method for reading cells|
|US7590001||Dec 18, 2007||Sep 15, 2009||Saifun Semiconductors Ltd.||Flash memory with optimized write sector spares|
|US7605579||Nov 21, 2006||Oct 20, 2009||Saifun Semiconductors Ltd.||Measuring and controlling current consumption and output current of charge pumps|
|US7638835||Dec 28, 2006||Dec 29, 2009||Saifun Semiconductors Ltd.||Double density NROM with nitride strips (DDNS)|
|US7638850||May 24, 2006||Dec 29, 2009||Saifun Semiconductors Ltd.||Non-volatile memory structure and method of fabrication|
|US7668017||Aug 17, 2005||Feb 23, 2010||Saifun Semiconductors Ltd.||Method of erasing non-volatile memory cells|
|US7675782||Oct 17, 2006||Mar 9, 2010||Saifun Semiconductors Ltd.||Method, system and circuit for programming a non-volatile memory array|
|US7692961||Aug 2, 2006||Apr 6, 2010||Saifun Semiconductors Ltd.||Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection|
|US7701779||Sep 11, 2006||Apr 20, 2010||Sajfun Semiconductors Ltd.||Method for programming a reference cell|
|US7724590||Oct 6, 2008||May 25, 2010||Rambus Inc.||Memory controller with multiple delayed timing signals|
|US7738304||Oct 11, 2005||Jun 15, 2010||Saifun Semiconductors Ltd.||Multiple use memory chip|
|US7743230||Feb 12, 2007||Jun 22, 2010||Saifun Semiconductors Ltd.||Memory array programming circuit and a method for using the circuit|
|US7760554||Aug 2, 2006||Jul 20, 2010||Saifun Semiconductors Ltd.||NROM non-volatile memory and mode of operation|
|US7786512||Jul 18, 2006||Aug 31, 2010||Saifun Semiconductors Ltd.||Dense non-volatile memory array and method of fabrication|
|US7808818||Dec 28, 2006||Oct 5, 2010||Saifun Semiconductors Ltd.||Secondary injection for NROM|
|US7870322||Apr 17, 2009||Jan 11, 2011||Rambus Inc.||Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices|
|US7964459||Dec 10, 2009||Jun 21, 2011||Spansion Israel Ltd.||Non-volatile memory structure and method of fabrication|
|US8045407||Apr 8, 2010||Oct 25, 2011||Rambus Inc.||Memory-write timing calibration including generation of multiple delayed timing signals|
|US8053812||Mar 13, 2006||Nov 8, 2011||Spansion Israel Ltd||Contact in planar NROM technology|
|US8214575||Dec 21, 2010||Jul 3, 2012||Rambus Inc.||Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices|
|US8214616||May 29, 2007||Jul 3, 2012||Rambus Inc.||Memory controller device having timing offset capability|
|US8218382||Sep 8, 2011||Jul 10, 2012||Rambus Inc.||Memory component having a write-timing calibration mode|
|US8253452||Feb 21, 2006||Aug 28, 2012||Spansion Israel Ltd||Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same|
|US8320202||Jun 25, 2007||Nov 27, 2012||Rambus Inc.||Clocked memory system with termination component|
|US8359445||Jan 27, 2009||Jan 22, 2013||Rambus Inc.||Method and apparatus for signaling between devices of a memory system|
|US8363493||Jul 9, 2012||Jan 29, 2013||Rambus Inc.||Memory controller having a write-timing calibration mode|
|US8364878||Feb 3, 2012||Jan 29, 2013||Rambus Inc.||Memory module having signal lines configured for sequential arrival of signals at a plurality of memory devices|
|US8391039||Nov 15, 2005||Mar 5, 2013||Rambus Inc.||Memory module with termination component|
|US8395951||May 2, 2012||Mar 12, 2013||Rambus Inc.||Memory controller|
|US8462566||Apr 29, 2008||Jun 11, 2013||Rambus Inc.||Memory module with termination component|
|US8493802||Jan 14, 2013||Jul 23, 2013||Rambus Inc.||Memory controller having a write-timing calibration mode|
|US8537601||Jul 6, 2012||Sep 17, 2013||Rambus Inc.||Memory controller with selective data transmission delay|
|US8625371||Jun 21, 2013||Jan 7, 2014||Rambus Inc.||Memory component with terminated and unterminated signaling inputs|
|US8717837||May 22, 2013||May 6, 2014||Rambus Inc.||Memory module|
|US8743636||May 9, 2013||Jun 3, 2014||Rambus Inc.||Memory module having a write-timing calibration mode|
|US8760944||Jun 21, 2013||Jun 24, 2014||Rambus Inc.||Memory component that samples command/address signals in response to both edges of a clock signal|
|US9053778||Dec 12, 2013||Jun 9, 2015||Rambus Inc.||Memory controller that enforces strobe-to-strobe timing offset|
|US9229470||May 1, 2014||Jan 5, 2016||Rambus Inc.||Memory controller with clock-to-strobe skew compensation|
|US9269405 *||Nov 4, 2014||Feb 23, 2016||Mediatek Inc.||Switchable bit-line pair semiconductor memory|
|US9311976||Oct 26, 2014||Apr 12, 2016||Rambus Inc.||Memory module|
|US9437279||Nov 24, 2015||Sep 6, 2016||Rambus Inc.||Memory controller with clock-to-strobe skew compensation|
|US9472262||Mar 15, 2016||Oct 18, 2016||Rambus Inc.||Memory controller|
|US20020121532 *||Feb 28, 2002||Sep 5, 2002||Timpte Inc.||Belt trap door closure|
|US20020181269 *||Feb 28, 2002||Dec 5, 2002||Jeung Seong-Ho|
|US20030072192 *||May 28, 2002||Apr 17, 2003||Ilan Bloom||Programming of nonvolatile memory cells|
|US20030117861 *||Dec 20, 2001||Jun 26, 2003||Eduardo Maayan||NROM NOR array|
|US20040008541 *||Jul 10, 2002||Jan 15, 2004||Eduardo Maayan||Multiple use memory chip|
|US20040022113 *||Aug 1, 2002||Feb 5, 2004||Ran Dvir||High voltage insertion in flash memory cards|
|US20040054845 *||Oct 22, 2001||Mar 18, 2004||Rambus, Inc.||Method and apparatus for signaling between devices of a memory system|
|US20040130385 *||Dec 22, 2003||Jul 8, 2004||Shor Joseph S.||Charge pump stage with body effect minimization|
|US20040170072 *||Dec 11, 2003||Sep 2, 2004||Rambus Inc.||Method and apparatus for coordinating memory operations among diversely-located memory components|
|US20040222437 *||Dec 7, 2000||Nov 11, 2004||Dror Avni||Programming and erasing methods for an NROM array|
|US20050018465 *||Jun 16, 2004||Jan 27, 2005||Jeung Seong-Ho|
|US20050162885 *||Jan 7, 2005||Jul 28, 2005||Kenji Kanamitsu||Nonvolatile semiconductor memory device|
|US20060007761 *||Sep 1, 2005||Jan 12, 2006||Ware Frederick A||Memory module with termination component|
|US20060036803 *||Aug 16, 2004||Feb 16, 2006||Mori Edan||Non-volatile memory device controlled by a micro-controller|
|US20060039174 *||Sep 1, 2005||Feb 23, 2006||Ware Frederick A||Memory module with termination component|
|US20060056244 *||Sep 15, 2004||Mar 16, 2006||Ware Frederick A||Memory systems with variable delays for write data signals|
|US20060069895 *||Nov 15, 2005||Mar 30, 2006||Ware Frederick A||Method, system and memory controller utilizing adjustable write data delay settings|
|US20060129776 *||Jan 18, 2006||Jun 15, 2006||Ware Frederick A||Method, system and memory controller utilizing adjustable read data delay settings|
|US20060193191 *||Apr 26, 2006||Aug 31, 2006||Wong Sau C||Contactless bidirectional nonvolatile memory|
|US20060215436 *||May 30, 2006||Sep 28, 2006||Jeung Seong-Ho|
|US20060277345 *||Jul 25, 2006||Dec 7, 2006||Haw-Jyh Liaw||High Frequency Bus System|
|US20060285402 *||Aug 14, 2006||Dec 21, 2006||Saifun Semiconductors Ltd.||Apparatus and methods for multi-level sensing in a memory array|
|US20070014142 *||Jul 15, 2005||Jan 18, 2007||Solomon Systech Limited||Flat-cell read-only memory structure|
|US20070150635 *||Mar 2, 2007||Jun 28, 2007||Haw-Jyh Liaw||Memory System Having Memory Devices on Two Sides|
|US20070150636 *||Mar 8, 2007||Jun 28, 2007||Haw-Jyh Liaw||Memory Module Having a Clock Line and Termination|
|US20070156943 *||Mar 12, 2007||Jul 5, 2007||Haw-Jyh Liaw||Memory Module Having a Clock Line and Termination|
|US20070206429 *||May 8, 2007||Sep 6, 2007||Ware Frederick A||Memory component with multiple delayed timing signals|
|US20070216800 *||Mar 26, 2007||Sep 20, 2007||Haw-Jyh Liaw||Memory System Having a Clock Line and Termination|
|US20070247935 *||Jun 25, 2007||Oct 25, 2007||Ware Frederick A||Clocked Memory System with Termination Component|
|US20070255889 *||Mar 22, 2007||Nov 1, 2007||Yoav Yogev||Non-volatile memory device and method of operating the device|
|US20070255919 *||May 29, 2007||Nov 1, 2007||Ware Frederick A||Memory controller device having timing offset capability|
|US20090063890 *||Oct 6, 2008||Mar 5, 2009||Ware Frederick A||Memory controller with multiple delayed timing signals|
|US20090210604 *||Apr 17, 2009||Aug 20, 2009||Haw-Jyh Liaw||Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at Synchronous Memory Devices|
|US20100188911 *||Apr 8, 2010||Jul 29, 2010||Ware Frederick A||Memory-write timing calibration including generation of multiple delayed timing signals|
|US20110090727 *||Dec 21, 2010||Apr 21, 2011||Haw-Jyh Liaw||Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at Synchronous Memory Devices|
|CN1321460C *||Oct 18, 2001||Jun 13, 2007||旺宏电子股份有限公司||High-density mask type non-volatility memory array structure with flat zone-block selected transistor|
|DE19609678A1 *||Mar 12, 1996||Sep 18, 1997||Siemens Ag||Speicherzellenanordnung und Verfahren zu deren Herstellung|
|DE19609678C2 *||Mar 12, 1996||Apr 17, 2003||Infineon Technologies Ag||Speicherzellenanordnung mit streifenförmigen, parallel verlaufenden Gräben und vertikalen MOS-Transistoren und Verfahren zu deren Herstellung|
|EP0783169A2 *||Nov 28, 1996||Jul 9, 1997||Siemens Aktiengesellschaft||Virtual ground array memory|
|EP0845811A2 *||Nov 26, 1997||Jun 3, 1998||Motorola, Inc.||A read only memory array and a method of manufacturing the array|
|EP0913868A1 *||Oct 31, 1997||May 6, 1999||Macronix International Co., Ltd.||Memory redundancy circuit for high density memory|
|EP0925609A1 *||Sep 10, 1996||Jun 30, 1999||Macronix International Co., Ltd.||Stacked read-only memory|
|U.S. Classification||365/104, 257/390, 365/184, 365/178, 257/E27.102|
|International Classification||H01L21/8246, H01L27/10, H01L27/108, G11C17/12, H01L21/316, H01L21/8242, H01L27/112|
|Cooperative Classification||H01L27/112, G11C17/126|
|European Classification||G11C17/12V, H01L27/112|
|Oct 29, 1990||AS||Assignment|
Owner name: MACRONIX INTERNATIONAL CO., LTD., 3F, NO. 56, PARK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:YIU, TOM DANG-HSING;REEL/FRAME:005500/0116
Effective date: 19901016
|Nov 6, 1995||FPAY||Fee payment|
Year of fee payment: 4
|Nov 24, 1999||FPAY||Fee payment|
Year of fee payment: 8
|Nov 26, 2003||FPAY||Fee payment|
Year of fee payment: 12